Datasheet CXD2587Q Datasheet (Sony)

Description

The CXD2587Q is a digital signal processor LSI for CD players. This LSI incorporates a digital servo, digital filter, zero detection circuit, 1-bit DAC and analog low-pass filter.

Features Digital Signal Processor (DSP) Block

• 1×, 2×, 4× speed playback supported

• 16K-RAM

• EFM data demodulation

• Enhanced EFM frame sync signal protection

• SEC strategy-based error correction

• Subcode demodulation and Sub Q data error

detection

• Digital spindle servo

• 16-bit traverse counter

• Asymmetry compensation circuit

• CPU interface on serial bus

• Error correction monitor signal, etc. output from a

new CPU interface

• Servo auto sequencer

• Digital audio interface outputs

• Digital level meter, peak meter

• CD TEXT data demodulation Digital Servo (DSSP) Block

• Microcomputer software-based flexible servo control

• Offset cancel function for servo error signal

• Auto gain control function for servo loop

• E:F balance, focus bias adjustment function

• Surf jump function supporting micro two-axis Digital Filter, DAC and Analog Low-pass Filter Blocks

• DBB (digital bass boost) function

• Double-speed playback supported

• Digital de-emphasis

• Digital attenuation

• 8Fs oversampling filter

• S/N: 100dB or more (master clock: 384Fs, typ.)

Logical value 109dB

• THD + N: 0.007% or less (master clock 384Fs, typ.)

• Rejection band attenuation: –60dB or less

Applications

CD players

Structure

Silicon gate CMOS IC

Absolute Maximum Ratings

• Supply voltage VDD –0.3 to +7.0 V

• Input voltage VI –0.3 to +7.0 V

(VSS – 0.3V to VDD + 0.3V)

• Output voltage VO –0.3 to +7.0 V

• Storage temperature Tstg –40 to +125 °C

• Supply voltage difference

VSS – AVSS –0.3 to +0.3 V VDD – AVDD –0.3 to +0.3 V

Note) AVDD includes XVDD and AVSS includes XVSS.

Recommended Operating Conditions

• Supply voltage VDD

∗

3.0 to 4.0 V

• Operating temperature Topr –20 to +75 °C

∗

The VDD for the CXD2587Q varies according to the playback speed.

I/O Capacitance

• Input pin CI 11 (Max.) pF

• Output pin CO 11 (Max.) pF

• I/O pin CI/O 11 (Max.) pF

Note) Measurement conditions VDD = VI = 0V

fM = 1MHz

– 1 –

CXD2587Q

E97518-PS

CD Digital Signal Processor with Built-in Digital Servo and DAC

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

80 pin LQFP (Plastic)

Playback speed

CD-DSP block

DAC block

4×

4.75 to 5.25

2×

3.0 to 5.5 4.5 to 5.5

1×

2.7 to 5.5 2.7 to 5.5

VDD [V]

For the availability of this product, please contact the sales office.

– 2 –

CXD2587Q

Block Diagram

PWM PWM

AOUT1

AIN1 LOUT1 AOUT2

AIN2 LOUT2

3rd-Order

Noise Shaper

Over Sampling

Digital Filter

Serial-In

Interface

LMUT

RMUT

XTAO

XTAI

Timing

Logic

XRST

TEST

TES1

D/A

Interface

DOUT

EFM

demodurator

Error

Corrector

16K

RAM

Digital

OUT

Sub Code Processor

Clock

Generator

Asymmetry

Corrector

Digital

PLL

Digital

CLV

CPU

Interface

Servo

Auto

Sequencer

Signal Processor Block

DAC Block

SYSM

BCK

PCMD

LRCK

C2PO

WFCK

EMPH

GFS

XUGF

XTSL

RFAC

ASYI

ASYO

BIAS

XPCK

FILO

FILI

PCO

CLTV

MDP LOCK SENS

DATA

XLAT CLOK SPOA SPOB XLON

SCOR SQSO SQCK

Servo Block

SERVO

Interface

SCLK COUT SSTP ATSK

MIRR DFCT

FOK

MIRR DFCT FOK

SERVO DSP

FOCUS SERVO

TRACKING

SERVO

SLED SERVO

PWM GENERATOR

FOCUS PWM GENERATOR

TRACKING PWM

GENERATOR

SLED PWM

GENERATOR

FFDR FRDR TFDR TRDR SFDR SRDR

RFDC

CE

TE

SE

FE

VC

IGEN

OPAmp

Analog SW

A/D

Converter

ADIO

– 3 –

CXD2587Q

Pin Configuration

21

22

23

24

25

26

27

28

29

30

40 39

38 37 36 35

34

31

32

33

4142

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

70

69

68

67

63 64 65 66

61

62

71

72 73

74 75 76 77 78 79 80

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

1

LRCK

PCMD

BCK

EMPH

XV

DD

XTAI

XTAO

XV

SS

AVDD1

AOUT1

AIN1

LOUT1

AV

SS1

AV

SS2

LOUT2

AIN2

AOUT2

AV

DD2

RMUT

LMUT

SE FE

VC XTSL TES1 TEST V

SS

FRDR

COUT

FFDR TRDR TFDR SRDR SFDR SSTP MDP LOCK

MIRR

DOUT

V

DD

V

SS

FILI

CLTV

AV

SS

3

TE

ASYO

AV

DD

0

IGEN

AV

SS

0

ADIO

RFDC

AV

DD

3

PCO

BIAS

ASYI

FILO

RFAC

CE

SQCK

XLAT

SENS

DATA

XRST

SYSM

CLOK

V

DD

SQSO

SCLK

SCOR

ATSK

SPOA

SPOB

XLON

WFCK

XUGF

XPCK

GFS

C2PO

FOK DFCT

– 4 –

CXD2587Q

Pin Description

Pin No.

Symbol I/O

Output values

Description

Sub Q 80-bit, PCM peak and level data outputs. CD TEXT data output. SQSO readout clock input. System reset. Reset when low. Mute input. Muted when high. Serial data input from CPU. Latch input from CPU. Serial data is latched at the falling edge. Serial data transfer clock input from CPU. SENS output to CPU. SENS serial data readout clock input. Digital power supply. Anti-shock input/output. Microcomputer extension interface (input A) Microcomputer extension interface (input B) Microcomputer extension interface (output) WFCK output. XUGF output. MINT1 or RFCK is output by switching with the command. XPCK output. MNT0 is output by switching with the command. GFS output. MNT3 or XROF is output by switching with the command. C2PO output. GTOP is output by switching with the command. Outputs a high signal when either subcode sync S0 or S1 is detected. Track count signal input/output. Mirror signal input/output. Defect signal input/output. Focus OK signal input/output. GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS

is low eight consecutive samples, this pin outputs low. Or input when LKIN = 1. Spindle motor servo control output. Disc innermost track detection signal input. Sled drive output. Sled drive output. Tracking drive output. Tracking drive output. Focus drive output. Focus drive output. Digital GND. Test pin. Normally, GND.

1, 0

—

1, 0

1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0

1, 0

1, Z, 0

1, 0 1, 0 1, 0 1, 0 1, 0 1, 0

—

O

I I I I I I

O

I

—

I/O

I

I O O O O O O O

I/O I/O I/O I/O

I/O

O

I O O O O O O

—

I

SQSO SQCK XRST SYSM DATA XLAT CLOK SENS SCLK VDD ATSK SPOA SPOB XLON WFCK XUGF XPCK GFS C2PO SCOR COUT MIRR DFCT FOK

LOCK MDP

SSTP SFDR SRDR TFDR TRDR FFDR FRDR VSS TEST

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

25 26

27 28 29 30 31 32 33 34 35

– 5 –

CXD2587Q

Pin No.

Symbol I/O

Output values

Description

Test pin. Normally, GND. Crystal selection input. Low when the crystal is 16.9344MHz; high when the

crystal is 33.8688MHz. Center voltage input. Focus error signal input. Sled error signal input. Tracking error signal input. Center servo analog input. RF signal input. Test pin. No connected. Analog GND. Operational amplifier constant current input. Analog power supply. EFM full-swing output. (low = Vss, high = VDD) Asymmetry comparator voltage input. Asymmetry circuit constant current input. EFM signal input. Analog GND. Multiplier VCO1 control voltage input. Master PLL filter output. (slave = digital PLL) Master PLL filter input. Master PLL charge pump output. Analog power supply. Digital GND. Digital power supply. Digital Out output. D/A interface. LR clock output f = Fs. D/A interface. Serial data output. (two's complement, MSB first) D/A interface. Bit clock output. Outputs a high signal when the playback disc has emphasis, and a low

signal when there is no emphasis. Master clock power supply. Crystal oscillation circuit input. Master clock is externally input from this pin. Crystal oscillation circuit output. Master clock GND. Analog power supply. L ch analog output. L ch operational amplifier input.

Analog

—

1, 0

—

Analog

1, Z, 0

— —

— 1, 0 1, 0 1, 0 1, 0

1, 0

—

I I I

I I I I I

O

—

I

—

O

I I I

—

I

O

I

O — — —

O

O —

I

O — —

O

I

TES1 XTSL VC

FE SE TE CE RFDC ADIO AVSS0 IGEN AVDD0 ASYO ASYI BIAS RFAC AVSS3 CLTV FILO FILI PCO AVDD3 VSS VDD DOUT LRCK PCMD BCK

EMPH XVDD

XTAI XTAO XVSS AVDD1 AOUT1 AIN1

36 37 38

39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

64 65

66 67 68 69 70 71

– 6 –

CXD2587Q

Pin No.

Symbol I/O

Output values

Description

L ch LINE output. Analog GND. Analog GND. R ch LINE output. R ch operational amplifier output. R ch analog output. Analog power supply. R ch zero detection flag. L ch zero detection flag.

— —

— 1, 0 1, 0

O — —

O

I

O —

O

LOUT1 AVSS1 AVSS2 LOUT2 AIN2 AOUT2 AVDD2 RMUT LMUT

72 73 74 75 76 77 78 79 80

Notes) • PCMD is a MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)

• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before

sync protection.

• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal transition point coincide.

• The GFS signal goes high when the frame sync and the insertion timing match.

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.

• C2PO represents the data error status.

• XROF is generated when the 16K RAM exceeds the ±4F jitter margin.

Monitor Pin Output Combinations

Command bit

Output data

MTSL1

0 0 1

0 1 0

XUGF MNT1 RFCK

XPCK MNT0 XPCK

GFS MNT3 XROF

C2PO C2PO

GTOP

MTSL0

– 7 –

CXD2587Q

Electrical Characteristics

1. DC Characteristics (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

Item

Input voltage (1)

Input voltage (2)

Input voltage (3)

Output voltage (1)

Output voltage (2)

Output voltage (3)

Input leak current (1)

Input leak current (2) Input leak current (3)

Input leak current (4)

∗1, ∗9

∗2, ∗10

∗3, ∗7, ∗8

∗4

∗5

∗6

∗1, ∗2

∗9, ∗10 ∗7

∗8

Schmitt input

Analog input IOH = –2mA

IOL = 4mA IOH = –6mA IOL = 4mA IOH = –0.28mA IOL = 0.36mA VIN = VSS

or VDD VIN = VSS

or VDD VI = 1.5 to 3.5V VI = 0 to 5.0V

High level input voltage Low level input voltage High level input voltage Low level input voltage

Input voltage High level output voltage

Low level output voltage High level output voltage Low level output voltage High level output voltage Low level output voltage

VIH (1) VIL (1) VIH (2) VIL (2)

VIN(3) VOH (1)

VOL (1) VOH (2) VOL (2) VOH (3) VOL (3)

ILI (1)

ILI (2) ILI (3)

ILI (4)

0.7VDD

0.8VDD

Vss

VDD – 0.8

Vss

VDD – 0.8

Vss

VDD – 0.5

Vss –10

–40 –20

–40

0.3VDD

0.2VDD VDD VDD

0.4

VDD

0.4

VDD

0.4 10

40 20

600

V V V V

V V

V V V V V

µA

µA µA

µA

Conditions Min. Typ. Max. Unit

Applicable pins

∗1

SYSM, DATA, XLAT, SSTP, XTSL, TEST, TES1

∗2

SQCK, XRST, CLOK

∗3

ASYI, RFAC, CLTV, FILI

∗4

SQSO, SENS, ATSK, XLON, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, COUT, MIRR, DFCT, FOK, LOCK, SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, ASYO, DOUT, LRCK, PCMD, BCK, EMPH, RMUT, LMUT

∗5

MDP, PCO

∗6

FILO

∗7

VC, FE, SE, TE, CE

∗8

RFDC

∗9

ATSK, COUT, MIRR, DFCT, FOK, LOCK

∗10

SCLK, SPOA, SPOB

– 8 –

CXD2587Q

2. AC Characteristics

(1) XTAI pin

(a) When using self-excited oscillation

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

(b) When inputting pulses to XTAI pin

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

(c) When inputting sine waves to XTAI pin via a capacitor

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)

Oscillation frequency

fMAX 7

34

MHz

Item Symbol Min. Typ. Max.

Unit

High level pulse width

tWHX

13 500

ns

Low level pulse width

tWLX

13 500

ns

Pulse cycle

tCX

26 1000

ns

Input high level VIHX VDD – 1.0

V

Input low level VILX 0.8

V

Rise time, fall time

tR, tF

10

ns

Item Symbol Min. Typ. Max. Unit

Input amplitude VI 2.0 VDD + 0.3 Vp-p

Item Symbol Min. Typ. Max. unit

tR tF

tWHX

tWLX

tCK

VILX

VIHX × 0.1

V

IHX × 0.9

V

IHX

XTAI

V

DD/2

– 9 –

CXD2587Q

(2) CLOK, DATA, XLAT and SQCK pin

(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width SQCK frequency SQCK pulse width

fCK

tWCK tSU tH tD tWL

fT

tWT

750 300 300 300 750

750

Note)

0.65

Note)

MHz

ns ns ns ns ns

MHz

ns

Item Symbol Min. Typ. Max. Unit

tWCK tWCK

1/fCK

tH

tSU

tWL

tD

1/fT

tWT tWT

tH

tSU

CLOK

DATA

XLAT

SQCK

SQSO

Note) In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCK maximum

operating frequency is 300kHz and its minimum pulse width is 1.5µs.

– 10 –

CXD2587Q

(4) COUT, MIRR and DFCT pins

Operating frequency

(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)

COUT maximum operating frequency MIRR maximum operating frequency DFCT maximum operating frequency

fCOUT fMIRR fDFCTH

40 40

5

kHz kHz kHz

∗1 ∗2 ∗3

Item Symbol Min. Typ. Max. Unit

Conditions

∗

1

When using a high-speed traverse TZC.

∗

2

When the RF signal continuously satisfies the following conditions during the above traverse.

• A = 0.12VDD to 0.26VDD

• ≤ 25%

∗

3

During complete RF signal omission. When settings related to DFCT signal generation are Typ.

(3) SCLK pin

SCLK frequency SCLK pulse width Delay time

fSCLK

tSPW tDLS

31.3 15

16 MHz

ns µs

Item Symbol Min. Typ. Max. Unit

tSPWtDLS

1/fSCLK

MSB LSB

•••

XLAT

SCLK

Serial Read Out Data

(SENS)

A

B

A + B

– 11 –

CXD2587Q

1-bit DAC and LPF Block Analog Characteristics

Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C)

Fs = 44.1kHz in all cases. The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.

LPF external circuit diagram

Block diagram of analog characteristics measurement

Item

Total harmonic distortion

Signal-to-noise ratio

Symbol

THD

S/N

Conditions

1kHz, 0dB data

Crystal

1kHz, 0dB data (Using A-weighting filter)

384Fs 768Fs 384Fs 768Fs

96 96

0.0050

0.0045 100 100

0.0070

0.0065

Min.

Typ.

Max.

Unit

%

dB

Audio Analyzer

SHIBASOKU (AM51A)

100k

22µ

680p

12k

150p

AOUT1 (2)

AIN1 (2)

LOUT1 (2)

Audio Analyzer

CXD2587Q

Rch A

Lch B

DATA RF

TEST DISC

768Fs/384Fs

(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Output voltage Load resistance

VOUT RL

∗1 ∗1

Vrms

kΩ

Item Symbol

8

Min.

Max.

1.12

Typ.

Applicable pins

Unit

∗

Measurement is conducted for the LPF external circuit diagram with the sine wave output of 1kHz and 0dB.

Applicable pins

∗1

LOUT1, LOUT2

– 12 –

CXD2587Q

Contents

§1. CPU Interface

§1-1. CPU Interface Timing ........................................................................................................................ 13

§1-2. CPU Interface Command Table ........................................................................................................ 13

§1-3. CPU Command Presets .................................................................................................................... 23

§1-4. Description of SENS Signals and Commands ................................................................................... 28

§2. Subcode Interface

§2-1. 80-bit Sub Q Readout ........................................................................................................................ 42

§3. Description of Other Functions

§3-1. Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 45

§3-2. Frame Sync Protection ...................................................................................................................... 46

§3-3. Error Correction ................................................................................................................................. 46

§3-4. DA Interface ....................................................................................................................................... 47

§3-5. Digital Out .......................................................................................................................................... 49

§3-6. Servo Auto Sequence ....................................................................................................................... 49

§3-7. Digital CLV ......................................................................................................................................... 56

§3-8. CD-DSP Block Playback Speed ........................................................................................................ 57

§3-9. DAC Block Playback Speed .............................................................................................................. 57

§3-10. Description of DAC Block Functions .................................................................................................. 58

§3-11. LPF Block .......................................................................................................................................... 61

§3-12. Asymmetry Compensation ................................................................................................................ 62

§3-13. CD TEXT Data Demodulation ........................................................................................................... 63

§4. Description of Servo Signal Processing System Functions and Commands

§4-1. General Description of Servo Signal Processing System .................................................................. 65

§4-2. Digital Servo Block Master Clock (MCK) ........................................................................................... 66

§4-3. AVRG Measurement and Compensation .......................................................................................... 66

§4-4. E:F Balance Adjustment Function ..................................................................................................... 68

§4-5. FCS Bias Adjustment Function .......................................................................................................... 68

§4-6. AGCNTL Function ............................................................................................................................. 70

§4-7. FCS Servo and FCS Search ............................................................................................................. 72

§4-8. TRK and SLD Servo Control ............................................................................................................. 73

§4-9. MIRR and DFCT Signal Generation .................................................................................................. 74

§4-10. DFCT Countermeasure Circuit .......................................................................................................... 75

§4-11. Anti-Shock Circuit .............................................................................................................................. 75

§4-12. Brake Circuit ...................................................................................................................................... 76

§4-13. COUT Signal ..................................................................................................................................... 77

§4-14. Serial Readout Circuit ........................................................................................................................ 77

§4-15. Writing to the Coefficient RAM .......................................................................................................... 78

§4-16. PWM Output ...................................................................................................................................... 78

§4-17. Servo Status Changes Produced by the LOCK Signal ..................................................................... 80

§4-18. Description of Commands and Data Sets ......................................................................................... 80

§4-19. List of Servo Filter Coefficients .......................................................................................................... 95

§4-20. Filter Composition .............................................................................................................................. 97

§4-21. TRACKING and FOCUS Frequency Response .............................................................................. 104

§5. Application Circuit .................................................................................................................................. 105

Explanation of abbreviations AVRG: Average

AGCNTL: Auto gain control FCS: Focus TRK: Tracking SLD: Sled DFCT: Defect

– 13 –

CXD2587Q

§1. CPU Interface

§1-1. CPU Interface Timing

• CPU interface

This interface uses DATA, CLOK and XLAT to set the modes. The interface timing chart is shown below.

• The internal registers are initialized by a reset when XRST = 0. Note) Be sure to set SQCK to high when XLAT is low.

§1-2. CPU Interface Command Table

Total bit length for each register

Register

0 to 2

3

4 to 6

7 8 9 A B C D E

8 bits

8 to 24 bits

8 bits 20 bits 28 bits 24 bits 28 bits 16 bits

8 bits 16 bits 20 bits

Total bit length

750ns or more

D18 D19 D20 D21 D22 D23

750ns or more

Valid

CLOK

DATA

XLAT

Registers

D0 D1

– 14 –

CXD2587Q

FOCUS SERVO ON

(FOCUS GAIN

NORMAL)

FOCUS SERVO ON

(FOCUS GAIN

DOWN)

FOCUS SERVO OFF,

0V OUT

FOCUS SERVO OFF,

FOCUS SEARCH

VOLTAGE OUT

FOCUS SEARCH

VOLTAGE DOWN

FOCUS SEACH

VOLTAGE UP

ANTI SHOCK ON

ANTI SHOCK OFF

BRAKE ON

BRAKE OFF

TRACKING GAIN

NORMAL

TRACKING GAIN UP

FILTER SELECT 1

TRACKING GAIN UP

FILTER SELECT 2

1

0

1

0

—

0

1

—

0

—

1

0

—

0

1

—

0

1

—

0

1

—

1

0

—

0

1

0 0 0 0

0 0 0 1

FOCUS

CONTROL

TRACKING

CONTROL

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Command Table ($0X to 1X)

—: Don’t care

– 15 –

CXD2587Q

TRACKING SERVO OFF

TRACKING SERVO ON

FORWARD TRACK JUMP

REVERSE TRACK JUMP

SLED SERVO OFF

SLED SERVO ON

FORWARD SLED MOVE

REVERSE SLED MOVE

SLED KICK LEVEL

(±1 × basic value) (Default)

SLED KICK LEVEL

(±2

×

basic value)

SLED KICK LEVEL

(±3

×

basic value)

SLED KICK LEVEL

(±4

×

basic value)

0

1

—

0

1

0

1

0

1

—

0

1

0

1

—

0

1

—

0

1

0

1

—

2

3

0 0 1 0

0 0 1 1

TRACKING

MODE

SELECT

Register

Command

Address

D23 to D20

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

—: Don’t care

Command Table ($2X to 3X)

– 16 –

CXD2587Q

Command Table ($340X)

KRAM DATA (K00)

SLED INPUT GAIN

KRAM DATA (K01)

SLED LOW BOOST FILTER A-H

KRAM DATA (K02)

SLED LOW BOOST FILTER A-L

KRAM DATA (K03)

SLED LOW BOOST FILTER B-H

KRAM DATA (K04)

SLED LOW BOOST FILTER B-L

KRAM DATA (K05)

SLED OUTPUT GAIN

KRAM DATA (K06)

FOCUS INPUT GAIN

KRAM DATA (K07)

SLED AUTO GAIN

KRAM DATA (K08)

FOCUS HIGH CUT FILTER A

KRAM DATA (K09)

FOCUS HIGH CUT FILTER B

KRAM DATA (K0A)

FOCUS LOW BOOST FILTER A-H

KRAM DATA (K0B)

FOCUS LOW BOOST FILTER A-L

KRAM DATA (K0C)

FOCUS LOW BOOST FILTER B-H

KRAM DATA (K0D)

FOCUS LOW BOOST FILTER B-L

KRAM DATA (K0E)

FOCUS PHASE COMPENSATE FILTER A

KRAM DATA (K0F)

FOCUS DEFECT HOLD GAIN

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 0 0

SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 17 –

CXD2587Q

Command Table ($341X)

KRAM DATA (K10)

FOCUS PHASE COMPENSATE FILTER B

KRAM DATA (K11)

FOCUS OUTPUT GAIN

KRAM DATA (K12)

ANTI SHOCK INPUT GAIN

KRAM DATA (K13)

FOCUS AUTO GAIN

KRAM DATA (K14)

HPTZC / AUTO GAIN HIGH PASS FILTER A

KRAM DATA (K15)

HPTZC / AUTO GAIN HIGH PASS FILTER B

KRAM DATA (K16)

ANTI SHOCK HIGH PASS FILTER A

KRAM DATA (K17)

HPTZC / AUTO GAIN LOW PASS FILTER B

KRAM DATA (K18)

FIX

KRAM DATA (K19)

TRACKING INPUT GAIN

KRAM DATA (K1A)

TRACKING HIGH CUT FILTER A

KRAM DATA (K1B)

TRACKING HIGH CUT FILTER B

KRAM DATA (K1C)

TRACKING LOW BOOST FILTER A-H

KRAM DATA (K1D)

TRACKING LOW BOOST FILTER A-L

KRAM DATA (K1E)

TRACKING LOW BOOST FILTER B-H

KRAM DATA (K1F)

TRACKING LOW BOOST FILTER B-L

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 0 1

SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 18 –

CXD2587Q

Command Table ($342X)

KRAM DATA (K20)

TRACKING PHASE COMPENSATE FILTER A

KRAM DATA (K21)

TRACKING PHASE COMPENSATE FILTER B

KRAM DATA (K22)

TRACKING OUTPUT GAIN

KRAM DATA (K23)

TRACKING AUTO GAIN

KRAM DATA (K24)

FOCUS GAIN DOWN HIGH CUT FILTER A

KRAM DATA (K25)

FOCUS GAIN DOWN HIGH CUT FILTER B

KRAM DATA (K26)

FOCUS GAIN DOWN LOW BOOST FILTER A-H

KRAM DATA (K27)

FOCUS GAIN DOWN LOW BOOST FILTER A-L

KRAM DATA (K28)

FOCUS GAIN DOWN LOW BOOST FILTER B-H

KRAM DATA (K29)

FOCUS GAIN DOWN LOW BOOST FILTER B-L

KRAM DATA (K2A)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER A

KRAM DATA (K2B)

FOCUS GAIN DOWN DEFECT HOLD GAIN

KRAM DATA (K2C)

FOCUS GAIN DOWN PHASE COMPENSATE FILTER B

KRAM DATA (K2D)

FOCUS GAIN DOWN OUTPUT GAIN

KRAM DATA (K2E)

NOT USED

KRAM DATA (K2F)

NOT USED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 1 0

SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 19 –

CXD2587Q

Command Table ($343X)

KRAM DATA (K30)

SLED INPUT GAIN (when SFSK = 1 TG up2)

KRAM DATA (K31)

ANTI SHOCK LOW PASS FILTER B

KRAM DATA (K32)

NOT USED

KRAM DATA (K33)

ANTI SHOCK HIGH PASS FILTER B-H

KRAM DATA (K34)

ANTI SHOCK HIGH PASS FILTER B-L

KRAM DATA (K35)

ANTI SHOCK FILTER COMPARATE GAIN

KRAM DATA (K36)

TRACKING GAIN UP2 HIGH CUT FILTER A

KRAM DATA (K37)

TRACKING GAIN UP2 HIGH CUT FILTER B

KRAM DATA (K38)

TRACKING GAIN UP2 LOW BOOST FILTER A-H

KRAM DATA (K39)

TRACKING GAIN UP2 LOW BOOST FILTER A-L

KRAM DATA (K3A)

TRACKING GAIN UP2 LOW BOOST FILTER B-H

KRAM DATA (K3B)

TRACKING GAIN UP2 LOW BOOST FILTER B-L

KRAM DATA (K3C)

TRACKING GAIN UP PHASE COMPENSATE FILTER A

KRAM DATA (K3D)

TRACKING GAIN UP PHASE COMPENSATE FILTER B

KRAM DATA (K3E)

TRACKING GAIN UP OUTPUT GAIN

KRAM DATA (K3F)

NOT USED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 0 1 1

SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 20 –

CXD2587Q

Command Table ($344X)

KRAM DATA (K40)

TRACKING HOLD FILTER INPUT GAIN

KRAM DATA (K41)

TRACKING HOLD FILTER A-H

KRAM DATA (K42)

TRACKING HOLD FILTER A-L

KRAM DATA (K43)

TRACKING HOLD FILTER B-H

KRAM DATA (K44)

TRACKING HOLD FILTER B-L

KRAM DATA (K45)

TRACKING HOLD FILTER OUTPUT GAIN

KRAM DATA (K46)

TRACKING HOLD INPUT GAIN (when THSK = 1 TG up2)

KRAM DATA (K47)

NOT USED

KRAM DATA (K48)

FOCUS HOLD FILTER INPUT GAIN

KRAM DATA (K49)

FOCUS HOLD FILTER A-H

KRAM DATA (K4A)

FOCUS HOLD FILTER A-L

KRAM DATA (K4B)

FOCUS HOLD FILTER B-H

KRAM DATA (K4C)

FOCUS HOLD FILTER B-L

KRAM DATA (K4D)

FOCUS HOLD FILTER OUTPUT GAIN

KRAM DATA (K4E)

NOT USED

KRAM DATA (K4F)

NOT USED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

KD7

KD6

KD5

KD4

KD3

KD2

KD1

KD0

3 0 0 1 1 0 1 0 0 0 1 0 0

SELECT

Register

Command

Address 1

D23 to D20

Address 2

D19 to D16

Address 3

D15 to D12

Address 4

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D1 D0

– 21 –

CXD2587Q

Command Table ($34FX to 3FX)

0 0 1 1

1

0

1

0

1

FOCUS BIAS LIMIT

FOCUS BIAS DATA

TRVSC DATA

FOCUS SEARCH SPEED/

VOLTAGE/AUTO GAIN

DTZC/TRACK JUMP

VOLTAGE/AUTO GAIN

FZSL/SLED MOVE/

Voltage/AUTO GAIN

LEVEL/AUTO GAIN/

DFSW/ (Initialize)

SERIAL DATA READ

MODE/SELECT

FOCUS BIAS

Operation for MIRR/

DFCT/FOK

TZC/COUT

BOTTOM/MIRR

SLED FILTER

Filter

Others

3

0 0 1 1

0

1

0

1

0

1

0

FBL9

FB9

TV9

FBL8

FB8

TV8

FBL7

FB7

TV7

FBL6

FB6

TV6

FBL5

FB5

TV5

FBL4

FB4

TV4

FBL3

FB3

TV3

FBL2

FB2

TV2

FBL1

FB1

TV1

—

TV0

0

1

0

1

0

1

0

1

FT1

TDZC

FZSH

VCLM

DAC

0

SFO2

FT0

DTZC

FZSL

VCLC

SD6

FBON

SFO1

FS5

TJ5

SM5

FLM

SD5

FBSS

SDF2

FS4

TJ4

SM4

FLC0

SD4

FBUP

SDF1

FS3

TJ3

SM3

RFLM

SD3

FBV1

MAX2

FS2

TJ2

SM2

RFLC

SD2

FBV0

MAX1

FS1

TJ1

SM1

AGF

SD1

0

SFOX

FS0

TJ0

SM0

AGT

SD0

TJD0

BTF

FTZ

SFJP

AGS

DFSW

0

FPS1

D2V2

FG6

TG6

AGJ

LKSW

0

FPS0

D2V1

FG5

TG5

AGGF

TBLM

0

TPS1

D1V2

FG4

TG4

AGGT

TCLM

0

TPS0

D1V1

FG3

TG3

AGV1

FLC1

0

RINT

FG2

TG2

AGV2

TLC2

0

SJHD

0

FG1

TG1

AGHS

TLC1

0

INBK

0

FG0

TG0

AGHT

TLC0

0

MTI0

0

1

0

1

F1NM

0

F1DM

AGG4

F3NM

XT4D

F3DM

XT2D

T1NM

0

T1UM

DRR2

T3NM

DRR1

T3UM

DRR0

DFIS

0

TLCD

ASFG

0

FTQ

LKIN

LPAS

COIN

SRO1

MDFI

0

MIRI

AGHF

XT1D

ASOT

1

0

1

COSS

SFID

COTS

SFSK

CETZ

THID

CETF

THSK

COT2

0

COT1

TLD2

MOT2

TLD1

0

TLD0

BTS1

0

BTS0

0

MRC1

0

MRC0

0

SELECT

Register

Command

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15 D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

Address

D23 to D20 D19 D18 D17 D16

Data 1

D15 D14 D13 D12

Data 2

D11 D10 D9 D8

Data 3

D7 D6 D5 D4

Data 4

D3 D2 D1 D0

—: Don’t care

– 22 –

CXD2587Q

Command Table

4

5

6

7

8

9

A

B

C

D

E

Auto sequence

Blind (A, E),

Overflow (C)

Brake (B)

Kick (D)

Auto sequence

(N) track jump

count

Mode

specification

Function

specification

Audio CTRL

Serial bus

CTRL

Spindle servo

coefficient

setting

CLV CTRL

CLV MODE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

2048

VCO

SEL1

0

TRMI

—

1

0

—

1024

0

TRMO

—

1

0

—

512

SOCT

0

OPSL20OPSL21MTSL1

—

1

0

—

256

0

EMPH

MTSL0

—

0

—

128

KSL3

OPSL10OPSL1

1

SMUT

0

—

0

—

64

KSL2

MCSL

AD10

0

—

0

—

32

1

0

AD9

0

—

0

—

16

0

AD8

0

—

0

—

8

0

ZDPL

AD7

—

0

—

4

0

ZMUT

AD6

—

0

—

2

0

—

0

AD5

—

0

—

1

0

—

0

AD4

—

0

—

0

—

0

AD3

—

0

—

DCOF

AD2

—

0

—

0

AD1

—

0

—

0

AD0

—

TXON

—

FMUT

—

TXOUT

—

LRWO

—

OUTL1

—

BSBST

—

OUTL0

—

BBSL

—

AS3

0.18ms

0.36ms

11.6ms

32768

CDROM

0

SL1

Gain

MDP1

0

CM3

AS2

0.09ms

0.18ms

5.8ms

16384

DOUT

Mute

DSPB

ON/OFF

DSPB

ON/OFF

0

SL0

Gain

MDP0

TB

CM2

AS1

0.05ms

0.09ms

2.9ms

8192

DOUT

ON/OFF

0

Mute

CPUSR

Gain

MDS1

TP

CM1

AS0

0.02ms

0.05ms

1.45ms

4096

WSEL

0

ATT

0

Gain

MDS0

Gain

CLVS

CM0

Command

Address

D3 D2 D1 D0

Data 1

D3 D2 D1 D0

Data 2

D3 D2 D1 D0

Data 3

D3 D2 D1 D0

Data 4

D3 D2 D1 D0

Data 5

D3 D2 D1 D0

Data 6

D3 D2 D1 D0

Register

– 23 –

CXD2587Q

FOCUS SERVO OFF,

0V OUT

TRACKING GAIN UP

FILTER SELECT 1

TRACKING SERVO OFF

SLED SERVO OFF

SLED KICK LEVEL

(±1 × basic value) (Default)

KRAM DATA

($3400XX to $344fXX)

0

1

0

—

0

1

2

0 0 0 0

0 0 0 1

0 0 1 0

FOCUS

CONTROL

TRACKING

CONTROL

TRACKING

MODE

Register

Command

Address

D23 to D20

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D1 D0

Register

Command

3 SELECT

Address

D23 to D20

0 0 1 1

0 0 1 1 0 1 0 0 0

See "Coefficient ROM Preset Values Table".

0 0 0 0 — — — — — — — — — — — — — — — —

Data 1

D19 D18 D17 D16

Data 2

D15 D14 D13 D12

Data 3

D11 D10 D9 D8

Data 4

D7 D6 D5 D4

Data 5

D3 D2 D0 D0

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15 D14 D13 D12

Address 3

D11 D10 D9 D8

Data 1

D7 D6 D5 D4

Data 2

D3 D2 D0 D0

§1-3. CPU Command Presets

Command Preset Table ($0X to 34X)

—: Don’t care

– 24 –

CXD2587Q

Command Preset Table ($34FX to 3FX)

0 0 1 1

1

0

1

0

1

FOCUS BIAS LIMIT

FOCUS BIAS DATA

TRVSC DATA

FOCUS SEARCH SPEED/

VOLTAGE AUTO GAIN

DTZC/TRACK JUMP

VOLTAGE AUTO GAIN

FZSL/SLED MOVE/

Voltage/AUTO GAIN

LEVEL/AUTO GAIN/

DFSW/ (Initialize)

SERIAL DATA READ

MODE/SELECT

FOCUS BIAS

Operation for MIRR/

DFCT/FOK

TZC/COUT

BOTTOM/MIRR

SLED FILTER

3

0 0 1 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Filter

Others

1

0

1

0

SELECT

Register

Command

Address 1

D23 to D20 D19 D18 D17 D16

Address 2

D15 D14 D13 D12

Data 1

D11 D10 D9 D8

Data 2

D7 D6 D5 D4

Data 3

D3 D2 D1 D0

Address

D23 to D20 D19 D18 D17 D16

Data 1

D15 D14 D13 D12

Data 2

D11 D10 D9 D8

Data 3

D7 D6 D5 D4

Data 4

D3 D2 D1 D0

—: Don’t care

– 25 –

CXD2587Q

Reset Initialization

Register

4

5

6

7

8

9

A

B

C

D

E

Auto sequence

Blind (A, E),

Overflow (C, G)

Brake (B),

Sled KICK,

BRAKE (D),

KICK (F)

Auto sequence (N)

track jump

count setting

MODE

specification

Function

specification

Audio CTRL

Serial bus

CTRL

Spindle servo

coefficient setting

CLV CTRL

CLV mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

—

0

—

1

0

—

0

1

—

1

0

—

0

—

1

0

—

1

0

—

0

—

0

—

0

—

0

1

0

—

0

—

0

1

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

0

—

Command

Address

D3 D2 D1 D0

Data 1

D3 D2 D1 D0

Data 2

D3 D2 D1 D0

Data 3

D3 D2 D1 D0

Data 4

D3 D2 D1 D0

Data 5

D3 D2 D1 D0

Data 6

D3 D2 D1 D0

– 26 –

CXD2587Q

ADDRESS

K00 K01 K02 K03 K04 K05 K06 K07 K08

K09 K0A K0B K0C K0D K0E K0F

E0 81 23 7F 6A 10 14 30 7F 46 81

1C

7F 58 82 7F

SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19 K1A K1B K1C K1D K1E K1F

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29 K2A K2B K2C K2D K2E K2F

4E 32 20 30 80 77 80 77 00 F1 7F 3B 81 44 7F 5E

FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix

∗

TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L

82 44 18 30 7F 46 81 3A 7F 66 82 44 4E 1B 00 00

TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN NOT USED NOT USED

DATA CONTENTS

∗

Fix indicates that normal preset values should be used.

– 27 –

CXD2587Q

ADDRESS

K30 K31 K32 K33 K34 K35 K36 K37 K38 K39 K3A K3B

K3C K3D K3E K3F

80 66 00 7F 6E 20 7F 3B 80 44 7F 77 86

0D

57 00

SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B NOT USED ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B TRACKING GAIN UP2 LOW BOOST FILTER A-H TRACKING GAIN UP2 LOW BOOST FILTER A-L TRACKING GAIN UP2 LOW BOOST FILTER B-H TRACKING GAIN UP2 LOW BOOST FILTER B-L TRACKING GAIN UP PHASE COMPENSATE FILTER A TRACKING GAIN UP PHASE COMPENSATE FILTER B TRACKING GAIN UP OUTPUT GAIN NOT USED

K40 K41 K42 K43 K44 K45 K46 K47 K48 K49

K4A K4B K4C K4D K4E K4F

04 7F 7F 79 17

6D

00 00 02 7F 7F 79 17 54 00 00

TRACKING HOLD FILTER INPUT GAIN TRACKING HOLD FILTER A-H TRACKING HOLD FILTER A-L TRACKING HOLD FILTER B-H TRACKING HOLD FILTER B-L TRACKING HOLD FILTER OUTPUT GAIN TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is accessed with THSK = 1.) NOT USED FOCUS HOLD FILTER INPUT GAIN FOCUS HOLD FILTER A-H FOCUS HOLD FILTER A-L FOCUS HOLD FILTER B-H FOCUS HOLD FILTER B-L FOCUS HOLD FILTER OUTPUT GAIN NOT USED NOT USED

DATA CONTENTS

– 28 –

CXD2587Q

Description of SENS Signals

Low while the auto sequencer is in operation, high when the operation terminates. Outputs the same signal as the FOK pin.

High for "focus OK". High when the regenerated frame sync is obtained with the correct timing. Counts the number of tracks with frequeny division ratio set by $B. High when $C is

latched, and toggles each time COUT is counted just for the frequency diviison ratio set by $B.

Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing through the sync detection filter.

XBUSY FOK GFS

COUT

OV64

SENS output

§1-4. Description of SENS Signals and Commands

SENS output

Note) The SENS output can be read from the SQSO pin when SOCT = 0, SL1 = 1 and SL0 = 0.

$38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement. SSTP is output in all other cases.

Microcomputer serial register (latching not required)

$0X $1X $2X $30 to 37 $38 $38 $3904 $3908 $390C $391C $391D $391F $3A $3B to 3F $4X $5X $6X, 7X, 8X, 9X $AX $BX $CX $DX $EX $FX

FZC

AS (Anti Shock)

TZC

SSTP

AGOK

XAVEBSY TE Avrg Reg. FE Avrg Reg. VC Avrg Reg.

TRVSC Reg.

FB Reg.

RFDC Avrg Reg.

FBIAS count STOP

SSTP

XBUSY

FOK

0

GFS

0

COUT frequency division

0

OV64

0

— — — — —

— 9 bit 9 bit 9 bit 9 bit 9 bit 8 bit

—

SENS output Output data length

– 29 –

CXD2587Q

The meaning of the data for each address is explained below. $4X commands

RXF = 0 FORWARD RXF = 1 REVERSE

• When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.

• When the Track jump/move commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is

interrupted.

$5X commands

Auto sequence timer setting Setting timers: A, E, C, B

Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset)

A = E = C = 0.11ms B = 0.23ms

$6X commands

Auto sequence timer setting Setting timer: D

Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset)

D = 10.15ms

$7X commands

Auto sequence track jump/move count setting (N)

This command is used to set N when a 2N-track jump and an N-track move are executed for auto sequence.

• The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count depends on the mechanical limitations of the optical system.

• The number of tracks jumped is counted according to the COUT signals.

CANCEL FOCUS-ON 1 TRACK JUMP 10 TRACK JUMP 2N TRACK JUMP N TRACK MOVE

0 0 1 1 1 1

0 1 0 0 1 1

0 1 0 1 0 1

0

1 RXF RXF RXF RXF

Command

AS3

AS2

AS1

AS0

Blind (A, E), Over flow (C) Brake (B)

0.18ms

0.36ms

0.09ms

0.18ms

0.05ms

0.09ms

0.02ms

0.05ms

Command

D3

D2

D1

D0

KICK (D)

11.6ms

5.8ms

2.9ms

1.45ms

Command

Data 1 Data 2

Data 3 Data 4

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 2152142132122112102928272625242322212

0

Auto sequence track jump count setting

D3

D2

D1

D0

– 30 –

CXD2587Q

Command

D3

CDROM

DOUT

Mute

DOUT

ON/OFF

WSEL

VCO

SEL1

0

SOCT 0 KSL3 KSL2 1 0

D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Data 1

Data 2

MODE specification

Data 3

Command bit

C2PO timing

CDROM = 1

CDROM = 0

See Timing Chart 1-1.

CDROM mode; average value interpolation and pre-value hold are not performed.

Audio mode; average value interpolation and pre-value hold are performed.

Processing

Command bit DOUT Mute = 1 DOUT Mute = 0

Digital Out output is muted. (DA output is not muted.) When no other mute conditions are set, Digital Out output is not muted.

Processing

$8X commands

Command bit

DOUT ON/OFF = 1 DOUT ON/OFF = 0

Digital Out is output from the DOUT pin. Digital Out is not output from the DOUT pin.

Processing

Command bit

Sync protection window width WSEL = 1 WSEL = 0

±26 channel clock

∗1

±6 channel clock

Anti-rolling is enhanced. Sync window protection is enhanced.

Application

See the $BX commands.

∗

1

In normal-speed playback, channel clock = 4.3218MHz.

D3

0 0 0 0

D2 D1 D0

Data 4

D3

0 0 0 0

D2 D1 D0

Data 5

D3

TXON

TXOUT

OUTL1 OUTL0

D2 D1 D0

Data 6

– 31 –

CXD2587Q

Command bit

VCOSEL1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Multiplier PLL VCO1 is set to normal speed, and the output is 1/1 frequency-divided.

Multiplier PLL VCO1 is set to normal speed, and the output is 1/2 frequency-divided.

Multiplier PLL VCO1 is set to normal speed, and the output is 1/4 frequency-divided.

Multiplier PLL VCO1 is set to normal speed, and the output is 1/8 frequency-divided.

Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/1 frequency-divided.

Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/2 frequency-divided.

Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/4 frequency-divided.

Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/8 frequency-divided.

KSL3 KSL2

Processing

∗1

Approximately twice the normal speed.

Command bit

TXOUT = 0

Processing

Various signals except for CD TEXT is output from the SQSO pin. CD TEXT data is output from the SQSO pin.

∗

See "§3-13. CD TEXT Data Demodulation"

TXOUT = 1

Command bit

OUTL1 = 0

Processing

WFCK and XPCK are output. WFCK and XPCK outputs are low.OUTL1 = 1

Command bit

OUTL0 = 0 OUTL0 = 1

Processing PCMD, BCK, LRCK and EMPH are output. PCMD, BCK, LRCK and EMPH outputs are low.

Command bit

TXON = 0

Processing When CD TEXT data is not demodulated, set TXON to 0.

When CD TEXT data is demodulated, set TXON to 1.

∗

See "§3-13. CD TEXT Data Demodulation"

TXON = 1

– 32 –

CXD2587Q

Timing Chart 1-1

Rch 16-bit C2 Pointer Lch 16-bit C2 Pointer

If C2 Pointer = 1,

data is NG

C2 Pointer for upper 8bits C2 Pointer for lower 8bits

Rch C2 Pointer

C2 Pointer for upper 8bits C2 Pointer for lower 8bits

Lch C2 Pointer

LRCK

CDROM = 0

CDROM = 1

C2PO

– 33 –

CXD2587Q

$9X commands (OPSL1= 0)

∗

Data 2 D0 and subsequent data are for DF/DAC function settings.

Command bit

DSPB = 1 DSPB = 0

Double-speed playback (CD-DSP block) Normal-speed playback (CD-DSP block)

Processing

Command bit

OPSL1 = 1 OPSL1 = 0

DCOF can be set. DCOF cannot be set.

Processing

Command bit

MCSL = 1 MCSL = 0

DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz) DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz)

Processing

Command

Data 1

D3

0

DSPB

ON/OFF

0

0 0 MCSL 0 0

ZDPL

ZMUT — —

D2 D1 D0 D3

D2

D1 D0 D3 D2 D1 D0

Data 3

Data 4

Data 2

Function specification

000 0

D3 to D1

D0

OPSL1

D3

—

— — —

D2 D1 D0

Data 5

$9X commands (OPSL1= 1)

∗

Data 2 D0 and subsequent data are for DF/DAC function settings.

Command

Data 1

D3

0

DSPB

ON/OFF

0

1 MCSL 0 0 ZDPL ZMUT 0 0

D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0

Data 3

Data 4Data 2

Function specification

000 0

D3 to D1

D0

OPSL1

D3

0 DCOF 0 0

D2 D1 D0

Data 5

– 34 –

CXD2587Q

Command bit

ZDPL = 1 ZDPL = 0

LMUT and RMUT pins are high when muted. LMUT and RMUT pins are low when muted.

Processing

∗

See "Mute flag output" for the mute flag output conditions.

Command bit

DCOF = 1 DCOF = 0

DC offset is off. DC offset is on.

Processing

∗

DCOF can be set when OPSL1 = 1.

∗

Set DC offset to off when zero detection mute is on.

Command bit

ZMUT = 1 ZMUT = 0

Zero detection mute is on. Zero detection mute is off.

Processing

$AX commands (OPSL2 = 0)

∗

Data 2 and subsequent data are for DF/DAC function settings.

Command

Data 1

D3

0

0 Mute ATT 0 0 0 EMPH

D2 D1 D0 D3

D2 D1

D0

Data 2

Data 3

Audio CTRL

SMUT AD10

D3 D2

OPSL2

Data 4

D3

AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

— — — —

D2

D1 D0

D3 D2 D1

D0

D3 D2 D1 D0

Data 5

Data 6Data 3

AD9 AD8

D1 D0

$AX commands (OPSL2 = 1)

∗

Data 2 and subsequent data are for DF/DAC function settings.

Command

Data 1

D3

0 0 Mute

ATT 0 0 1 EMPH

D2 D1 D0 D3 D2 D1 D0

Data 2

Data 3

Audio CTRL

SMUT

AD10

D3 D2

OPSL2

Data 4

D3

AD7 AD6

AD5 AD4

AD3 AD2 AD1 AD0 FMUT LRWO

BSBST

BBSL

D2 D1 D0

D3

D2

D1

D0

D3 D2

D1 D0

Data 5

Data 6

Data 3

AD9

AD8

D1 D0

– 35 –

CXD2587Q

The attenuation data consists of 11 bits, and is set as follows.

Attenuation data

400h

3FEh 3FDh

:

001h 000h

0dB

–0.0085dB –0.0170dB

–60.206dB

– ∞

Audio output

Command bit

EMPH = 1 EMPH = 0

De-emphasis is on. De-emphasis is off.

Processing

∗

If either the EMPHI pin or EMPH is high, de-emphasis is on.

∗

If either the SMUT pin or SMUT is high, soft mute is on.

Command bit

SMUT = 1 SMUT = 0

Soft mute is on. Soft mute is off.

Processing

Command bit

AD10 to 0 Attenuation data.

Meaning

Command bit

Mute = 1 Mute = 0

CD-DSP block mute is on. 0 data is output from the CD-DSP block. CD-DSP block mute is off.

Processing

Command bit

ATT = 1 ATT = 0

CD-DSP block output is attenuated (–12dB). CD-DSP block output attenuation is off.

Processing

Command bit

OPSL2 = 1 OPSL2 = 0

FMUT, LRWO, BSBST and BBSL can be set. FMUT, LRWO, BSBST and BBSL cannot be set.

Meaning

The attenuation data (AD10 to AD0) consists of 11bits, and can be set in 1024 different ways in the range of 000h to 400h. The audio output from 001h to 400h is obtained using the following equation.

Audio output = 20log [dB]

Attenuation data

1024

– 36 –

CXD2587Q

Command bit

FMUT = 1 FMUT = 0

Forced mute is on. Forced mute is off.

Meaning

∗

FMUT can be set when OPSL2 = 1.

Command bit

BSBST = 1 BSBST = 0

Bass boost is on. Bass boost is off.

Processing

∗

BSBST can be set when OPSL2 = 1.

Command bit

BBSL = 1 BBSL = 0

Bass boost is Max. Bass boost is Mid.

Processing

∗

BBSL can be set when OPSL2 = 1.

Command bit

LRWO = 1 LRWO = 0

Forced synchronization mode

Note)

Normal operation.

Meaning

∗

LRWO can be set when OPSL2 = 1.

Note) Synchronization is performed at the first falling edge of LRCK during reset, so there is normally no need

to set this mode. However, synchronization can be forcibly performed by setting LRWO = 1.

– 37 –

CXD2587Q

Command

D3

SL1

SL0

CPUSR

0

D2

D1 D0

TRM1

D3

TRM0

D2

MTSL1

D1

MTSL0

D0

Data 1 Data 2

Serial bus

CTRL

$BX commands

SOCT

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SubQ

Peak meter

SENSDSubQAB

C

SL1 SL0 mode

The SQSO pin output can be switched to the various

signals by setting the SOCT command of $8X and the SL1

and SL0 commands of $BX. Set SQCK to high at the

falling edge of XLAT.

Except for Sub Q and peak meter, the signals are loaded

to the register when they are set at the falling edge of

XLAT. Sub Q is loaded to the register with each SCOR,

and Peak meter is loaded when a peak is detected.

mode A

XLAT

SQCK

mode B

mode C

mode D

Peak meter

PER1 PER2 PER3 PER4 PER5 PER6 PER7 C1F1 0C1F2 C2F1 0C2F2 FOK LOCKGFS EMPH —ALOCK — — — — — — —

— — — — — — — — ALOCK C1F1 C1F2 0 C2F1 0C2F2 FOK LOCKGFS EMPH

PER1 PER2 PER3 PER4 PER5 PER6 PER7PER0 C1F1 C1F2 0 C2F1 0C2F2 FOK LOCKGFS EMPH0

PER0

SPOA C1F1 C1F2 C2F1 C2F2XRAOFFOKGFS

L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7

LOCKEMPH RFCKWFCK SCOR00SPOB GTOP

—

: don't care

– 38 –

CXD2587Q

Signal

PER0 to 7

FOK

GFS LOCK EMPH

ALOCK

SPOA, B

WFCK

SCOR GTOP RFCK

XRAOF

L0 to L7,

R0 to R7

RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB. Focus OK High when the frame sync and the insertion protection timing match. GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight

consecutive samples, a low signal is output. High when the playback disc has emphasis. GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is

output. If GFS is low eight consecutive samples, a low signal is output. SPOA and B pin inputs. Write frame clock output. High when either subcode sync S0 or S1 is detected. High when the sync protection window is open. Read frame clock output. Low when the built-in 16K RAM exceeds the ±4 frame jitter margin. Peak meter register output. L0 to 7 are the left-channel and R0 to 7 are the right-channel peak

data. L0 and R0 are LSB.

Description

C1F1

0 1 1

0 0 1

No Error Single Error Correction Irretrievable Error

C1F2 C1 correction status C2F1

0 1 1

0 0 1

No Error Single Error Correction Irretrievable Error

C2F2 C2 correction status

Command bit

CPUSR = 1 CPUSR = 0

XLON pin is high. XLON pin is low.

Processing

– 39 –

CXD2587Q

Peak meter

SQSO

XLAT

SQCK

(Peak meter)

L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7

Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively, results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data values (absolute value, upper 8bits) for the left and right channels can be read from SQSO by inputting 16 clocks to SQCK. Peak detection is not performed during SQCK input, and the peak register does not change during readout. This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant of 270µs to 400µs. The time during which SQCK input is high should be 270µs or less. Also, peak detection is restarted 270µs to 400µs after SQCK input.

The peak register is reset with each readout (16 clocks input to SQCK). The maximum value in peak detection mode is detected and held in this status until the next readout. When switching to peak detection mode, readout should be performed one time initially to reset the peak register.

Peak detection can also be performed for previous value hold and average value interpolation data.

Traverse monitor count value setting

These bits are set when monitoring the traverse condition of the SENS output according to the COUT frequency division.

Command bit

0 0 1 1

0 1 0 1

1/64 frequency division 1/128 frequency division 1/256 frequency division 1/512 frequency division

TRM1

XUGF MNT1 RFCK

XUGF

XPCK MNT0 XPCK

XPCK

GFS MNT3 XROF

GFS

C2PO C2PO

GTOP

C2PO

MTSL1

0 0 1

Command bit

MTSL0

0 1 0

Symbol

TRM0

Processing

Output data

Monitor output switching

The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B.

– 40 –

CXD2587Q

$CX commands

• CLV mode gain setting: GCLVS

• CLVP mode gain setting: GMDP: GMDS

Servo coefficient setting

CLV CTRL ($DX)

Gain

MDP1

Gain

MDP0

Gain

MDS1

Gain

MDS0

Gain

CLVS

Gain

MDS1

0 0 0 0 1 1

Gain

MDS0

0 0 1 1 0 0

Gain

CLVS

0 1 0 1 0 1

GCLVS

–12dB

–6dB –6dB

0dB 0dB

+6dB

Command

D3

D2

D1

D0

Gain

MDP1

0 0 1

Gain

MDP0

0 1 0

GMDP

–6dB

0dB

+6dB

Gain

MDS1

0 0 1

Gain

MDS0

0 1 0

GMDS

–6dB

0dB

+6dB

$DX commands

Command bit Description

TB = 0 TB = 1 TP = 0 TP = 1

Bottom hold at a cycle of RFCK/32 in CLVS mode. Bottom hold at a cycle of RFCK/16 in CLVS mode. Peak hold at a cycle of RFCK/4 in CLVS mode. Peak hold at a cycle of RFCK/2 in CLVS mode.

Command

D3

0

TB TP

Gain

CLVS

1 1 1 0

0 0 0

0

D2 D1 D0 D3 D2 D1 D0 D3 D2

D1 D0

Data 1

Data 2

CLV CTRL

Data 3

See the $CX commands.

– 41 –

CXD2587Q

$EX commands

Command

Data 1

CLV mode CM3 CM2 CM1 CM0

D3 D2 D1

D0

Data 2

0 0 0 0

D3

D2 D1 D0

Data 3

0 0 0 0

D3

D2 D1

D0

Command bit

CM3

CM2 CM1

Description

Spindle stop mode.

∗1

Spindle forward rotation mode.

∗1

Spindle reverse rotation mode. Valid only when LPWR = 0 in any mode.

∗1

Rough servo mode. When the RF-PLL circuit isn't locked, this mode is used to pull the disc rotations within the RFPLL capture range.

PLL servo mode. Automatic CLVS/CLVP switching mode.

Used for normal playback.

0 1

1

1 0

0 0

0

1

1 1

0 0

1

1 1

CM0

0 0

0

1 0

Mode

STOP

KICK

BRAKE

CLVS

CLVP CLVA

∗1

See Timing Charts 1-2 and 1-3.

Data 4

0 0 0 0

D3 D2 D1 D0

Timing Chart 1-3

MDP

Acceleration

Z

Deceleration

132kHz

7.6µs

n · 236 (ns) n = 0 to 31

Timing Chart 1-2

KICK

MDP

H

KICK

BRAKE

MDP

BRAKE

STOP

MDP

STOP

Z

L

Z

– 42 –

CXD2587Q

§2. Subcode Interface

In the CXD2587Q, only SubQ can be readout. The subcodes P and R to W cannot be readout. Sub Q can be read out after checking CRC of the 80 bits in the subcode frame. Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes correctly and CRCF is high.

§2-1. 80-bit Sub Q Readout

Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register.

• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check circuit.

• 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are loaded into the parallel/serial register. When SQSO goes high 400µs (monostable multivibrator time constant) or more after subcode readout, the CPU determines that the new data (which passed the CRC check) has been loaded.

• The CRCF reset is performed by inputting SQCK. When the subcode data is discontinuous after track jump, etc. CRCF is reset by inputting SQCK. Then, if CRCF =1, the CPU determines that the new data has been loaded.

• When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.

• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read. The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.

• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval, the serial/parallel register is not loaded into the parallel/serial register.

• While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register. In other words, while reading out with a clock cycle shorter than this time constant, the register will not be rewritten by CRCOK and others. (See Timing Chart 2-2.)

• The high and low intervals for SQCK should be between 750ns and 120µs.

– 43 –

CXD2587Q

Block Diagram 2-1

SUBQ

SIN

A B C D E F G H

(AFRAM)

H G F E D C B A

(ASEC)

(AMIN)

80bit S/P Register

ADDRS CTRL

8

Order

Inversion

8

SI

LD

80bit P/S Register

SO

SHIFT

SQCK

CRCF

Mix

SQSO

Mono/Multi

CRCC

SUBQ

SHIFT

– 44 –

CXD2587Q

Timing Chart 2-2

1

2

3

91 92 93 94

95 96 97

98

WFCK

SCOR

SQSO

SQCK

Mono/multi (Internal)

Order

Inversion

CRCF1

Determined by mode

L

CRCF2

80 Clock

Registere load forbidder

270 to 400µs when SQCK = high.

750ns to 120µs

300ns max

CRCF

ADR0

ADR1

ADR2

ADR3

CTL0

CTL1

CTL2

CTL3

SQCK

SQSO

1

2

3

– 45 –

CXD2587Q

§3. Description of Other Functions

§3-1. Channel Clock Regeneration by the Digital PLL Circuit

• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.

Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to 11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result, T, that is the channel clock, is necessary. In an actual player, a PLL is necessary for regenerating the channel clock because the fluctuation in the spindle rotation alters the width of the EFM signal pulses.

The block diagram of this PLL is shown in Fig. 3-1. The CXD2587Q has a built-in three-stage PLL.

• The first-stage PLL regenerates the high-frequency clock needed by the second-stage digital PLL.

• The second-stage PLL is a digital PLL that regenerates the actual channel clock.

Block Diagram 3-1

X'tal

XTSL

OSC

1/M

1/N

Phase comparator

VCO1

VCOSEL1

1/K

(KSL3, 2)

Digital PLL

RFPLL

PCO

FILI

FILO

CLTV

CXD2587Q

– 46 –

CXD2587Q

§3-2. Frame Sync Protection

• In normal-speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is

used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be recognized, the data is processed as error data because the data cannot be recognized. As a result, recognizing the frame sync properly is extremely important for improving playability.

• In the CXD2587Q, window protection and forward protection/backward protection have been adopted for

frame sync protection. These functions achieve very powerful frame sync protection. There are two window widths; one for cases where a rotational disturbance affects the player and the other for cases where there is no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the backward protection counter to 3. Concretely, when the frame sync is being played back normally and then cannot be detected due to scratches, a maximum of 13 frames are inserted. If the frame sync cannot be detected for 13 frames or more, the window opens to resynchronize the frame sync. In addition, immediately after the window opens and the resynchronization is executed, if a proper frame sync cannot be detected within 3 frames, the window opens immediately.

§3-3. Error Correction

• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code

is created with 28-byte information and 4-byte C1 parity. For C2 correction, the code is created with 24-byte information and 4-byte parity. Both C1 and C2 are Reed Solomon codes with a minimum distance of 5.

• The CXD2587Q's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to

achieve high playability.

• The correction status can be monitored externally. See Table 3-2.

• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an

average value interpolation was made for the data.

MNT3

0 0 0 1 1 1

MNT1

0 0 1 0 0 1

MNT0

0 1 1 0 1 0

Description No C1 errors One C1 error corrected C1 correction impossible No C2 errors One C2 error corrected C2 correction impossible

Table 3-2.

– 47 –

CXD2587Q

Timing Chart 3-3

Normal-speed PB

MNT3

MNT1

MNT0

t = Dependent on error

condition

C1 correction C2 correction

Strobe

§3-4. DA Interface

• The CXD2587Q's DA interface is as follows:

Interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is high, the data is for the left channel.

– 48 –

CXD2587Q

Timing Chart 3-4

LRCK

(44.1k)

BCK

(2.12M)

PCMD

LRCK

(88.2k)

BCK

(4.23M)

PCMD

48-bit slot Normal-Speed Playback

1

24

R0

Lch MSB (15)

L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 RMSB

R0

Lch MSB (15)

24

Rch MSB

2 3 4 5 6 7 8 9 10 11 12

48-bit slot Double-Speed Playback

1 2

L0

– 49 –

CXD2587Q

§3-5. Digital Out

There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use, and the type 2 form 2 format for the manufacture of software. The CXD2587Q supports type 2 form 1. Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3) of the channel status.

Table 3-5.

§3-6. Servo Auto Sequence

This function performs a series of controls, including auto focus and track jumps. When the auto sequence command is received from the CPU, auto focus, 1-track jump, 2N-track jump and N-track move are executed automatically. The commands which enable transfer to the CXD2587Q during the execution of auto sequence are $4X to $EX. When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of 100µs after that point.

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0

ID0

ID1

COPY

Emph

0 0 0 0 1 0 0 0 0 0 0 0

From sub Q

0

16

32

48

176

Bits 0 to 3 Sub Q control bits that matched twice with CRCOK

Digital Out C bit

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

– 50 –

CXD2587Q

(a) Auto focus ($47)

Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on. If $47 is received from the CPU, the focus servo is turned on according to Fig. 3-6. The auto focus starts with focus search-up, and note that the pickup should be lowered beforehand (focus search down). In addition, blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling edge of FZC after FZC has been continuously high for a longer time than E.

Auto focus

Focus search up

FOK = H

NO

YES

FZC = H

NO

YES

FZC = L

NO

YES

END

Focus servo ON

(Check whether FZC is continuously high for the period of time E set with register 5.)

Fig. 3-6-(a). Auto Focus Flow Chart

– 51 –

CXD2587Q

Fig. 3-6-(b). Auto Focus Timing Chart

(b) Track jump

1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled servos are on. Note that tracking gain-up and braking-on should be sent beforehand because they are not involved in this sequence.

• 1-track jump When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance with Fig. 3-7. Set blind A and brake B with register 5.

• 10-track jump When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance with Fig. 3-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than the overflow C set with register 5), the tracking and sled servos are turned on.

• 2N-track jump When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance with Fig. 3-9. The track jump count N is set with register 7. Although N can be set to 2

16

tracks, note that the setting is actually limited by the actuator. COUT is used for counting the number of jumps. Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.

• N-track move When $4E ($4F for REV) is received from the CPU, a FWD (REV) N-track move is performed in accordance with Fig. 3-10. N can be set to 216tracks. COUT is used for counting the number of jumps. The N-track move is executed only by moving the sled, and is therefore suited for moving across several thousand to several ten-thousand tracks.

XLAT

FOK

(FZC)

BUSY

Command for

DSSP

$47latch

$03

Blind E

$08

– 52 –

CXD2587Q

Fig. 3-7-(a). 1-Track Jump Flow Chart

Track

NO

YES

END

Track FWD kick

sled servo OFF

WAIT

(Blind A)

COUT =

Track REV

kick

WAIT

(Brake B)

Track, sled

servo ON

(FWD kick for REV jump)

(REV kick for REV jump)

Fig. 3-7-(b). 1-Track Jump Timing Chart

XLAT

COUT

BUSY

Command for

DSSP

$48 (REV = $49) latch

$28 ($2C)

Blind A

Brake B

$2C ($28)

$25

– 53 –

CXD2587Q

Fig. 3-8-(a). 10-Track Jump Flow Chart

10 Track

NO

YES

END

Track, sled

FWD kick

WAIT

(Blind A)

COUT = 5 ?

Track, REV

kick

Track, sled

servo ON

(Check whether the COUT cycle is longer than overflow C.)

(Counts COUT × 5)

NO

YES

C = Overflow ?

Fig. 3-8-(b). 10-Track Jump Timing Chart

XLAT

COUT

BUSY

Command for

DSSP

$4A (REV = $4B) latch

Blind A

$2A ($2F)

COUT 5 count

$2E ($2B)

Overflow C

$25

– 54 –

CXD2587Q

Fig. 3-9-(a). 2N-Track Jump Flow Chart

2N Track

NO

YES

END

Track, sled

FWD kick

WAIT

(Blind A)

COUT = N

Track REV

kick

Track servo

ON

NO

YES

C = Overflow

WAIT

(Kick D)

Sled servo

ON

Fig. 3-9-(b). 2N-Track Jump Timing Chart

XLAT

BUSY

Command for

DSSP

Blind A

$2A ($2F)

COUT N count

$2E ($2B)

Overflow C

Kick D

$26 ($27)

$25

$4C (REV = $4D) latch

COUT

– 55 –

CXD2587Q

Fig. 3-10-(a). N-Track Move Flow Chart

N Track move

NO

YES

END

Track servo OFF

Sled FWD kick

WAIT

(Blind A)

COUT = N

END

Track, sled servo OFF

Fig. 3-10-(b). N-Track Move Timing Chart

XLAT

BUSY

Command for

DSSP

$22 ($23)

Blind A

COUT N count

$20

$4E (REV = $4F) latch

COUT

– 56 –

CXD2587Q

§3-7. Digital CLV

Fig. 3-11 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes. In addition, the digital spindle servo gain is variable.

Digital CLV

CLVS U/D

MDS Error

MDP Error

CLV P/S

Measure

2/1 MUX

Oversampling

Filter-1

Gain MDS

1/2

MUX

CLV P/S

Oversampling

Filter-2

Noise Shape

Modulation

KICK, BRAKE, STOP

MDP

Gain MDP

CLVS U/D :Up/down signal from CLVS servo MDS error: Frequency error for CLVP servo MDP error: Phase error for CLVP servo

Fig. 3-11. Block Diagram

– 57 –

CXD2587Q

§3-8. CD-DSP Block Playback Speed

In the CXD2587Q, the following playback modes can be selected through different combinations of the crystal, XTSL pin and the DSPB command of $9X.

CD-DSP block playback speed

Crystal

768Fs 768Fs 768Fs 384Fs 384Fs 384Fs

0 1 1 0 0 1

1 0 1 0 1 1

4×

∗1

1× 2× 1× 2×

1×

∗2

XTSL DSPB CD-DSP block playback speed

Fs = 44.1kHz.

∗1

In 4× speed playback, the timer value for the auto sequence is halved.

∗2

Low power consumption mode. The CD-DSP processing speed is halved, allowing power consumption to be reduced.

§3-9. DAC Block Playback Speed

The operation speed for the DAC block is determined by the crystal and the MCSL command of $9X regardless of the CD-DSP operating conditions noted above. This allows the playback modes for the DAC and CD-DSP blocks to be set independently.

1-bit DAC block playback speed

Crystal

768Fs 768Fs 384Fs

1 0 0

1× 2× 1×

MCSL DAC block playback speed

Fs = 44.1kHz.

– 58 –

CXD2587Q

§3-10. Description of DAC Block Functions

Zero data detection

When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or all "1" has continued about for 300ms, zero data is detected. Zero data detection is performed independently for the left and right channels.

Mute flag output

The LMUT and RMUT pins go active when any one of the following conditions is met. The polarity can be selected with the ZDPL command of $9X.

• When zero data is detected

• When a high signal is input to the SYSM pin

• When the SMUT command of $AX is set

Attenuation operation

Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and Y3 (Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1 continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then approaches Y3 from the value (B or C in the figure) at that point.

A

Y1

B

Y3

C

Y2

23.2 [ms]

– ∞ 000 (H)

0dB

3FF (H)

– 59 –

CXD2587Q

DAC block mute operation

Soft mute

Soft mute results and the input data is attenuated to zero when any one of the following conditions is met.

• When attenuation data of "000" (high) is set

• When the SMUT command of $AX is set to 1

• When a high signal is input to the SYSM input pin

Forced mute

Forced mute results when the FMUT command of $AX is set to 1. Forced mute fixes the PWM output that is input to the LPF block to low.

∗

When setting FMUT, set OPSL2 to 1. (See the $AX commands.)

Zero detection mute

Forced mute is applied when the ZMUT command of $9X is set to 1 and the zero data is detected for the left and right channels. (See "Zero data detection".) When the ZMUT command of $9X is set to 1, the forced mute is applied even if the mute flag output condition is met. When the zero detection mute is on, set the DCOF command of $9X to 1.

Soft mute on Soft mute offSoft mute off

23.2 [ms] 23.2 [ms]

0dB

– ∞dB

– 60 –

CXD2587Q

Normal DBB MID DBB MAX

10.00

–4.00

6.00

4.00

2.00

0.00

–2.00

8.00

–6.00

–8.00 –10.00 –12.00 –14.00

10 30 100 300 1k 3k 10k 30k

Digital Bass Boost Frequency Response [Hz]

[dB]

Graph 3-12.

LRCK Synchronization

Synchronization is performed at the first falling edge of the LRCK input during reset. After that, synchronization is lost when the LRCK input frequency changes and resynchronization must be performed. The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed changes such as the following cases.

• When the XTSL pin switches between high and low

• When the DSPB command of $9X setting changes

• When the MCSL command of $9X setting changes

LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC block. Resynchronization must be performed in this case as well. For resynchronization, set the LRWO command of $AX to 1, wait for one LRCK cycle or more, and then set LRWO to 0.

∗

When setting LRWO, set OPSL2 to 1. (See the $AX commands.)

Digital Bass Boost

Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels: Mid. and Max. BSBST and BBSL of address A are used for the setting. See Graph 3-12 for the digital bass boost frequency response.

– 61 –

CXD2587Q

Analog out

C2

680p

12k

C1

150p

AOUT1 (2)

AIN1 (2)

LOUT1 (2)

Vc

Fig. 3-13. LPF External Circuit

§3-11. LPF Block

The CXD2587Q contains an initial-stage secondary active LPF with numerous resistors and capacitors and an operational amplifier with reference voltage. The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly. The reference voltage (VC) is (AVDD – AVSS) × 0.43.

The LPF block application circuit is shown below. In this circuit, the cut-off frequency is fc ≈ 40kHz.

The external capacitors' values when fc = 30kHz and 50kHz are noted below as a reference. The resistors' values do not change at this time.

• When fc ≈ 30kHz: C1 = 200pF, C2 = 910pF

• When fc ≈ 50kHz: C1 = 120pF, C2 = 560pF

LPF Block Application Circuit

– 62 –

CXD2587Q

§3-12. Asymmetry Compensation

Fig. 3-14 shows the block diagram and circuit example.

RFAC

R1

ASYO

ASYI

R1 2 R2 5

=

BIAS

R1

R2

CXD2587Q

Fig. 3-14. Asymmetry Compensation Application Circuit

– 63 –

CXD2587Q

§3-13. CD TEXT Data Demodulation

• In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to 1.

It requires 26.7ms (max.) to demodulate the CD TEXT data correctly after TXON is set to 1.

• The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is enabled by setting the command $8 Data 6 D2 TXOUT to 1. To read data, the readout clock should be input to SQCK.

• The readable data are the CRC counting results for the each pack and the CD TEXT data (16 bytes) except for CRC data.

• When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result, although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.

• Data which can be stored in the LSI is 1 packet (4 packs).

Fig. 3-15. Block Diagram of CD TEXT Demodulation Circuit

SQCK

SQSO

TXOUT

Subcode

Decoder

CD TEXT

Decoder

– 64 –

CXD2587Q

CRC

4

CRC

3

CRC

2

CRC

1

0

0 0 0

S2 R2 W1 V1 U1 T1 S1 R1 U3 T3 S3 R3 W2 V2 U2 T2 W4 V4 U4 T4 S4

CRC Data

ID1 (Pack1)

ID2 (Pack1)

ID3 (Pack1)

16 Bytes

4 bits

Subcode Q Data

SCOR

TXOUT

(command)

SQCK

SQSO

SQCK

TXOUT

(command)

LSB

MSB

LSB MSB

LSB

CRC

0

Pack1

Pack2

Pack3

Pack4

CRCF

80 clocks

SQSO

520 clocks

Fig. 3-16. CD TEXT DATA Timing Chart

– 65 –

CXD2587Q

§4. Description of Servo Signal Processing System Functions and Commands

§4-1. General Description of the Servo Signal Processing System (VDD: Supply voltage)

Focus servo

Sampling rate: 88.2kHz (when MCK = 128Fs) Input range: 0.3VDD to 0.7VDD Output format: 7-bit PWM Other: Offset cancel

Focus bias adjustment Focus search Gain-down function Defect countermeasure Auto gain control

Tracking servo

Sampling rate: 88.2kHz (when MCK = 128Fs) Input range: 0.3VDD to 0.7VDD Output format: 7-bit PWM Other: Offset cancel

E:F balance adjustment Track jump Gain-up function Defect countermeasure Drive cancel Auto gain control Vibration countermeasure

Sled servo

Sampling rate: 345Hz (when MCK = 128Fs) Input range: 0.3VDD to 0.7VDD Output format: 7-bit PWM Other: Sled move

FOK, MIRR, DFCT signal generation

RF signal sampling rate: 1.4MHz (when MCK = 128Fs) Input range: 0.43VDD to VDD Other: RF zero level automatic measurement

– 66 –

CXD2587Q

§4-2. Digital Servo Block Master Clock (MCK)

The clock with the 2/3 frequency of the crystal is supplied to the digital servo block. The XT4D and XT2D command can be set with D13 and D12 of $3F, and the XT1D command can be set with D1 of $3E. (Default = 0) The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical.

Mode

1 2 3 4 5 6 7

384Fs 384Fs 384Fs 768Fs 768Fs 768Fs 768Fs

256Fs 256Fs 256Fs 512Fs 512Fs 512Fs 512Fs

∗ ∗

0

∗ ∗ ∗

1

∗ ∗

0

∗ ∗

1 0

∗

1 0

∗

1 0 0

1 0 0 1 0 0 0

1 1/2 1/2

1 1/2 1/4 1/4

256Fs 128Fs 128Fs 512Fs 256Fs 128Fs 128Fs

XTLI Input to servo XTSL XT4D XT2D XT1D Frequency division ratio MCK

Fs = 44.1kHz, ∗: Don’t care

Table 4-1.

§4-3. AVRG (Average) Measurement and Compensation

The CXD2587Q has a circuit that measures the averages of RFDC, VC, FE and TE and a circuit that compensates these signals to control the servo effectively. AVRG measurement and compensation is necessary to initialize the CXD2587Q, and is able to cancel the offset. The level applied to the VC, FE, RFDC and TE pins can be measured by setting D15 (VCLM), D13 (FLM), D11 (RFLM) and D4 (TCLM) of $38 respectively to 1. AVRG measurement takes the level applied to each analog input pin as the average of 256 samples, and then loads each value into the AVRG register. AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is received. During AVRG measurement, if the upper 8 bits of the command register are 38 (Hex), the completion of AVRG measurement operation can be confirmed through the SENS pin. (See Timing Chart 4-2.)

XLAT

SENS (= XAVEBSY)

Max. 1µs

AVRG measurement completed

2.9 to 5.8ms

Timing Chart 4-2.

– 67 –

CXD2587Q

• VC AVRG The offset can be canceled by measuring the VC level which is the center voltage for the system and using that value to apply compensation to each input error signal.

• FE AVRG The FE signal DC level is measured. In addition, compensation is applied to the FZC comparator level output from the SENS pin during FCS SEARCH (focus search) using these measurement results.

• TE AVRG The TE signal DC level is measured.

• RF AVRG The MIRR, DFCT and FOK signals are generated from the RF signal. Since the FOK signal is generated by comparing the RF signal at a certain level, it is necessary to establish a zero level which becomes the comparator level reference. Therefore, the RF signal is measured before playback, and is compensated to take this level as the zero level.

An example of sending AVRG measurement and compensation commands is shown below. (Example) $380800 (RF AVRG measurement on)

$382000 (FE AVRG measurement on) $380010 (TE AVRG measurement on) $388000 (VC AVRG measurement on) (Complete each AVRG measurement before starting the next.) $38140A (RFLC, FLC0, FLC1 and TLC1 commands on)

(The required compensation should be turned on together; see Fig. 4-3.) An interval of 5.8ms (when MCK = 128Fs) or more must be maintained between each command, or the SENS pin must be monitored to confirm that the previous command has been completed before the next AVRG command is sent.

See Fig. 4-3 for the contents of each compensation below.

• RFLC

The difference by which the RF signal exceeds the RF AVRG value is input to the RF In register. (00 is input when the RF signal is lower than the RF AVRG value.)

• TCL0

The value obtained by subtracting the VC AVRG value from the TE signal is input to the TRK In register.

• TCL1

The value obtained by subtracting the TE AVRG value from the TE signal is input to the TRK In register.

• VCLC

The value obtained by subtracting the VC AVRG value from the FE signal is input to the FCS In register.

• FLC1

The value obtained by subtracting the FE AVRG value from the FE signal is input to the FCS In register.

• FLC0

The value obtained by subtracting the FE AVRG value from the FE signal is input to the FZC register.

– 68 –

CXD2587Q

§4-4. E:F Balance Adjustment Function

When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search), the traverse waveform appears in the TE signal due to disc eccentricity. In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold filter by setting D5 (TBLM) of $38 to 1. The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC register value is established when TBLM returns to 0. Next, setting D2 (TLC2) of $38 to 1 compensates TE and SE values with the TRVSC register value (subtraction), resulting the E:F balance offset to be adjusted. (See Fig. 4-3.)

§4-5. FCS Bias (Focus Bias) Adjustment Function

The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See Fig. 4-3.) When the FBIAS register value is set when D11 = 0 and D10 = 1 with $34F, data can be written using the 9-bit value of D9 to D1 (D9: MSB). In addition, the RF jitter can be monitored by setting the SOCT command of $8 to 1. (See "DSP Block Timing Chart".)

The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0. The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A.

When using the FBIAS register as a counter, the counter stops if the FBIAS value and the value set beforehand in FBL9 to 1 of $34 match. Also, if the upper 8 bits of the command register are $3A at this time, SENS becomes high and the counter stop can be monitored.

A B C

FBIAS setting value (FB9 to 1)

LIMIT value (FBL9 to 1)

SENS pin

A: Register mode B: Counter mode C: Counter mode (when stopped)

Here, assume the FBIAS setting value FB9 to 1 and the FBIAS LIMIT value FBL9 to 1 like status A. For example, if command registers FBUP = 0, FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from this status, down count starts from status A and approaches the set LIMIT value. When the FBIAS value matches FBL9 to 1, the counter stops and the SENS pin goes to high. Note that the up/down counter counts at each sampling cycle of the focus servo filter. The number of steps by which the count value changes can be selected from 1, 2, 4 or 8 steps by FBV1 and FBV0. When converted to FE input, 1 step corresponds to 1/512 × VDD × 0.4.

– 69 –

CXD2587Q

TE AVRG

register

TLC1

TRVSC

register

TLC2

– –

To TRK In register

VC AVRG

register

TLC0

–

VCLC

–

TE from A/D

FE AVRG

register

FLC1

FBIAS

register

FBON

–

To FCS In register

FLC0

To FZC register

FE from A/D

–

RFLC

–

To RF In registerRFDC from A/D

RF AVRG

register

– –

To SLD In register

–

SE from A/D

TLC0 · TLD0 TLC1 · TLD1 TLC2 · TLD2

Fig. 4-3.

– 70 –

CXD2587Q

§4-6. AGCNTL (Automatic Gain Control) Function

The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate gain with the servo loop. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but also obtains the optimal gain for each disc. The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of the command register are 38 (Hex), the completion of AGCNTL operation can be confirmed through the SENS pin. (See Timing Chart 4-4 and "Description of SENS Signals".) Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation.

Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described

hereafter) must be disabled.

XLAT

SENS (= AGOK)

Max. 11.4µs

AGCNTL completion

Timing Chart 4-4.

Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking AGCNTL) due to AGCNTL. These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written externally. After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from the SENS pin with the serial readout function (described hereafter).

AGCNTL related settings

The following settings can be changed with $35, $36 and $37. FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex) TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex) AGS; Self-stop on/off AGJ; Convergence completion judgment time AGGF; Internally generated sine wave amplitude (AGF) AGGT; Internally generated sine wave amplitude (AGT) AGV1; AGCNTL sensitivity 1 (during rough adjustment) AGV2; AGCNTL sensitivity 2 (during fine adjustment) AGHS; Rough adjustment on/off AGHT; Fine adjustment time

Note) Converging servo loop gain values can be changed with the FG6 to 0 and TG6 to 0 setting values. In

addition, these setting values must be within the effective setting range. The default settings aim for 0 dB at 1kHz. However, since convergence values vary according to the characteristics of each constituent element of the servo loop, FG and TG values should be set as necessary.

– 71 –

CXD2587Q

AGCNTL and default operation have two stages. In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select 256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value. The sensitivity at this time can be selected from two types with AGV1. In the second stage, the AGCNTL coefficient is finely adjusted to approach more appropriate value with relatively low sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops changing, the CXD2587Q confirms that the AGCNTL coefficient has not changed for a certain period of time (select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode) This self-stop mode can be canceled by setting AGS to 0. In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0. An example of AGCNTL coefficient transitions during AGCNTL in various settings are shown in Fig. 4-5.

Initial value

SENS

AGCNTL Start

AGCNTL completion

Convergence value

AGCNTL coefficient value

Slope AGV1

AGHT

AGJ

Slope AGV2

Fig. 4-5.

Note) Fig. 4-5 shows the example where the AGCNTL coefficient value converges to the smaller value from

the initial value.

– 72 –

CXD2587Q

§4-7. FCS Servo and FCS Search (Focus Search)

The FCS servo is controlled by the 8-bit serial command $0X. (See Table 4-6.)

Register name

Command

D23 to D20

D19 to D16

1 0 ∗ ∗ 1 1 ∗ ∗ 0 ∗ 0 ∗ 0 ∗ 1 ∗ 0 ∗ 1 0 0 ∗ 1 1

FOCUS SERVO ON (FOCUS GAIN NORMAL) FOCUS SERVO ON (FOCUS GAIN DOWN) FOCUS SERVO OFF, 0V OUT FOCUS SER VO OFF, FOCUS SEARCH VOLTAGE OUT FOCUS SEARCH VOLTAGE DOWN FOCUS SEARCH VOLTAGE UP

0 0 0 0

FOCUS CONTROL

0

Table 4-6.

FCS Search

FCS search is required in the course of turning on the FCS servo.

Fig. 4-7 shows the signals for sending commands $00 → $02 → $03 and performing only FCS search operation. Fig. 4-8 shows the signals for sending $08 (FCS on) after that.

FCSDRV

RF

FOK

FE

FZC

FZC comparator level

$00 $02 $03

0

FCSDRV

RF

FOK

FE

FZC

$00 $02 $03

0

$08

Fig. 4-7. Fig. 4-8.

∗: Don’t care

– 73 –

CXD2587Q

§4-8. TRK (Tracking) and SLD (Sled) Servo Control

The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 4-9.) When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin.

D23 to D20

D19 to D16

0 0 ∗ ∗ 0 1 ∗ ∗ 1 0 ∗ ∗ 1 1 ∗ ∗

∗ ∗ 0 0 ∗ ∗ 0 1 ∗ ∗ 1 0 ∗ ∗ 1 1

TRACKING SERVO OFF TRACKING SERVO ON FORWARD TRACK JUMP REVERSE TRACK JUMP SLED SERVO OFF SLED SERVO ON FORWARD SLED MOVE REVERSE SLED MOVE

0 0 1 0

TRACKING MODE

2

Table 4-9.

TRK Servo

The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36. In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode. The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the anti-shock circuit (described hereafter) enabled. The CXD2587Q has 2 types of filters in TRK gain-up mode which can be selected by setting D16 of $1. (See Table 4-17.)

SLD Servo

The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by multiplying this value by 1×, 2×, 3× or 4× magnification set using D17 and D16 when D18 = D19 = 0 is set with $3. (See Table 4-10.) SLD MOV must be performed continuously for 50µs or more. In addition, if the LOCK input signal goes low when the SLD servo is on, the SLD servo turns off.

Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off

by the default. These operations are disabled by setting D6 (LKSW) of $38 to 1.

D23 to D20

D19 to D16

0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1

SLED KICK LEVEL (basic value × ±1) SLED KICK LEVEL (basic value × ±2) SLED KICK LEVEL (basic value × ±3) SLED KICK LEVEL (basic value × ±4)

0 0 1 1

SELECT

3

Table 4-10.

∗: Don’t care

Register name

Command

Register name

Command

– 74 –

CXD2587Q

§4-9. MIRR and DFCT Signal Generation

The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and loaded. The MIRR and DFCT signals are generated from this RF signal.

MIRR Signal Generation

The loaded RF signal is applied to peak hold and bottom hold circuits. An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is generated from the average of this envelope waveform. The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value from the peak hold value with this MIRR comparator level. (See Fig. 4-11.) The bottom hold speed and mirror sensitivity can be selected from 4 values using D7 and 6, and D5 and 4, respectively, of $3C.

RF

Peak Hold

Bottom Hold

Peak Hold – Bottom Hold

MIRR

MIRR Comp (Mirror comparator level)

H L

RF

Peak Hold1

Peak Hold2

– Peak Hold1

DFCT

(Defect comparator level)

H L

SDF

Fig. 4-11.

DFCT Signal Generation

The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is generated by comparing the difference between these two peak hold waveforms with the DFCT comparator level. (See Fig. 4-12.) The DFCT comparator level can be selected from four values using D13 and D12 of $3B.

Fig. 4-12.

– 75 –

CXD2587Q

§4-10. DFCT Countermeasure Circuit

The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become easily dislocated due to scratches or defects on discs. Specifically, these operations are achieved by detecting scratch and defect with the DFCT signal generation circuit, and when DFCT goes high, applying the low-frequency component of the error signal before DFCT went high to the FCS and TRK servo filter inputs. (See Fig. 4-13.) In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38 to 1.

Input register

Hold register

Hold Filter

Servo Filter

EN

Error signal

DFCT

Fig. 4-13.

§4-11. Anti-Shock Circuit

When vibrations occurs in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures. Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is increased. (See Fig. 4-14.) The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator level is practically variable by adjusting the value of the anti-shock filter output coefficient K35. This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See Table 4-17.) This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up mode by inputting high level to the ATSK pin. When the upper 4 bits of the command register are 1 (Hex), vibration detection can be monitored from the SENS pin. It also can be monitored from the ATSK pin by setting the ASOT command of $3F to 1.

TE

Anti Shock

Filter

TRK Gain Up

Filter

TRK Gain Normal

Filter

TRK

PWM Gen

ATSK

SENS

Comparator

Fig. 4-14.

– 76 –

CXD2587Q

§4-12. Brake Circuit

Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to turn on. The brake circuit prevents these phenomenon. The brake circuit is to use tracking drive as a brake by cutting unnecessary portions of it utilizing the 180° offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 4-15 and 4-16.) Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal. The brake circuit can be turned on and off by D18 of $1. (See Fig. 4-17.)

TRK DRV

FWD

JMP

REV

JMP

Servo ON

RF Trace

MIRR

TE

0

TZC Edge

TRKCNCL

TRK DRV

SENS TZC out

Inner track Outer track

TRK DRV

REV JMP

FWD

JMP

Servo ON

RF Trace

MIRR

TE 0

0

TZC Edge

TRKCNCL

TRK DRV

SENS TZC out

Outer track Inner track

Fig. 4-15. Fig. 4-16.

D23 to D20

D19 to D16

1 0 ∗ ∗ 0 ∗ ∗ ∗

∗ 1 ∗ ∗ ∗ 0 ∗ ∗ ∗ ∗ 0 ∗ ∗ ∗ 1 ∗ ∗ ∗ ∗ 1 ∗ ∗ ∗ 0

ANTI SHOCK ON ANTI SHOCK OFF BRAKE ON BRAKE OFF TRACKING GAIN NORMAL TRACKING GAIN UP TRACKING GAIN UP FILTER SELECT 1 TRACKING GAIN UP FILTER SELECT 2

0 0 0 1

TRACKING CONTROL

1

Fig. 4-17.

∗: Don’t care

Register name

Command

– 77 –

CXD2587Q

§4-13. COUT Signal

The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by loading the MIRR signal at both edges of the TZC signal. And the used TZC signal can be selected among three different phases for each COUT signal application.

• HPTZC: For 1-track jumps Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a cut-off 1kHz digital HPF; when MCK = 128Fs.)

• STZC: For COUT signal generation when MIRR is externally input and for applications other than COUT generation. This is generated from sampling TE at 700kHz. (when MCK = 128Fs)

• DTZC: For high-speed traverse Reliable COUT signal generation with a delayed phase STZC signal.

Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance with the MIRR signal delay during high-speed traverse. The COUT signal output method is switched with D15 and 14 of $3C.

When D15 = 1 : STZC When D15 = 0 and D14 = 0 : HPTZC When D15 = 0 and D14 = 1 : DTZC

When the DTZC is selected, the delay can be selected from two values with D14 of $36.

§4-14. Serial Readout Circuit

The following measurement and adjustment results can be read out from the SENS pin by inputting the readout clock to the SCLK pin by $39. (See Fig. 4-18, Table 4-19 and "Description of SENS Signals".)

Specified commands

$390C: VC AVRG measurement result $3908: FE AVRG measurement result $3904: TE AVRG measurement result $391F: RF AVRG measurement result $3953: FCS AGCNTL coefficient result $3963: TRK AGCNTL coefficient result $391C: TRVSC adjustment result $391D: FBIAS register value

•••

tDLS

tSPW

1/fSCLK

MSB LSB

XLAT

SCLK

Serial Read Out Data (SENS)

Item

Symbol

Min.

Typ.

Max.

Unit SCLK frequency SCLK pulse width Delay time

fSCLK

tSPW tDLS

31.3 15

16

MHz

ns µs

Table 4-19.

During readout, the upper 8 bits of the command register must be 39 (Hex).

Fig. 4-18.

– 78 –

CXD2587Q

§4-15. Writing to the Coefficient RAM

The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and transfer from the ROM to the RAM is completed approximately 40µs (when MCK = 128Fs) after the XRST pin rises. (The coefficient RAM cannot be rewritten during this period.) After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address of the coefficient RAM. The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and D7 to D0 as data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is received. When rewriting multiple coefficients, be sure to wait 11.3µs (when MCK = 128Fs) before sending the next rewrite command.

§4-16. PWM Output

FCS, TRK and SLD outputs are output as PWM waveforms. A double oversampling noise shaper is used for FCS and TRK. Timing Chart 4-20 and Fig. 4-21 show examples of output waveforms and drive circuits.

tMCK = ≈ 180ns

Timing Chart 4-20.

64tMCK

64tMCK 64tMCK

AtMCK

SFDR

SRDR

SLD

32tMCK 32tMCK 32tMCK 32tMCK32tMCK32tMCK

FCS/TRK

FFDR/ TFDR

FRDR/ TRDR

Output value +A Output value –A Output value 0

t

MCK

A 2

tMCK

A 2

tMCK

A

2

tMCK

A 2

MCK (5.6448MHz) ↑ ↑ ↑ ↑ ↑ ↑ ↑

1

5.6448MHz

– 79 –

CXD2587Q

Example of Driver Circuit

RDR

FDR

22k

DRV

V

CC

VEE

Fig. 4-21. Driver Circuit

– 80 –

CXD2587Q

§4-17. Servo Status Changes Produced by the LOCK Signal

When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off in order to prevent SLD free-running. Setting D6 (LKSW) of $38 to 1 deactivates this function. In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low. This enables microcomputer control.

§4-18. Description of Commands and Data Sets

The following description contains portions which convert internal voltages into the values when they are output externally and describe them as input conversion or output conversion. Input conversion converts these voltages into the voltages entering input pins before A/D conversion. Output conversion converts PWM output values into analog voltage values.

– 81 –

CXD2587Q

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 KA6 KA5 KA4 KA3 KA2 KA1 KA0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0

When D15 = 0

KA6 to KA0: Coefficient address KD7 to KD0: Coefficient data

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 1 1 0 1 FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1 —

When D15 = D14 = D13 = D12 = 1 ($34F)

D11 = 0, D10 = 1 FBIAS register write FB9 to FB1: Data; FB9 is MSB two's complement data.

For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 × VDD/5 and FB9 to FB1 = 100000000 to –256/256 × VDD/5 respectively. (VDD: supply voltage)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 1 1 1 0 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 —

When D15 = D14 = D13 = D12 = D11 = 1 ($34F)

D10 = 0 FBIAS LIMIT register write FBL9 to FBL1: Data; data compared with FB9 to 1, FBL9 = MSB.

When using the FBIAS register in counter mode, counter operation stops when the value of FB9 to 1 matches with FBL9 to 1.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1 1 1 1 0 0 TV9 TV8 TV7 TV6 TV5 TV4 TV3 TV2 TV1 TV0

When D15 = D14 = D13 = D12 = 1 ($34F)

D11 = 0, D10 = 0 TRVSC register write TV9 to TV0: Data; TV9 is MSB two's complement data.

For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 × VDD/5 and TV9 to TV0 = 1100000000 to –256/256 × VDD/5 respectively. (VDD: supply voltage)

Note) • When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to

each bit TV8 to TV0 during external write are read out.

• When reading out internally measured values and then writing these values externally, set TV9 the same as TV8.

$34

– 82 –

CXD2587Q

$35 (preset: $35 58 2D)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FT1 FT0 FS5 FS4 FS3 FS2 FS1 FS0 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0

FT1, FT0, FTZ: Focus search-up speed

Default value: 010 (0.673 × VDD V/s) Focus drive output conversion

FT1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

0 0 0 0 1 1 1 1

1.35 × VDD

0.673 × VDD

0.449 × VDD

0.336 × VDD

1.79 × VDD

1.08 × VDD

0.897 × VDD

0.769 × VDD

FT0 FTZ Focus search speed [V/s]

FS5 to FS0: Focus search limit voltage

Default value: 011000 (±24/64 × VDD, VDD: PWM driver supply voltage) Focus drive output conversion

FG6 to FG0: AGF convergence gain setting value

Default value: 0101101

$36 (preset: $36 0E 2E)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

TDZC DTZC TJ5 TJ4 TJ3 TJ2 TJ1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0

TDZC: Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation.

TDZC = 0: the edge of the HPTZC or STZC signal, whichever has the faster phase, is used. TDZC = 1: the edge of the HPTZC or STZC signal or the tracking drive signal zero-cross, whichever has the faster phase, is used. (See §4-12.)

DTZC: DTZC delay (8.5/4.25µs, when MCK = 128Fs)

Default value: 0 (4.25µs)

TJ5 to TJ0: Track jump voltage

Default value: 001110 (≈ ±14/64 × VDD, VDD: PWM driver supply voltage) Tracking drive output conversion

SFJP: Surf jump mode on/off

The tracking PWM output is made by adding the tracking filter output and TJReg (TJ5 to 0), by setting D7 to 1 (on)

TG6 to TG0: AGT convergence gain setting value

Default value: 0101110

∗

∗: preset, VDD: PWM driver supply voltage

– 83 –

CXD2587Q

$37 (preset: $37 50 BA)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ

AGGF AGGT

AGV1 AGV2

AGHS AGHT

FZSH, FZSL: FZC (Focus Zero Cross) slice level

Default value: 01 (1/8 × VDD × 0.4, VDD: supply voltage); FE input conversion

FZSH

0 0 1 1

0 1 0 1

1/4 × VDD × 0.4 1/8 × VDD × 0.4 1/16 × VDD × 0.4 1/32 × VDD × 0.4

FZSL Slice level

SM5 to SM0: Sled move voltage

Default value: 010000 (≈ ±16/64 × VDD, VDD: PWM driver supply voltage) Sled drive output conversion

AGS: AGCNTL self-stop on/off

Default value: 1 (on)

AGJ: AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms,

when MCK = 128Fs) Default value: 0 (63ms)

AGGF: Focus AGCNTL internally generated sine wave amplitude (small/large)

Default value: 1 (large)

AGGT: Tracking AGCNTL internally generated sine wave amplitude (small/large)

Default value: 1 (large)

AGGF

0 (small) 1 (large)

∗

1/32 × VDD × 0.4 1/16 × VDD × 0.4

1/16 × VDD × 0.4 1/8 × VDD × 0.4

AGGT

0 (small) 1 (large)

∗

FE/TE input conversion

AGV1: AGCNTL convergence sensitivity during high sensitivity adjustment; high/low

Default value: 1 (high)

AGV2: AGCNTL convergence sensitivity during low sensitivity adjustment; high/low

Default value: 0 (low)

AGHS: AGCNTL high sensitivity adjustment on/off

Default value: 1 (on)

AGHT: AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs)

Default value: 0 (256ms)

∗

∗: preset

– 84 –

CXD2587Q

$38 (preset: $38 00 00)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

VCLM

VCLC

FLM FLC0

RFLM

RFLC AGF AGT

DFSW

LKSW TBLM TCLM

FLC1 TLC2 TLC1 TLC0

VCLM: VC level measurement (on/off) VCLC: VC level compensation for FCS In register (on/off) FLM: Focus zero level measurement (on/off) FLC0: Focus zero level compensation for FZC register (on/off) RFLM: RF zero level measurement (on/off) RFLC: RF zero level compensation (on/off) AGF: Focus auto gain adjustment (on/off) AGT: Tracking auto gain adjustment (on/off) DFSW: Defect disable switch (on/off)

Setting this switch to 1 (on) disables the defect countermeasure circuit.

LKSW: Lock switch (on/off)

Setting this switch to 1 (on) disables the sled free-running prevention circuit. TBLM: Traverse center measurement (on/off) TCLM: Tracking zero level measurement (on/off) FLC1: Focus zero level compensation for FCS In register (on/off) TLC2: Traverse center compensation (on/off) TLC1: Tracking zero level compensation (on/off) TLC0: VC level compensation for TRK/SLD In register (on/off)

Note) Commands marked with are accepted every 2.9ms. (when MCK = 128Fs)

All commands are on when set to 1.

– 85 –

CXD2587Q

SD6

1 0

0

1

0

Data RAM data for address = SD4 to SD0

Coefficient RAM data for address = SD5 to SD0

SD4

1

0

SD3 to SD0

1 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1

1 1 ∗ ∗ 1 0 ∗ ∗ 0 1 ∗ ∗ 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0

RF AVRG register RFDC input signal FBIAS register TRVSC register RFDC envelope (bottom) RFDC envelope (peak) RFDC envelope

(peak) – (bottom)

VC AVRG register FE AVRG register TE AVRG register FE input signal TE input signal SE input signal VC input signal

8 bits 8 bits 9 bits 9 bits 8 bits 8 bits 8 bits

9 bits 9 bits 9 bits 8 bits 8 bits 8 bits 8 bits

$399F $399E $399D $399C $3993 $3992 $3991

$398C $3988 $3984 $3983 $3982 $3981 $3980

8 bits

16 bits

SD5 Readout data Readout data length

Note) Coefficients K40 to K4F cannot be read out. ∗: Don't care

See the description for SRO1 of $3F concerning readout methods for the above data.

D15 D14 D13 D12 D11 D10 D9 D8

DAC

SD6

SD5 SD4 SD3 SD2 SD1 SD0

DAC: Serial data readout DAC mode (on/off) SD6 to SD0: Serial readout data select

$39

– 86 –

CXD2587Q

$3A (preset: $3A 00 00)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 FBON FBSS FBUP FBV1 FBV0 0 TJD0 FPS1 FPS0 TPS1 TPS0 0 SJHD INBK MTI0

FBON: FBIAS (focus bias) register addition (on/off)

The FBIAS register value is added to the signal loaded into the FCS In register by FBON = 1 (on).

FBSS: FBIAS (focus bias) register/counter switching

FBSS = 0: register, FBSS = 1: counter.

FBUP: FBIAS (focus bias) counter up/down operation switching

This performs counter up/down control when FBSS = 1. FBUP = 0: down counter, FBUP = 1: up counter.

FBV1, FBV0: FBIAS (focus bias) counter voltage switching

The number of FCS BIAS count-up/-down steps per cycle is decided by these bits.

TJD0: This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on

only when SFJP = 1 (during surf jump operation). FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block. TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block.

This is effective for increasing the overall gain in order to widen the servo band.

Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However,

6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the

relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00.

SJHD: This holds the tracking filter output at the value when surf jump starts during surf jump. INBK: When INBK = 0 (off), the brake circuit masks the tracking drive signal with TRKCNCL which is

generated by taking the MIRR signal at the TZC edge. When INBK = 1 (on), the tracking filter

input is masked instead of the drive output. MTI0: The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1 (on).

The counter changes once for each sampling cycle of the focus servo filter. When MCK is 128Fs, the sampling frequency is 88.2kHz. When converted to FE input, 1 step is approximately 1/2

9

× VDD × 0.4, VDD = supply voltage.

FBV1

0 0 1 1

0 1 0 1

1 2 4 8

FBV0 Number of steps per cycle

FPS1

0 0 1 1

FPS0

0 1 0 1

0dB

+6dB +12dB +18dB

Relative gain

TPS1

0 0 1 1

TPS0

0 1 0 1

0dB

+6dB +12dB +18dB

Relative gain

∗

∗: preset

∗

∗: preset

∗

– 87 –

CXD2587Q

$3B (preset: $3B E0 50)

SFOX, SFO2, SFO1: FOK slice level

Default value: 011 (28/256 × VDD × 0.57, VDD = supply voltage) RFDC input conversion

SFOX

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

16/256 × VDD × 0.57 20/256 × VDD × 0.57 24/256 × VDD × 0.57 28/256 × VDD × 0.57 32/256 × VDD × 0.57 40/256 × VDD × 0.57 48/256 × VDD × 0.57 50/256 × VDD × 0.57

SFO2

0 1 0 1 0 1 0 1

SFO1 Slice level

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SFO2 SFO1 SDF2 SDF1

MAX2 MAX1 SFOX BTF

D2V2 D2V1 D1V2 D1V1 RINT 0 0 0

∗: preset

∗

SDF2, SDF1: DFCT slice level

Default value: 10 (0.0313 × VDD × 1.14V) RFDC input conversion

SDF2

0 0 1 1

0 1 0 1

0.0156 × VDD × 1.14

0.0234 × VDD × 1.14

0.0313 × VDD × 1.14

0.0391 × VDD × 1.14

SDF1 Slice level

MAX2, MAX1: DFCT maximum time (MCK = 128Fs)

Default value: 00 (no timer limit)

MAX2

0 0 1 1

0 1 0 1

No timer limit

2.00ms

2.36

2.72

MAX1 DFCT maximum time

BTF: Bottom hold double-speed count-up mode for MIRR signal generation

On/off (default: off) On when set to 1.

∗: preset, VDD: supply voltage

∗

∗: preset

∗

– 88 –

CXD2587Q

D2V2, D2V1: Peak hold 2 for DFCT signal generation

Count-down speed setting Default value: 01 (0.086 × VDD × 1.14V/ms, 44.1kHz)

[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter.

D1V2, D1V1: Peak hold 1 for DFCT signal generation

Count-down speed setting Default value: 01 (0.688

× VDD

× 1.14V/ms, 352.8kHz)

[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the operating frequency of the internal counter.

RINT: This initializes the initial-state registers of the circuits which generate MIRR, DFCT and FOK.

D2V2

0 0 1 1

0 1 0 1

22.05

44.1

88.2

176.4

0.0431 × VDD × 1.14

0.0861 × VDD × 1.14

0.172 × VDD × 1.14

0.344 × VDD × 1.14

D2V1

Count-down speed [V/ms] [kHz]

∗: preset, VDD: supply voltage

∗

D2V2

0 0 1 1

0 1 0 1

176.4

352.8

705.6

1411.2

0.344 × VDD × 1.14

0.688 × VDD × 1.14

1.38 × VDD × 1.14

2.75 × VDD × 1.14

D2V1

Count-down speed [V/ms] [kHz]

∗

– 89 –

CXD2587Q

$3C (preset: $3C 00 80)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

COSS COTSCETZ CETF

COT2 COT1 MOT2 0

BTS1 BTS0 MRC1 MRC0 0 0 0 0

COSS, COTS: These select the TZC signal used when generating the COUT signal.

Preset = HPTZC.

STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs) DTZC is the delayed phase STZC. (The delay amount can be selected by D14 of $36.) HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz. See §4-13.

CETZ: The input from the TE pin normally enters the TRK filter and is used to generate the TZC

signal. However, the input from the CE pin can also be used. This function is for the center error servo. When CETZ = 0, the TZC signal is generated by using the TE input signal. When CETZ = 1, the TZC signal is generated by using the CE input signal.

CETF: When CETF = 0, the signal input to the TE pin is input to the TRK servo filter.

When CETF = 1, the signal input to the CE pin is input to the TRK servo filter.

These commands output the TZC signal. COT2, COT1: This outputs the TZC signal from the COUT pin.

COSS

1 0 0

—

0 1

STZC HPTZC DTZC

COTS TZC

∗: preset, —: don't care

∗

BTS1

0 0 1 1

0 1 0 1

1 2 4 8

BTS0 Number of count-up steps per cycle MRC1

0 0 1 1

0 1 0 1

5.669 ∗

11.338

22.675

45.351

MRC0 Setting time [µs]

∗: preset (when MCK = 128Fs)

∗

MOT2: The STZC signal is output from the MIRR pin by setting MOT2 to 1. These commands set the MIRR signal generation circuit.

BTS1, BTS0: This sets the count-up speed for the bottom hold value of the MIRR generation circuit.

The time per step is approximately 708 ns (when MCK = 128Fs). The preset value is BTS1 = 1, BTS0 = 0. However, this is valid only when BTF of $3B is 0.

MRC1, MRC0: This sets the minimum pulse width for masking the MIRR signal of the MIRR generation circuit.

As noted in §4-9, the MIRR signal is generated by comparing the waveform obtained by subtracting the bottom hold value from the peak hold value with the MIRR comparator level. Strictly speaking, however, for MIRR to become high, these levels must be compared continuously for a certain time. This sets that time. The preset value is MRC1 = 0, MRC0 = 0.

COT2

1 0 0

—

1 0

STZC HPTZC COUT

COT1 COUT pin output

∗: preset, —: don't care

∗

– 90 –

CXD2587Q

$3D (preset: $3D 00 00)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SFID SFSK THID THSK 0 TLD2 TLD1 TLD0 0 0 0 0 0 0 0 0

SFID: SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK

filter second-stage output. When the low-frequency component of the tracking error signal obtained from the RF amplifier is attenuated, the low frequency can be amplified and input to the SLD servo filter.

SFSK: Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally

the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M00 can be kept uniform by adjusting the K30 value even during the above switching.

THID: TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK

filter second-stage output. When signals other than the tracking error signal from the RF amplifier are input to the SE input pin, the signal transmitted from the TE pin can be obtained as TRK hold filter input.

THSK: Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally

the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up 2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted to M18 can be kept uniform by adjusting the K46 value even during the above switching.

∗

Please refer to §4-20. Filter Composition, for further information on SFID, SFSK, THID and THSK commands.

TLD0 to 2: SLD filter correction turns on and off independently of the TRK filter.

Please refer also to $38 (TLC0 to 2) and Figure 4-3.

TLC0

0

1

—

0 1

OFF

ON

OFF

ON ON

TLD0

VC level correction

TRK filter SLD filter

∗: preset, — : Don't care

∗

TLC1

0

1

—

0 1

OFF

ON

OFF

ON ON

TLD1

Tracking zero level correction

TRK filter SLD filter

∗

TLC2

0

1

—

0 1

OFF

ON

OFF

ON ON

TLD2

Traverse center correction

TRK filter SLD filter

∗

– 91 –

CXD2587Q

• Input coefficient inversion when SFID = 1 and THID = 1

The preset coefficients for the TRK filter are negative for input and positive for output. With this, the error input and servo that outputs reversed phase drive can be hypothesized.

TRK Filter

Negative input coefficient Positive output coefficient

TE

SLD Filter

Negative input coefficient Positive output coefficient

SE

TRK Hold Filter

Positive input coefficient Positive output coefficient

TRK Hold

When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so invert the SLD input coefficient (K00) code. For the same reason, when THID = 1, invert the TRK hold input coefficient (K40) code.

TRK Filter

Negative input coefficient Positive output coefficient

TE

SLD Filter

Positive input coefficient Positive output coefficient

SE

TRK Hold Filter

Negative input coefficient Positive output coefficient

TRK Hold

M0D

Please refer also to §4-20. Filter Composition.

– 92 –

CXD2587Q

$3E (preset: $3E 00 00)

F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage

On when set to 1; default = 0. F1NM: Gain normal F1DM: Gain down

T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage

On when set to 1; default = 0. T1NM: Gain normal T1UM: Gain up

F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage

On when set to 1; default = 0. Generally, the advance amount of the phase becomes large by partially setting the FCS servo third-stage filter which is used as the phase compensation filter to double accuracy. F3NM: Gain normal F3DM: Gain down

T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage

On when set to 1; default = 0. Generally, the advance amount of the phase becomes large by partially setting the TRK servo third-stage filter which is used as the phase compensation filter to double accuracy. T3NM: Gain normal T3UM: Gain up

Note) Filter first- and third-stage quasi double accuracy settings can be set individually.

See "Filter Composition" at the end of this specification concerning quasi double accuracy.

DFIS: FCS hold filter input extraction node selection

0: M05 (Data RAM address 05); default 1: M04 (Data RAM address 04)

TLCD: This command masks the TLC2 command set by D2 of $38 only when FOK is low.

On when set to 1; default = 0

LKIN: When 0, the internally generated LOCK signal is output to the LOCK pin. (default)

When 1, the LOCK signal can be input from an external source to the LOCK pin.

COIN: When 0, the internally generated COUT signal is output to the COUT pin. (default)

When 1, the COUT signal can be input from an external source to the COUT pin. The MIRR, DFCT and FOK signals can also be input from an external source.

MDFI: When 0, the MIRR, DFCT and FOK signals are generated internally. (default)

When 1, the MIRR, DFCT and FOK signals can be input from an external source through the MIRR, DFCT and FOK pins.

MIRI: When 0, the MIRR signal is generated internally. (default)

When 1, the MIRR signal can be input from an external source through the MIRR pin.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

F1NM F1DM F3NM F3DM

T1NM T1UM T3NM T3UM

DFIS TLCD 0 LKIN COIN MDFI MIRI XT1D

XT1D: The clock input from FSTI can be used without being frequency-divided as the master clock for

the servo block by setting D0 to 1. This command takes precedence over the XTSL pin, XT2D and XT4D. See the description of $3F for XT2D and XT4D.

MDFI

0 0 1

0 1

—

MIRR, DFCT and FOK are all generated internally. MIRR only is input from an external source. MIRR, DFCT and FOK are all input from an external source.

MIRI

∗

∗: preset, —: don't care

– 93 –

CXD2587Q

$3F (preset: $3F 00 00)

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

0 AGG4 XT4D XT2D 0 DRR2 DRR1 DRR0 0 ASFG FTQ LPAS SRO1 0

AGHF

ASOT

XT4D, XT2D: MCK (digital servo master clock) frequency division setting

This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is generated from the signal input to the FSTI pin. See the description of $3E for XT1D.

AGG4: This varies the amplitude of the internally generated sine wave using the AGGF and AGGT

commands during AGC. When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below.

AGGF (MSB)

0 0 1 1

0 1 0 1

1/64 × VDD × 0.4 [V] 1/32 × VDD × 0.4 1/16 × VDD × 0.4 1/8 × VDD × 0.4

AGGT (LSB) TE/FE input conversion

DRR2 to DRR0: Partially clears the Data RAM values (0 write).

The following values are cleared when set to 1 (on) respectively; default = 0 DRR2: M08, M09, M0A DRR1: M00, M01, M02 DRR0: M00, M01, M02 only when LOCK = low Note) Set DRR1 and DRR0 on for 50µs or more.

ASFG: When vibration detection is performed during anti-shock circuit operation, FCS servo filter is

forcibly set to gain normal status. On when set to 1; default = 0

LPAS: Built-in analog buffer low-current consumption mode

This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE input analog buffers by using a single operational amplifier. On when set to 1; default = 0 Note) When using this mode, first check whether each error signal is properly A/D converted

using the SRO1 and SRO0 commands of $3F.

SRO1: These commands are used to output various data externally continuously which have been

specified with the $39 command. (However, D15 (DAC) of $39 must be set to 1.) Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting these commands to 1 respectively. The default is 0, 0. (no readout)

The output pins for each case are shown below.

SOCK XOLT SOUT

LMUT pin WFCK pin RMUT pin

SRO1 = 1

(See "Description of Data Readout" on the following page.)

AGHF: This halves the frequency of the internally generated sine wave during AGC. FTQ: The slope of the output during focus search is a quarter of the conventional output slope. ASOT: The anti-shock signal, which is internally detected, is output from the ATSK pin.

Output when set to 1; default=0 Vibration detection when a high signal is output for the anti-shock signal output.

These settings are the same for both focus auto gain control and tracking auto gain control.

∗: preset, —: don't care

∗

XT1D

0 1 0 0

XT2D

0

—

1 0

XT4D

0 — —

1

According to XTSL

1/1 1/2 1/4

Frequency division ratio

∗

∗: preset

– 94 –

CXD2587Q

Description of Data Readout

SOCK

(5.6448MHz)

XOLT

(88.2kHz)

SOUT

MSB LSB· · · MSB LSB· · ·

· · ·· · ·· · ·· · ·

16-bit register for

serial/parallel

conversion

16-bit register

for latch

SOUT

SOCK

XOLT

CLK CLK

MSB

LSB

•

To the 7-segment LED

Data is connected to the 7-segment LED by 4-bits at a time. This enables Hex display using four 7-segment LEDs.

MSB

LSB

SOUT

SOCK

XOLT

Serial data input

Clock input

Latch enable input

Analog output

D/A

To an oscilloscope, etc.

Offset adjustment, gain adjustment

Waveforms can be monitored with an oscilloscope using a serial input-type D/A converter as shown above.

– 95 –

CXD2587Q

§4-19. List of Servo Filter Coefficients

∗

Fix indicates that normal preset values should be used.

ADDRESS

K00 K01 K02 K03 K04 K05 K06 K07 K08

K09 K0A K0B K0C K0D K0E K0F

E0 81 23 7F 6A 10 14 30 7F 46 81

1C

7F 58 82 7F

SLED INPUT GAIN SLED LOW BOOST FILTER A-H SLED LOW BOOST FILTER A-L SLED LOW BOOST FILTER B-H SLED LOW BOOST FILTER B-L SLED OUTPUT GAIN FOCUS INPUT GAIN SLED AUTO GAIN FOCUS HIGH CUT FILTER A FOCUS HIGH CUT FILTER B FOCUS LOW BOOST FILTER A-H FOCUS LOW BOOST FILTER A-L FOCUS LOW BOOST FILTER B-H FOCUS LOW BOOST FILTER B-L FOCUS PHASE COMPENSATE FILTER A FOCUS DEFECT HOLD GAIN

K10

K11

K12

K13

K14

K15

K16

K17

K18

K19 K1A K1B K1C K1D K1E K1F

K20

K21

K22

K23

K24

K25

K26

K27

K28

K29 K2A K2B K2C K2D K2E K2F

4E 32 20 30 80 77 80 77 00 F1 7F 3B 81 44 7F 5E

FOCUS PHASE COMPENSATE FILTER B FOCUS OUTPUT GAIN ANTI SHOCK INPUT GAIN FOCUS AUTO GAIN HPTZC / Auto Gain HIGH PASS FILTER A HPTZC / Auto Gain HIGH PASS FILTER B ANTI SHOCK HIGH PASS FILTER A HPTZC / Auto Gain LOW PASS FILTER B Fix

∗

TRACKING INPUT GAIN TRACKING HIGH CUT FILTER A TRACKING HIGH CUT FILTER B TRACKING LOW BOOST FILTER A-H TRACKING LOW BOOST FILTER A-L TRACKING LOW BOOST FILTER B-H TRACKING LOW BOOST FILTER B-L

82 44 18 30 7F 46 81 3A 7F 66 82 44 4E 1B 00 00

TRACKING PHASE COMPENSATE FILTER A TRACKING PHASE COMPENSATE FILTER B TRACKING OUTPUT GAIN TRACKING AUTO GAIN FOCUS GAIN DOWN HIGH CUT FILTER A FOCUS GAIN DOWN HIGH CUT FILTER B FOCUS GAIN DOWN LOW BOOST FILTER A-H FOCUS GAIN DOWN LOW BOOST FILTER A-L FOCUS GAIN DOWN LOW BOOST FILTER B-H FOCUS GAIN DOWN LOW BOOST FILTER B-L FOCUS GAIN DOWN PHASE COMPENSATE FILTER A FOCUS GAIN DOWN DEFECT HOLD GAIN FOCUS GAIN DOWN PHASE COMPENSATE FILTER B FOCUS GAIN DOWN OUTPUT GAIN NOT USED NOT USED

DATA CONTENTS

– 96 –

CXD2587Q

ADDRESS

K30 K31 K32 K33 K34 K35 K36 K37 K38

K39 K3A K3B K3C K3D K3E K3F

80 66 00 7F 6E 20 7F 3B 80 44 7F 77 86

0D

57 00

SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.) ANTI SHOCK LOW PASS FILTER B NOT USED ANTI SHOCK HIGH PASS FILTER B-H ANTI SHOCK HIGH PASS FILTER B-L ANTI SHOCK FILTER COMPARATE GAIN TRACKING GAIN UP2 HIGH CUT FILTER A TRACKING GAIN UP2 HIGH CUT FILTER B TRACKING GAIN UP2 LOW BOOST FILTER A-H TRACKING GAIN UP2 LOW BOOST FILTER A-L TRACKING GAIN UP2 LOW BOOST FILTER B-H TRACKING GAIN UP2 LOW BOOST FILTER B-L TRACKING GAIN UP PHASE COMPENSATE FILTER A TRACKING GAIN UP PHASE COMPENSATE FILTER B TRACKING GAIN UP OUTPUT GAIN NOT USED

K40

K41

K42

K43

K44

K45

K46

K47

K48

K49 K4A K4B K4C K4D K4E K4F

04 7F 7F 79 17

6D

00 00 02 7F 7F 79 17 54 00 00

TRACKING HOLD FILTER INPUT GAIN TRACKING HOLD FILTER A-H TRACKING HOLD FILTER A-L TRACKING HOLD FILTER B-H TRACKING HOLD FILTER B-L TRACKING HOLD FILTER OUTPUT GAIN TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is accessed with THSK = 1.) NOT USED FOCUS HOLD FILTER INPUT GAIN FOCUS HOLD FILTER A-H FOCUS HOLD FILTER A-L FOCUS HOLD FILTER B-H FOCUS HOLD FILTER B-L FOCUS HOLD FILTER OUTPUT GAIN NOT USED NOT USED

DATA CONTENTS

– 97 –

CXD2587Q

§4-20. Filter Composition

The internal filter composition is shown below. K∗∗ and M∗∗ indicate coefficient RAM and Data RAM address values respectively.

FCS Servo Gain Normal fs = 88.2kHz

K0D

K0C K0E K10

Z

–1

K0B

Z

–1

K09 K0AK08

Z

–1

M04M03

2

–7

2

–7

M05 M06

Z

–1

K11 K13

K0F

FCS

Hold Reg 1

FCS

AUTO Gain

FCS PWM

2

7

FCS SRCH

M07

2

–1

K06

AGFON

K06

DFCT

FCS

Hold Reg 2

FCS

In Reg

Sin ROM

FCS Servo Gain Down fs = 88.2kHz

Z

–1

Z

–1

Z

–1

M04M03

2

–7

2

–7

M05 M06

Z

–1

2

7

M07

2

–1

DFCT

K29

K28 K2A K2C

K27

K25 K26K24

K2D K13

K2B

FCS

Hold Reg 1

FCS

AUTO Gain

FCS PWM

FCS SRCH

K06

FCS

Hold Reg 2

FCS

In Reg

Note) Set the MSB bit of the K0B and K0D coefficients to 0.

Note) Set the MSB bit of the K27 and K29 coefficients to 0.

– 98 –

CXD2587Q

TRK Servo Gain Normal fs = 88.2kHz

K1F

K1E K20 K21

Z

–1

K1D

Z

–1

K1B K1CK1A

Z

–1

M0CM0B

2

–7

2

–7

M0D M0E

Z

–1

K22 K23

TRK

AUTO Gain

TRK PWM

2

7

TRK JMP

M0F

2

–1

K19

AGTON

K19

DFCT

TRK

Hold Reg

TRK

In Reg

Sin ROM

To SLD Servo, TRK Hold

Note) Set the MSB bit of the K1D and K1F coefficients to 0.

TRK Servo Gain Up 1 fs = 88.2kHz

K3D

Z

–1

Z

–1

K1B K3CK1A

Z

–1

M0CM0B M0E

K3E K23

TRK

AUTO Gain

TRK PWM

2

7

TRK JMP

M0F

2

–1

K19

DFCT

TRK

Hold Reg

TRK

In Reg

– 99 –

CXD2587Q

TRK Servo Gain Up 2 fs = 88.2kHz

K3B

K3A K3C K3D

Z

–1

K39

Z

–1

K37 K38K36

Z

–1

M0CM0B

2

–7

2

–7

M0D

M0E

Z

–1

K3E K23

TRK

AUTO Gain

TRK PWM

2

7

TRK JMP

M0F

2

–1

K19

DFCT

TRK

Hold Reg

TRK

In Reg

To SLD Servo, TRK Hold

Note) Set the MSB bit of the K39 and K3B coefficients to 0.

SLD Servo fs = 345Hz

K04

K03

Z

–1

K02

Z

–1

K01

K00

M00

2

–7

2

–7

M01

K05 K07

TRK

AUTO Gain

SLD PWM

2

–7

SLD MOV

M02

SLD

In Reg

2

–1

K30

SFSK (only when TGUP2 is used)

SFID

M0D

TRK SERVO FILTER second-stage output

Note) Set the MSB bit of the K02 and K04 coefficients to 0.

HPTZC/Auto Gain fs = 88.2kHz

K15 K17

Z

–1

K14

M08 M09 M0A

Z

–1

AUTO Gain

Reg

2

–1

AGTON AGFON

AGFON

FCS

In Reg

TRK

In Reg

Sin ROM

Z

–1

Slice

TZC RegSlice

2

–1

– 100 –

CXD2587Q

Anti Shock fs = 88.2kHz

K34

K33

Z

–1

Z

–1

K31 K16

Z

–1

M09M08

2

–7

M0A

K35

Comp

K12

Anti Shock

Reg

2

–1

TRK

In Reg

Note) Set the MSB bit of the K34 coefficient to 0.

The comparator input is 1/16 the maximum amplitude of the comparator input.

AVRG fs = 88.2kHz

M08

AVRG Reg

2

–1

VC, TE, FE,

RFDC

Z

–1

2

–7

TRK Hold fs = 345Hz

K44

K43

Z

–1

K42

Z

–1

K41

K40

M18

2

–7

2

–7

M19

K45

TRK

Hold Reg

SLD

In Reg

2

–1

K46

THSK (only when TGUP2 is used)

THID

M0D

TRK SERVO FILTER second-stage output

Note) Set the MSB bit of the K42 and K44 coefficients to 0.

FCS Hold fs = 345Hz

K4C

K4B

Z

–1

K4A

Z

–1

K49

K48

M10

2

–7

2

–7

M11

K4D

FCS

Hold Reg 1

FCS

Hold Reg 2

Note) Set the MSB bit of the K4A and K4C coefficients to 0.