MOTOROLA SN74LS194ADR2, SN74LS194AN, SN74LS194AD Datasheet
Semiconductor Components Industries, LLC, 1999
December, 1999 – Rev. 6
1 Publication Order Number:
SN74LS194A/D
SN74LS194A
4-Bit Bidirectional
Universal Shift Register
The SN74LS194A is a High Speed 4-Bit Bidirectional Universal
Shift Register. As a high speed multifunctional sequential building
block, it is useful in a wide variety of applications. It may be used in
serial-serial, shift left, shift right, serial-parallel, parallel-serial, and
parallel-parallel data register transfers. The LS194A is similar in
operation to the LS195A Universal Shift Register, with added features
of shift left without external connections and hold (do nothing) modes
of operation. It utilizes the Schottky diode clamped process to achieve
high speeds and is fully compatible with all ON Semiconductor TTL
families.
• Typical Shift Frequency of 36 MHz
• Asynchronous Master Reset
• Hold (Do Nothing) Mode
• Fully Synchronous Serial or Parallel Data Transfers
• Input Clamp Diodes Limit High Speed Termination Effects
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 4.75 5.0 5.25 V
T
A
Operating Ambient
T emperature Range
0 25 70 °C
I
OH
Output Current – High –0.4 mA
I
OL
Output Current – Low 8.0 mA
LOW
POWER
SCHOTTKY
Device Package Shipping
ORDERING INFORMATION
SN74LS194AN 16 Pin DIP 2000 Units/Box
SN74LS194AD 16 Pin
SOIC
D SUFFIX
CASE 751B
http://onsemi.com
2500/Tape & Reel
PLASTIC
N SUFFIX
CASE 648
16
1
16
1
SN74LS194A
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2
CONNECTION DIAGRAM DIP (TOP VIEW)
Mode Control Inputs
Parallel Data Inputs
Serial (Shift Right) Data Input
Serial (Shift Left) Data Input
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Parallel Outputs
S
0
, S
1
P0 – P
3
D
SR
D
SL
CP
MR
Q0 – Q
3
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
HIGH LOW
(Note a)LOADING
PIN NAMES
14 13 12 11 10 9
123456
7
16 15
8
V
CC
MR
Q0Q1Q2Q
3
S
1
CP S
0
DSRP0P1P2P3DSLGND
SN74LS194A
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3
LOGIC DIAGRAM
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
S
1
S
0
D
SR
D
SL
CP
MR
Q
0
Q
1
Q
2
Q
3
P
0
P
1
P
2
P
3
14
1
2
6
7
3
4
5
9
11
12
10
1315
SQ
0
CP
R
CLEAR
SQ
1
CP
R
CLEAR
SQ
2
CP
R
CLEAR
SQ
3
CP
R
CLEAR
FUNCTIONAL DESCRIPTION
The Logic Diagram and Truth Table indicate the
functional characteristics of the LS194A 4-Bit Bidirectional
Shift Register. The LS194A is similar in operation to the
ON Semiconductor LS195A Universal Shift Register when
used in serial or parallel data register transfers. Some of the
common features of the two devices are described below:
All data and mode control inputs are edge-triggered,
responding only to the LOW to HIGH transition of the Clock
(CP). The only timing restriction, therefore, is that the mode
control and selected data inputs must be stable one set-up
time prior to the positive transition of the clock pulse.
The register is fully synchronous, with all operations
taking place in less than 15 ns (typical) making the device
especially useful for implementing very high speed CPUs,
or the memory buffer registers.
The four parallel data inputs (P
0
, P1, P2, P3) are D-type
inputs. When both S
0
and S1 are HIGH, the data appearing
on P0, P1, P2, and P3 inputs is transferred to the Q0, Q1, Q2,
and Q3 outputs respectively following the next LOW to
HIGH transition of the clock.
The asynchronous Master Reset (MR), when LOW,
overrides all other input conditions and forces the Q outputs
LOW .
Special logic features of the LS194A design which
increase the range of application are described below:
Two mode control inputs (S
0
, S1) determine the
synchronous operation of the device. As shown in the Mode
Selection T able, data can be entered and shifted from left to
right (shift right, Q
0
!
Q1, etc.) or right to left (shift left, Q
3
!
Q2, etc.), or parallel data can be entered loading all four
bits of the register simultaneously. When both S0 and S1,are
LOW, the existing data is retained in a “do nothing” mode
without restricting the HIGH to LOW clock transition.
D-type serial data inputs (D
SR
, DSL) are provided on both
the first and last stages to allow multistage shift right or shift
left data transfers without interfering with parallel load
operation.
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