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SEMICONDUCTOR TECHNICAL DATA
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The MC74VHCT132A is an advanced high speed CMOS Schmitt NAND
trigger fabricated with silicon gate CMOS technology . It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
Pin configuration and function are the same as the MC74VHC00, but the
inputs have hysteresis and, with its Schmitt trigger function, the VHCT132A
can be used as a line receiver which will receive slow input signals.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V , because it has full 5V CMOS
level output swings.
The VHCT132A input structures provide protection when voltages
between 0V and 5.5V are applied, regardless of the supply voltage. The
output structures also provide protection when VCC = 0V. These input and
output structures help prevent device destruction caused by supply voltage
– input/output voltage mismatch, battery backup, hot insertion, etc.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: tPD = 4.9ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C
• TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 72 FETs or 18 Equivalent Gates
= 0.8V (Max)
OLP
Pinout: 14–Lead Packages (Top View)
VCCB4 A4 Y4
1314 12 11 10 9 8
B3 A3 Y3
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
14–LEAD TSSOP PACKAGE
14–LEAD SOIC EIAJ PACKAGE
MC74VHCTXXAD
MC74VHCTXXADT
MC74VHCTXXAM
DT SUFFIX
CASE 948G–01
M SUFFIX
CASE 965–01
ORDERING INFORMATION
SOIC
TSSOP
SOIC EIAJ
FUNCTION TABLE
Inputs Output
ABY
LLH
LHH
HLH
HHL
4/99
Motorola, Inc. 1999
21 34567
A1 B1 Y1 A2 B2 Y2 GND
1
A1
2
B1
4
A2
5
B2
1
LOGIC DIAGRAM
3
Y1
6
Y2
A3
B3
A4
B4
9
10
12
13
REV 0
8
Y3
11
Y4
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MC74VHCT132A
MAXIMUM RATINGS*
Symbol
V
V
I
I
I
Î
T
DC Supply Voltage
CC
V
DC Input Voltage
in
DC Output Voltage
out
I
Input Diode Current
IK
Output Diode Current
OK
DC Output Current, per Pin
out
DC Supply Current, VCC and GND Pins
CC
P
Power Dissipation in Still Air, SOIC Packages†
D
ОООООООООООО
Storage Temperature
stg
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
V
V
T
DC Supply Voltage
CC
DC Input Voltage
in
DC Output Voltage
out
Operating Temperature, All Package Types
A
DC ELECTRICAL CHARACTERISTICS
Symbol
V
T+
Î
V
T–
Î
V
H
Î
V
OH
Î
Î
Î
Î
V
OL
Î
Positive Threshold Voltage
ОООООО
Negative Threshold Voltage
ОООООО
Hysteresis Voltage
ОООООО
Minimum High–Level
ОООООО
Output Voltage
IOH = –50µA
ОООООО
ОООООО
ОООООО
Maximum Low–Level
Output Voltage
ОООООО
Parameter
Parameter
Parameter
– 0.5 to + 7.0
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
TSSOP Package†
ÎÎÎÎ
– 65 to + 150
V
Test Conditions
V
3.0
ОООООÎÎ
4.5
5.5
3.0
ОООООÎÎ
4.5
6.0
3.0
ОООООÎÎ
4.5
5.5
VIN = VIH or V
ООООО
IOH = – 50µA
ООООО
ООООО
IOH = – 4mA
IOH = – 8mA
ООООО
VIN = VIH or V
IOL = 50µA
ООООО
IL
IL
2.0
Î
3.0
4.5
Î
Î
4.5
5.5
Î
2.0
3.0
Î
4.5
Value
– 20
± 20
± 25
± 50
500
450
Min
Max
4.5
5.5
0
5.5
0
V
CC
– 40
+ 85
TA = 25°C
Min
Typ
ÎÎÎÎÎ
0.35
0.5
Î
ÎÎÎÎÎ
0.6
0.30
0.40
Î
ÎÎÎ
0.50
1.9
2.9
4.4
2.0
Î
3.0
4.5
Î
Î
Î
Î
Î
Î
2.58
3.94
Î
0.0
0.0
ÎÎÎ
0.0
Unit
V
V
V
mA
mA
mA
mA
mW
Î
_
C
Unit
V
V
V
_
C
Max
1.7
2.0
2.0
1.20
1.40
1.60
Î
Î
Î
Î
0.1
0.1
Î
0.1
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
should be constrained to the
out
range GND v (Vin or V
Unused inputs must always be
) v VCC.
out
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
TA ≤ 85°C
Min
Max
1.6
ÎÎÎ
2.0
2.0
0.35
0.5
ÎÎÎ
0.6
0.30
1.20
0.40
1.40
Î
0.50
Î
1.60
1.9
Î
Î
Î
2.48
3.80
Î
2.9
4.4
Î
Î
Î
Î
0.1
0.1
ÎÎÎ
0.1
TA ≤ 125°C
Min
Max
1.6
ÎÎÎ
2.0
2.0
0.35
0.5
0.6
0.30
0.40
Î
0.50
ÎÎÎ
1.20
1.40
Î
1.60
1.9
Î
2.9
4.4
Î
Î
2.34
3.66
Î
Î
Î
Î
Î
0.1
0.1
ÎÎÎ
0.1
Unit
V
Î
V
V
Î
V
Î
Î
Î
Î
V
Î
ÎÎООООООÎООООО
I
Maximum Input Leakage
IN
Current
I
Î
I
CCT
I
OPD
Maximum Quiescent Supply
CC
ОООООО
Current
Quiescent Supply Current
Output Leakage Current
IOL = 4mA
IOL = 8mA
VIN = 5.5V or GND
VIN = VCC or GND
ООООО
Input: VIN = 3.4V
V
= 5.5V
OUT
MOTOROLA VHC Data – Advanced CMOS Logic
4.5
Î
5.5
0 to 5.5
5.5
Î
5.5
0.0
2
ÎÎÎÎÎ
0.36
0.36
± 0.1
ÎÎÎÎÎ
2.0
1.35
0.5
0.44
ÎÎÎ
0.44
± 1.0
ÎÎÎ
20
1.50
5.0
0.52
ÎÎÎ
0.52
± 1.0
ÎÎÎ
40εA
1.65
10
DL203 — Rev 0
Î
µA
mA
µA
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MC74VHCT132A
AC ELECTRICAL CHARACTERISTICS (Input t
= tf = 3.0ns)
r
TA = – 40 to
ÎÎООООООÎОООООООÎООООО
Symbol
t
,
PLH
t
Î
ÎÎООООООÎООООООО
Î
Maximum Propagation
Delay, A or B to Y
PHL
ОООООО
C
Maximum Input
in
ОООООО
Capacitance
Parameter
Test Conditions
VCC = 3.3 ± 0.3 V CL = 15pF
ООООООО
CL = 50pF
VCC = 5.0 ± 0.5 V CL = 15pF
CL = 50pF
ОООООООÎÎÎÎ
TA = 25°C
Min
Typ
7.6
ÎÎÎ
ÎÎÎ
10.1
4.9
6.4
4
Max
11.9
15.4
Î
7.7
Î
9.7
10
Î
85°C
ÎÎÎ
Min
Max
1.0
14.0
1.0
17.5
Î
Î
1.0
1.0
Î
9.0
Î
11.0
10
ÎÎÎ
ÎÎÎ
TA ≤ 125°C
Min
Max
16.5
20.0
ÎÎÎ
11.0
ÎÎÎ
13.0
10ÎpF
ÎÎÎ
Î
Unit
ns
Î
Î
Typical @ 25°C, VCC = 5.0 V
C
Power Dissipation Capacitance (Note 1.)
PD
16
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
dynamic power consumption; PD = CPD V
NOISE CHARACTERISTICS (Input t
= tf = 3.0ns, CL = 50pF, VCC = 5.0 V)
r
2
fin + ICC VCC.
CC
CC(OPR
= CPD VCC fin + ICC/4 (per gate). CPD is used to determine the no–load
)
TA = 25°C
Symbol Characteristic
V
V
V
V
OLP
OLV
IHD
ILD
Quiet Output Maximum Dynamic V
Quiet Output Minimum Dynamic V
OL
OL
Minimum High Level Dynamic Input Voltage 3.5 V
Maximum Low Level Dynamic Input Voltage 1.5 V
Typ Max
0.3 0.8 V
– 0.3 – 0.8 V
Unit
VHC Data – Advanced CMOS Logic
DL203 — Rev 0
3 MOTOROLA