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SEMICONDUCTOR TECHNICAL DATA
Order this document
by MC74VHC4066/D
1
REV 3
Motorola, Inc. 1999
07/99
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High–Performance Silicon–Gate CMOS
The MC74VHC4066 utilizes silicon–gate CMOS technology to
achieve fast propagation delays, low ON resistances, and low OFF–
channel leakage current. This bilateral switch/multiplexer/demultiplexer
controls analog and digital voltages that may vary across the full
power–supply range (from VCC to GND).
The VHC4066 is identical in pinout to the metal–gate CMOS MC14066
and the high–speed CMOS HC4066A. Each device has four independent
switches. The device has been designed so that the ON resistances
(RON) are much more linear over input voltage than RON of metal–gate
CMOS analog switches.
The ON/OFF control inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL outputs.
For analog switches with voltage–level translators, see the VHC4316.
• Fast Switching and Propagation Speeds
• High ON/OFF Output Voltage Ratio
• Low Crosstalk Between Switches
• Diode Protection on All Inputs/Outputs
• Wide Power–Supply Voltage Range (VCC – GND) = 2.0 to 12.0 Volts
• Analog Input Voltage Range (VCC – GND) = 2.0 to 12.0 Volts
• Improved Linearity and Lower ON Resistance over Input Voltage than
the MC14016 or MC14066
• Low Noise
• Chip Complexity: 44 FETs or 11 Equivalent Gates
LOGIC DIAGRAM
X
A
Y
A
12
A ON/OFF CONTROL
13
X
B
Y
B
43
B ON/OFF CONTROL
5
X
C
Y
C
89
C ON/OFF CONTROL
6
X
D
Y
D
11 10
D ON/OFF CONTROL
12
ANALOG
OUTPUTS/INPUTS
ANALOG INPUTS/OUTPUTS = XA, XB, XC, X
D
PIN 14 = V
CC
PIN 7 = GND
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
FUNCTION TABLE
PIN ASSIGNMENT
11
12
13
14
8
9
105
4
3
2
1
7
6
Y
D
X
D
D ON/OFF
CONTROL
A ON/OFF
CONTROL
V
CC
X
C
Y
C
X
B
Y
B
Y
A
X
A
GND
C ON/OFF
CONTROL
B ON/OFF
CONTROL
On/Off Control State of
Input Analog Switch
LOff
HOn
ORDERING INFORMATION
MC74VHCXXXXD
MC74VHCXXXXDT
SOIC
TSSOP
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
DT SUFFIX
14–LEAD TSSOP PACKAGE
CASE 948G–01
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MC74VHC4066
MOTOROLA VHC Data – Advanced CMOS Logic
DL203 — Rev 2
2
Positive DC Supply Voltage (Referenced to GND)
Analog Input Voltage (Referenced to GND)
Digital Input Voltage (Referenced to GND)
DC Current Into or Out of Any Pin
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
Lead Temperature, 1 mm from Case for 10 Seconds
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Positive DC Supply Voltage (Referenced to GND)
Analog Input Voltage (Referenced to GND)
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature, All Package Types
Input Rise and Fall Time, ON/OFF Control
Inputs (Figure 10) VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 9.0 V
VCC = 12.0 V
ns
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)
Minimum High–Level Voltage
ON/OFF Control Inputs
Maximum Low–Level Voltage
ON/OFF Control Inputs
Maximum Input Leakage Current
ON/OFF Control Inputs
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
VIO = 0 V
µA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
I/O pins must be connected to a
properly terminated line or bus.
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MC74VHC4066
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
3 MOTOROLA
DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)
Vin = V
IH
VIS = VCC to GND
IS v 2.0 mA (Figures 1, 2)
Vin = V
IH
VIS = VCC or GND (Endpoints)
IS v 2.0 mA (Figures 1, 2)
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Vin = V
IH
VIS = 1/2 (VCC – GND)
IS v 2.0 mA
Maximum Off–Channel Leakage
Current, Any One Channel
Vin = V
IL
VIO = VCC or GND
Switch Off (Figure 3)
Maximum On–Channel Leakage
Current, Any One Channel
Vin = V
IH
VIS = VCC or GND
(Figure 4)
µA
†At supply voltage (VCC) approaching 3 V the analog switch–on resistance becomes extremely non–linear. Therefore, for low–voltage
operation, it is recommended that these devices only be used to control digital signals.
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)
Maximum Propagation Delay , Analog Input to Analog Output
(Figures 8 and 9)
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 10 and 11)
Maximum Propagation Delay, ON/OFF Control to Analog Output
(Figures 10 and 1 1)
Maximum Capacitance ON/OFF Control Input
Control Input = GND
Analog I/O
Feedthrough
Typical @ 25°C, VCC = 5.0 V
C
PD
Power Dissipation Capacitance (Per Switch) (Figure 13)*
15
pF
*Used to determine the no–load dynamic power consumption: PD = CPD V
CC
2
f + ICC VCC.
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MC74VHC4066
MOTOROLA VHC Data – Advanced CMOS Logic
DL203 — Rev 2
4
ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)
Maximum On–Channel Bandwidth or
Minimum Frequency Response
(Figure 5)
fin = 1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at V
OS
Increase fin Frequency Until dB Meter Reads – 3 dB
RL = 50 Ω, CL = 10 pF
Off–Channel Feedthrough Isolation
(Figure 6)
fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at V
IS
fin = 10 kHz, RL = 600 Ω, CL = 50 pF
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF
Feedthrough Noise, Control to
Switch
(Figure 7)
Vin v 1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
RL = 600 Ω, CL = 50 pF
Crosstalk Between Any Two Switches
(Figure 12)
fin Sine Wave
Adjust fin Voltage to Obtain 0 dBm at V
IS
fin = 10 kHz, RL = 600 Ω, CL = 50 pF
fin = 1.0 MHz, RL = 50 Ω, CL = 10 pF
Total Harmonic Distortion
(Figure 14)
fin = 1 kHz, RL = 10 kΩ, CL = 50 pF
THD = THD
Measured
– THD
Source
VIS = 4.0 VPP sine wave
VIS = 8.0 VPP sine wave
VIS = 11.0 VPP sine wave
%
*Guaranteed limits not tested. Determined by design and verified by qualification.