FEATURES
■AD7572 Pinout
■12-Bit Resolution
■3μs and 8μs Conversion Times
■On-Chip Sample-and-Hold
■Up to 250kHz Sample Rates
■5V Single Supply Operation
■No Negative Supply Required
■On-Chip 25ppm/°C Reference
■75mW (Typ) Power Consumption
■24-Pin Narrow DIP and SOL Packages
■ESD Protected on All Pins
APPLICATIOUS
■High Speed Data Acquisition
■Digital Signal Processing (DSP)
■Multiplexed Data Acquisition Systems
■Single Supply Systems
LTC1272
12-Bit, 3μs, 250kHz Sampling A/D Converter
DESCRIPTIOU
The LTC1272 is a 3μs, 12-bit, successive approximation sampling A/D converter. It has the same pinout as the industry standard AD7572 and offers faster conversion time, on-chip sample-and-hold, and single supply operation. It uses LTBiCMOSTM switched-capacitor technology to combine a high speed 12-bit ADC with a fast, accurate sample-and-hold and a precision reference.
The LTC1272 operates with a single 5V supply but can also accept the 5V/–15V supplies required by the AD7572 (Pin
23, the negative supply pin of the AD7572, is not connected on the LTC1272). The LTC1272 has the same 0V to 5V input range as the AD7572 but, to achieve single supply operation, it provides a 2.42V reference output instead of the
– 5.25V of the AD7572. It plugs in for the AD7572 if the reference capacitor polarity is reversed and a 1μs sample- and-hold acquisition time is allowed between conversions.
The output data can be read as a 12-bit word or as two 8-bit bytes. This allows easy interface to both 8-bit and higher processors. The LTC1272 can be used with a crystal or an external clock and comes in speed grades of 3μs and 8μs.
LTBiCMOS is a trademark of Linear Technology Corporation
TYPICAL APPLICATIOU
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Single 5V Supply, 3μs, 12-Bit Sampling ADC |
5V |
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1024 Point FFT, fS = 250kHz, fIN = 10kHz |
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LTC1272 |
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0 |
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ANALOG INPUT |
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A IN |
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VDD |
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2.42V |
(0V TO 5V) |
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+ |
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–20 |
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VREF |
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NC |
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S |
= 72.1 |
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VREF |
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10 |
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(N+D) |
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OUTPUT |
10μF |
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0.1 |
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0.1μF |
AGND |
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BUSY |
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(dB) |
–40 |
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D11 (MSB) |
CS |
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–60 |
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AMPLITUDE |
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D10 |
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CONTROL |
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D9 |
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HBEN |
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LINES |
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–80 |
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D8 |
CLK OUT |
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–100 |
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D7 |
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CLK IN |
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8 OR 12-BIT |
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D6 |
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D0/8 |
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–120 |
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PARALLEL |
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D5 |
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D1/9 |
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–140 |
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BUS |
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20 |
40 |
60 |
80 |
100 |
120 |
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0 |
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D4 |
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D2/10 |
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FREQUENCY (kHz) |
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DGND |
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D3/11 |
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LTC1272 • TA02 |
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LTC1272 • TA01 |
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1
LTC1272
ABSOLUTE WAXIWUW RATIUGS
(Notes 1 and 2)
Supply Voltage (VDD) ................................................. |
6V |
Analog Input Voltage (Note 3) ................... |
– 0.3V to 15V |
Digital Input Voltage .................................. |
– 0.3V to 12V |
Digital Output Voltage .................... |
– 0.3V to VDD + 0.3V |
Power Dissipation .............................................. |
500mW |
Operating Temperature Range |
0°C to 70°C |
LTC1272-XAC, CC ................................. |
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Storage Temperature Range ................. |
– 65°C to 150°C |
Lead Temperature (Soldering, 10 sec).................. |
300°C |
PACKAGE/ORDER IUFORWATIOU
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TOP VIEW |
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TOP VIEW |
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A IN |
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VDD |
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1 |
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A IN |
1 |
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24 |
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VDD |
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NC |
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VREF |
2 |
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23 |
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VREF |
2 |
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23 |
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NC |
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AGND |
3 |
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BUSY |
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AGND |
3 |
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22 |
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BUSY |
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(MSB) D11 |
4 |
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21 |
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CS |
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(MSB) D11 |
4 |
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21 |
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CS |
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D10 |
5 |
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20 |
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RD |
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D10 |
5 |
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RD |
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D9 |
6 |
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HBEN |
D9 |
6 |
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19 |
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HBEN |
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D8 |
7 |
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CLK OUT |
D8 |
7 |
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18 |
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CLK OUT |
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D7 |
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CLK IN |
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8 |
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D7 |
8 |
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17 |
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CLK IN |
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D6 |
9 |
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D0/8 |
D6 |
9 |
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16 |
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D0/8 |
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D5 |
10 |
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D1/9 |
D5 |
10 |
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15 |
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D1/9 |
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D4 |
11 |
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D2/10 |
D4 |
11 |
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D2/10 |
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DGND |
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D3/11 |
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12 |
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DGND |
12 |
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13 |
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D3/11 |
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N PACKAGE |
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S PACKAGE |
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24-LEAD PLASTIC DIP |
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24-LEAD PLASTIC SOL |
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TJMAX = 110°C, θJA = 100°C/W |
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TJMAX = 110°C, θJA = 130°C/W |
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ORDER PART NUMBER
CONVERSION |
CONVERSION |
TIME = 3μs |
TIME = 8μs |
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LTC1272-3ACN |
LTC1272-8ACN |
LTC1272-3CCN |
LTC1272-8CCN |
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S PACKAGE ONLY
LTC1272-3ACS LTC1272-8ACS LTC1272-3CCS LTC1272-8CCS
Consult factory for Industrial and Military grade parts.
COUVERTER CHARACTERISTICS |
With Internal Reference (Note 4) |
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LTC1272-XA |
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LTC1272-XC |
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PARAMETER |
CONDITIONS |
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MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
UNITS |
Resolution (No Missing Codes) |
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12 |
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12 |
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Bits |
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Integral Linearity Error |
(Note 5) |
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±1/2 |
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±1 |
LSB |
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Differential Linearity Error |
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±1 |
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±1 |
LSB |
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Offset Error |
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±3 |
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±4 |
LSB |
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±4 |
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±6 |
LSB |
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Gain Error |
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±10 |
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±15 |
LSB |
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Full-Scale Tempco |
IOUT (Reference) = 0 |
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±5 |
±25 |
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±10 |
±45 |
ppm/°C |
2
LTC1272
IUTERUAL REFEREUCE CHARACTERISTICS (Note 4) |
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LTC1272-XA |
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LTC1272-XC |
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PARAMETER |
CONDITIONS |
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MIN |
TYP |
MAX |
MIN |
TYP |
MAX |
UNITS |
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VREF Output Voltage (Note 6) |
IOUT = 0 |
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2.400 |
2.420 |
2.440 |
2.400 |
2.420 |
2.440 |
V |
VREF Output Tempco |
IOUT = 0 |
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25 |
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10 |
45 |
ppm/°C |
VREF Line Regulation |
4.75V £ VDD £ 5.25V, IOUT = 0 |
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0.01 |
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0.01 |
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LSB/V |
VREF Load Regulation (Sourcing Current) |
0 £ êIOUT ê £ 1mA |
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2 |
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LSB/mA |
DIGITAL AUD DC ELECTRICAL CHARACTERISTICS |
(Note 4) |
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LTC1272-XA/C |
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SYMBOL |
PARAMETER |
CONDITIONS |
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MIN |
TYP |
MAX |
UNITS |
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VIH |
High Level Input Voltage |
CS, |
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RD, |
HBEN, CLK IN |
VDD = 5.25V |
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2.4 |
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V |
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VIL |
Low Level Input Voltage |
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VDD = 4.75V |
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0.8 |
V |
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CS, |
RD, HBEN, CLK IN |
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IIN |
Input Current |
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HBEN |
VIN = 0V to VDD |
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±10 |
mA |
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CS, |
RD, |
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Input Current CLK IN |
VIN = 0V to VDD |
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±20 |
mA |
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VOH |
High Level Output Voltage All Logic Outputs |
VDD = 4.75V IOUT = – 10mA |
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4.7 |
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V |
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IOUT = – 200mA |
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4.0 |
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V |
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VOL |
Low Level Output Voltage All Logic Outputs |
VDD = 4.75V, IOUT = 1.6mA |
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0.4 |
V |
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IOZ |
High-Z Output Leakage D11-D0/8 |
VOUT = 0V to VDD |
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mA |
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COZ |
High-Z Output Capacitance (Note 7) |
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15 |
pF |
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ISOURCE |
Output Source Current |
VOUT = 0V |
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– 10 |
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mA |
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ISINK |
Output Sink Current |
VOUT = VDD |
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10 |
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mA |
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IDD |
Positive Supply Current |
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15 |
30 |
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CS |
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PD |
Power Dissipation |
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75 |
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mW |
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DYUAWIC ACCURACY (Note 4) fSAMPLE = 250kHz (LTC1272-3), 111kHz (LTC1272-8) |
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LTC1272-XA/C |
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SYMBOL |
PARAMETER |
CONDITIONS |
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MIN |
TYP |
MAX |
UNITS |
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S/(N + D) |
Signal-to-Noise Plus Distortion Ratio |
10kHz Input Signal |
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72 |
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THD |
Total Harmonic Distortion (Up to 5th Harmonic) |
10kHz Input Signal |
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– 82 |
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Peak Harmonic or Spurious Noise |
10kHz Input Signal |
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– 82 |
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AUALOG I
U
PUT
(Note 4)
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LTC1272-XA/B/C |
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SYMBOL |
PARAMETER |
CONDITIONS |
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MIN |
TYP |
MAX |
UNITS |
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VIN |
Input Voltage Range |
4.75V £ VDD £ 5.25V |
● |
0 |
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5 |
V |
IIN |
Input Current |
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3.5 |
mA |
CIN |
Input Capacitance |
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50 |
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pF |
tACQ |
Sample-and-Hold Acquisition Time |
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0.45 |
1 |
ms |
3
LTC1272
TIWIUG CHARACTERISTICS |
(Note 8) |
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LTC1272-XA/C |
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SYMBOL |
PARAMETER |
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CONDITIONS |
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MIN |
TYP |
MAX |
UNITS |
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t1 |
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CS |
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to |
RD |
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Setup Time |
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● |
0 |
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t2 |
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to |
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Delay |
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CL = 50pF |
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80 |
190 |
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RD |
BUSY |
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COM Grade |
● |
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230 |
ns |
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t3 |
Data Access Time After |
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↓ |
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CL = 20pF |
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50 |
90 |
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RD |
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COM Grade |
● |
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110 |
ns |
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CL = 100pF |
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70 |
125 |
ns |
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COM Grade |
● |
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150 |
ns |
t4 |
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Pulse Width |
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t3 |
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COM Grade |
● |
t3 |
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t5 |
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to |
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Hold Time |
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CS |
RD |
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t6 |
Data Setup Time After |
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40 |
70 |
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BUSY |
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COM Grade |
● |
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90 |
ns |
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t7 |
Bus Relinquish Time |
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20 |
30 |
75 |
ns |
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COM Grade |
● |
20 |
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85 |
ns |
t8 |
HBEN to |
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Setup Time |
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RD |
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t9 |
HBEN to |
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Hold Time |
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RD |
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t10 |
Delay Between |
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Operations |
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200 |
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RD |
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t11 |
Delay Between Conversions |
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t12 |
Aperture Delay of Sample and Hold |
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Jitter <50ps |
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25 |
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t13 |
CLK to |
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Delay |
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80 |
170 |
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BUSY |
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COM Grade |
● |
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220 |
ns |
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tCONV |
Conversion Time |
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● |
12 |
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13 |
CLK |
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CYCLES |
The ● indicates specifications which apply over the full operating temperature range; all other limits and typicals TA = 25°C.
Note 1: Absolute maximum ratings are those values beyond which the life of a device may be impaired.
Note 2: All voltage values are with respect to ground with DGND and AGND wired together, unless otherwise noted.
Note 3: When the analog input voltage is taken below ground it will be clamped by an internal diode. This product can handle, with no external diode, input currents of greater than 60mA below ground without latch-up.
Note 4: VDD = 5V, fCLK = 4MHz for LTC1272-3, and 1.6MHz for LTC1272-8, tr = tf = 5ns unless otherwise specified. For best analog
performance, the LTC1272 clock should be synchronized to the RD and CS control inputs with at least 40ns separating convert start from the nearest clock edge.
Note 5: Linearity error is specified between the actual end points of the A/D transfer curve.
Note 6: The LTC1272 has the same 0V to 5V input range as the AD7572 but, to achieve single supply operation, it provides a 2.42V reference output instead of the –5.25V of the AD7572. This requires that the polarity of the reference bypass capacitor be reversed when plugging an LTC1272 into an AD7572 socket.
Note 7: Guaranteed by design, not subject to test.
Note 8: VDD = 5V. Timing specifications are sample tested at 25°C to ensure compliance. All input control signals are specified with tr = tf = 5ns (10% to 90% of 5V) and timed from a voltage level of 1.6V. See Figures 13 through 17.
4
LTC1272
PIU FUUCTIOUS
AIN (Pin 1): Analog Input, 0V to 5V Unipolar Input.
VREF (Pin 2): 2.42V Reference Output. When plugging into an AD7572 socket, reverse the reference bypass capacitor polarity and short the 10Ω series resistor.
AGND (Pin 3): Analog Ground.
D11 to D4 (Pins 4-11): Three-State Data Outputs.
DGND (Pin 12): Digital Ground.
D3/11 to D0/8 (Pins 13-16): Three-State Data Outputs.
CLK IN (Pin 17): Clock Input. An external TTL/CMOS compatible clock may be applied to this pin or a crystal can be connected between CLK IN and CLK OUT.
CLK OUT (Pin 18): Clock Output. An inverted CLK IN signal appears at this pin.
Data Bus Output, CS and RD = LOW
HBEN (Pin 19): High Byte Enable Input. This pin is used to multiplex the internal 12-bit conversion result into the lower bit outputs (D7 to D0/8). See table below. HBEN also disables conversion starts when HIGH.
RD (Pin 20): Read Input. This active low signal starts a conversion when CS and HBEN are low. RD also enables the output drivers when CS is low.
CS (Pin 21): The Chip Select Input must be low for the ADC to recognize RD and HBEN inputs.
BUSY (Pin 22): The BUSY Output is low when a conversion is in progress.
NC (Pin 23): Not Connected Internally. The LTC1272 does not require negative supply. This pin can accommodate the –15V required by the AD7572 without problems.
VDD (Pin 24): Positive Supply, 5V.
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Pin 4 |
Pin 5 |
Pin 6 |
Pin 7 |
Pin 8 |
Pin 9 |
Pin 10 |
Pin 11 |
Pin 13 |
Pin 14 |
Pin 15 |
Pin 16 |
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MNEMONIC* |
D11 |
D10 |
D9 |
D8 |
D7 |
D6 |
D5 |
D4 |
D3/11 |
D2/10 |
D1/9 |
D0/8 |
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HBEN = LOW |
DB11 |
DB10 |
DB9 |
DB8 |
DB7 |
DB6 |
DB5 |
DB4 |
DB3 |
DB2 |
DB1 |
DB0 |
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HBEN = HIGH |
DB11 |
DB10 |
DB9 |
DB8 |
LOW |
LOW |
LOW |
LOW |
DB11 |
DB10 |
DB9 |
DB8 |
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*D11...D0/8 are the ADC data output pins.
DB11...DB0 are the 12-bit conversion results, DB11 is the MSB.
TYPICAL PERFORWAUCE CHARACTERISTICS
Integral Nonlinearity
INL ERROR (LSBs)
1.0
VDD = 5V fCLK = 4MHz
0.5
0
–0.5
–1.0
0 |
512 |
1024 |
1536 |
2048 |
2560 |
3072 |
3584 |
4096 |
CODE
LTC1272 • TPC01
5
LTC1272
TYPICAL PERFORWAUCE CHARACTERISTICS
INL ERROR (LSBs)
Differential Nonlinearity
1.0
VDD = 5V
fCLK = 4MHz
0.5
0
–0.5
–1.0
0 |
512 |
1024 |
1536 |
2048 |
2560 |
3072 |
3584 |
4096 |
CODE
LTC1272 • TPC02
VDD SUPPLY CURRENT, IDD (mA)
VDD Supply Current vs
Temperature
30
VDD = 5V 25 fCLK = 4MHz
20
15
10
5
0 |
–25 |
0 |
25 |
50 |
75 |
100 |
125 |
–55 |
TEMPERATURE (°C)
LT1272 • TPC03
Minimum Clock Frequency vs
Temperature
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600 |
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VDD = 5V |
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(kHz) |
500 |
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FREQUENCY |
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300 |
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CLOCK |
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200 |
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100 |
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–25 |
0 |
25 |
50 |
75 |
100 |
125 |
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–55 |
TEMPERATURE (°C)
LT1272 • TPC04
CLOCK FREQUENCY (MHz)
Maximum Clock Frequency vs Temperature
8
7
6
5
4
3
2 |
–25 |
0 |
25 |
50 |
75 |
100 |
125 |
–55 |
TEMPERATURE (°C)
LT1272 • TPC05
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VREF vs ILOAD (mA) |
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2.435 |
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2.430 |
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2.425 |
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(V) |
2.420 |
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ENOBs* |
V |
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REF |
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2.415 |
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2.410 |
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2.405 |
–4 |
–3 |
–2 |
–1 |
0 |
1 |
2 |
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IL (mA) |
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LT1272 • TPC06 |
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LTC1272 ENOBs* vs Frequency
12
11
10
9
8
7
6
5
4
3
2
fS = 250kHz 1 VDD = 5V
0
0 |
20 |
40 |
60 |
80 |
100 |
120 |
fIN (kHz)
LT1272 • TPC07
*EFFECTIVE NUMBER OF BITS, ENOBs = S/(N + D) – 1.76dB 6.02
6