Linear Technology LTC1290DMJ, LTC1290DISW, LTC1290DCSW, LTC1290BISW, LTC1290BIN Datasheet

FEATURES

■Software Programmable Features

–Unipolar/Bipolar Conversion

–Four Differential/Eight Single-Ended Inputs

–MSBor LSB-First Data Sequence

–Variable Data Word Length

–Power Shutdown

■Built-In Sample-and-Hold

■Single Supply 5V or ±5V Operation

■Direct Four-Wire Interface to Most MPU Serial Ports and All MPU Parallel Ports

■50kHz Maximum Throughput Rate

KEY SPECIFICATIOUS

■Resolution: 12 Bits

■Fast Conversion Time: 13 s Max Over Temp

■Low Supply Current: 6.0mA

LTC1290

Single Chip 12-Bit Data

Acquisition System

DESCRIPTIOU

The LTC®1290 is a data acquisition component which contains a serial I/O successive approximation A/D converter. It uses LTCMOSTM switched capacitor technology to perform either 12-bit unipolar or 11-bit plus sign bipolar A/D conversions. The 8-channel input multiplexer can be configured for either single-ended or differential inputs (or combinations thereof). An on-chip sample-and-hold is included for all single-ended input channels. When the LTC1290 is idle it can be powered down with a serial word in applications where low power consumption is desired.

The serial I/O is designed to be compatible with industry standard full duplex serial interfaces. It allows either MSBor LSB-first data and automatically provides 2's complement output coding in the bipolar mode. The output data word can be programmed for a length of 8, 12 or 16 bits. This allows easy interface to shift registers and a variety of processors.

, LTC and LT are registered trademarks of Linear Technology Corporation.

LTCMOS is a trademark of Linear Technology Corporation.

TYPICAL APPLICATIOU

12-Bit 8-Channel Sampling Data Acquisition System

SINGLE-ENDED INPUT

1k

0V TO 5V OR ±5V

CH0

VCC

5V

•

+

±15V OVERVOLTAGE RANGE*

22 F

•

CH1

ACLK

TANTALUM

1N5817

•

CH2

SCLK

TO AND FROM

CH3

DIN

1N4148

MICROPROCESSOR

DIFFERENTIAL INPUT (+)

CH4

DOUT

±5V COMMON MODE RANGE (–)

LTC1290

CH5

CS

•

REF +

8V TO 40V

CH6

LT®1027

•

+

•

CH7

REF –

4.7 F

1 F

COM

V –

–5V

TANTALUM

DGND

AGND

1N5817

0.1 F

1290 • TA01

*FOR OVERVOLTAGE PROTECTION ON ONLY ONE CHANNEL LIMIT THE INPUT CURRENT TO 15mA. FOR OVERVOLTAGE PROTECTION ON MORE THAN ONE CHANNEL LIMIT THE INPUT CURRENT TO 7mA PER CHANNEL AND 28mA FOR ALL CHANNELS. (SEE SECTION ON

OVERVOLTAGE PROTECTION IN THE APPLICATIONS INFORMATION SECTION.) CONVERSION RESULTS ARE NOT VALID WHEN THE SELECTED OR ANY OTHER CHANNEL IS OVERVOLTAGED (VIN < V– OR VIN > VCC).

1

LTC1290

ABSOLUTE

WAXIWUW

RATIUGS (Notes 1, 2)

Supply Voltage (V ) to GND or V –		........................ 12V
CC		– 6V to GND
Negative Supply Voltage (V –)	....................
Voltage	(V – ) – 0.3V to VCC + 0.3V
Analog/Reference Inputs .........
Digital Inputs ........................................		– 0.3V to 12V
Digital Outputs ...........................		– 0.3V to V CC + 0.3V
Power Dissipation .............................................		500mW

Operating Temperature Range

LTC1290BC, LTC1290CC, LTC1290DC .... 0°C to 70°C

LTC1290BI, LTC1290CI, LTC1290DI ....	– 40°C to 85°C
LTC1290BM, LTC1290CM,	– 55°C to 125°C
LTC1290DM.......................................
Storage Temperature Range ................	– 65°C to 150°C
Lead Temperature (Soldering, 10 sec.)................	300°C

PACKAGE/ORDER IUFORWATIOU

		TOP VIEW
					VCC
CH0	1			20
					ACLK
CH1	2			19
					SCLK
CH2	3			18
CH3	4			17	DIN
CH4	5			16	DOUT
CH5	6			15		CS
					REF+
CH6	7			14
					REF–
CH7	8			13
					V–
COM	9			12
					AGND
DGND	10			11
J PACKAGE			N PACKAGE
20-LEAD CERAMIC DIP			20-LEAD PDIP

TJMAX = 150°C, θJA = 80°C/W (J) TJMAX = 110°C, θJA = 100°C/W (N)

ORDER PART

NUMBER

LTC1290BMJ

LTC1290CMJ

LTC1290DMJ

LTC1290BIJ

LTC1290CIJ

LTC1290DIJ

LTC1290BIN

LTC1290CIN

LTC1290DIN

LTC1290BCN

LTC1290CCN

LTC1290DCN

			TOP VIEW
CH0
	1			20	VCC
CH1
	2			19	ACLK
CH2
	3			18	SCLK
CH3	4			17	DIN
CH4	5			16	DOUT
CH5	6			15		CS
					REF+
CH6	7			14
					REF–
CH7	8			13
COM					V–
	9			12
DGND
	10			11	AGND

SW PACKAGE

20-LEAD PLASTIC SO WIDE

TJMAX = 110°C, θJA = 130°C/W (SW)

ORDER PART

NUMBER

LTC1290BCSW

LTC1290CCSW

LTC1290DCSW

LTC1290BISW

LTC1290CISW

LTC1290DISW

COUVERTER AUD WULTIPLEXER CHARACTERISTICS (Note 3)

LTC1290B

LTC1290C

LTC1290D

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Offset Error

(Note 4)

●

±1.5

±1.5

±1.5

LSB

Linearity Error (INL)

(Notes 4,5)

●

±0.5

±0.5

±0.75

LSB

Gain Error

(Note 4)

●

±0.5

±1.0

±4.0

LSB

Minimum Resolution for Which

●

12

12

12

Bits

No Missing Codes are Guaranteed

Analog and REF Input Range

(Note 7)

(V–) – 0.05V to V

+ 0.05V

(V–) – 0.05V to V

CC

+ 0.05V

(V–) – 0.05V to V

CC

+ 0.05V

V

CC

On Channel Leakage Current

On Channel = 5V

●

±1

±1

±1

A

(Note 8)

Off Channel = 0V

On Channel = 0V

●

±1

±1

±1

A

Off Channel = 5V

Off Channel Leakage Current

On Channel = 5V

●

±1

±1

±1

A

(Note 8)

Off Channel = 0V

On Channel = 0V

●

±1

±1

±1

A

Off Channel = 5V

2

LTC1290

AC CHARACTERISTICS (Note 3)

LTC1290B/LTC1290C/LTC1290D

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

fSCLK

Shift Clock Frequency

VCC = 5V (Note 6)

0

2.0

MHz

fACLK

A/D Clock Frequency

VCC = 5V (Note 6)

(Note 10)

4.0

MHz

tACC

Delay time from

↓ to DOUT Data Valid

(Note 9)

2

ACLK

CS

Cycles

tSMPL

Analog Input Sample Time

See Operating Sequence

7

SCLK

Cycles

tCONV

Conversion Time

See Operating Sequence

52

ACLK

Cycles

tCYC

Total Cycle Time

See Operating Sequence (Note 6)

12 SCLK +

Cycles

56 ACLK

tdDO

Delay Time, SCLK↓ to DOUT Data Valid

See Test Circuits

LTC1290BC, LTC1290CC

●

130

220

ns

LTC1290DC, LTC1290BI

LTC1290CI, LTC1290DI

LTC1290BM, LTC1290CM

●

180

270

ns

LTC1290DM

tdis

Delay Time,

↑ to DOUT Hi-Z

See Test Circuits

70

100

ns

CS

●

ten

Delay Time, 2nd ACLK↓ to DOUT Enabled

See Test Circuits

●

130

200

ns

Hold Time,

After Last SCLK↓

VCC = 5V (Note 6)

0

ns

CS

thCS

thDI

Hold Time, DIN After SCLK↑

VCC = 5V (Note 6)

50

ns

thDO

Time Output Data Remains Valid After SCLK↓

50

ns

tf

DOUT Fall Time

See Test Circuits

●

65

130

ns

tr

DOUT Rise Time

See Test Circuits

●

25

50

ns

tsuDI

Setup Time, DIN Stable Before SCLK↑

VCC = 5V (Note 6)

50

ns

Setup Time,

↓ Before Clocking in

(Notes 6, 9)

2 ACLK Cycles

tsuCS

CS

First Address Bit

+ 100ns

tWHCS

CS High Time During Conversion

VCC = 5V (Note 6)

52

ACLK

Cycles

CIN

Input Capacitance

Analog Inputs On Channel

100

pF

Analog Inputs Off Channel

5

pF

Digital Inputs

5

pF

U

D DC

ELECTRICAL CHARACTERISTICS (Note 3)

DIGITAL A

LTC1290B/LTC1290C/LTC1290D

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP MAX

UNITS

VIH

High Level Input Voltage

VCC = 5.25V

●

2.0

V

VIL

Low Level Input Voltage

VCC = 4.75V

●

0.8

V

IIH

High Level Input Current

VIN = VCC

●

2.5

µA

IIL

Low Level Input Current

VIN = 0V

●

– 2.5

µA

VOH

High Level Output Voltage

VCC = 4.75V

IO = 10µA

4.7

V

IO = 360µA

●

2.4

4.0

V

VOL

Low Level Output Voltage

VCC = 4.75V

IO = 1.6mA

●

0.4

V

IOZ

High-Z Output Leakage

VOUT = VCC,

High

3

µA

CS

●

VOUT = 0V,

CS

High

●

– 3

µA

ISOURCE

Output Source Current

VOUT = 0V

–20

mA

3

LTC1290

U

D DC

ELECTRICAL CHARACTERISTICS

(Note 3)

DIGITAL A

LTC1290B/LTC1290C/LTC1290D

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

ISINK

Output Sink Current

VOUT = VCC

20

mA

ICC

Positive Supply Current

High

6

12

mA

CS

●

CS

High

LTC1290BC, LTC1290CC

●

5

10

A

Power Shutdown

LTC1290DC, LTC1290BI

ACLK Off

LTC1290CI, LTC1290DI

LTC1290BM, LTC1290CM

●

5

15

A

LTC1290DM

IREF

Reference Current

VREF = 5V

●

10

50

A

I–

Negative Supply Current

High

1

50

A

CS

●

The ● denotes specifications which apply over the full operating temperature range; all other limits and typicals TA = 25°C.

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.

Note 2: All voltage values are with respect to ground with DGND, AGND and REF– wired together (unless otherwise noted).

Note 3: VCC = 5V, VREF + = 5V, VREF – = 0V, V – = 0V for unipolar mode and

– 5V for bipolar mode, ACLK = 4.0MHz unless otherwise speicfied.

Note 4: These specs apply for both unipolar and bipolar modes. In bipolar mode, one LSB is equal to the bipolar input span (2VREF) divided by 4096. For example, when VREF = 5V, 1LSB (bipolar) = 2(5V)/4096 = 2.44mV.

Note 5: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.

Note 6: Recommended operating conditions.

Note 7: Two on-chip diodes are tied to each reference and analog input which will conduct for reference or analog input voltages one diode drop

below V – or one diode drop above VCC. Be careful during testing at low VCC levels (4.5V), as high level reference or analog inputs (5V) can cause this input diode to conduct, especially at elevated temperatures and cause errors for inputs near full scale. This spec allows 50mV forward bias of either diode. This means that as long as the reference or analog input does not exceed the supply voltage by more than 50mV, the output code will be correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V over initial tolerance, temperature variations and loading.

Note 8: Channel leakage current is measured after the channel selection.

Note 9: To minimize errors caused by noise at the chip select input, the internal circuitry waits for two ACLK falling edge after a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock an address in or data out until the minimum chip select setup time has elapsed.

Note 10: Increased leakage currents at elevated temperatures cause the

S/H to droop, therefore it's recommended that fACLK ≥ 500kHz at 125°C, fACLK ≥ 125kHz at 85°C and fACLK ≥ 15kHz at 25°C.

TYPICAL PERFORWAUCE CHARACTERISTICS

			Supply Current vs Supply Voltage												Supply Current vs Temperature
	26														10
				ACLK = 4MHz													ACLK = 4MHz
(mA)	22			TA = 25°C										(mA)	9		VCC = 5V
															8
	18
CC														CC
I														I
CURRENT,	14													CURRENT,	7
SUPPLY														SUPPLY	6
	10
															5
	6
															4
	2
															3
	4			6				8		10					–50			–30			–10		10		30		50		70		90		110		130
					SUPPLY VOLTAGE, V					(V)																					°
								CC												AMBIENT TEMPERATURE, TA ( C)
											1290 • TPC01																					LT1290 • TPC02

Unadjusted Offset Voltage vs

Reference Voltage

			0.9
)			0.8											VCC =	5V
	REF
• V			0.7
		4096
1			0.6
=
(LSB			0.5
							VOS = 0.25mV
ERROR			0.4
OFFSET
			0.3
			0.2					VOS =		0.125mV
			0.1
							3
			1		2								4			5

REFERENCE VOLTAGE, VREF (V)

1290 • TPC03

4

LTC1290

TYPICAL PERFORWAUCE CHARACTERISTICS

)
	REF
• V
1		4096
LINEARITY ERROR (LSB =

Change in Linearity vs Reference Voltage

1.25

VCC = 5V

1.00

0.75

0.50

0.25

0

0

1

2

3

4

5

REFERENCE VOLTAGE, VREF (V)

Change in Gain vs Reference

Voltage

)			0
	REF
• V
1	4096		–0.1
=
(LSBERROR			–0.2
IN GAIN			–0.3
			–0.4
CHANGE
					VCC = 5V
			–0.5
					2				3		4		5
			1

REFERENCE VOLTAGE, VREF (V)

MAGNITUDE OF OFFSET CHANGE ΔOFFSET (LSB)

Change in Offset vs Temperature

0.5

ACLK = 4MHz

VCC = 5V 0.4 VREF = 5V

0.3

0.2

0.1

0 –50 –30 –10 10 30 50 70 90 110 130

AMBIENT TEMPERATURE, TA (°C)

1290 • TPC04

	Change in Linearity Error vs
(LSB)	Temperature
	0.6
LINEARITYΔ
			ACLK = 4MHz
	0.5		VCC = 5V
			VREF = 5V
CHANGE	0.4
	0.3
LINEARITYOF	0.2
MAGNITUDE	0.1
	0
																90
	–50 –30				–10		10			30		50		70				110		130

AMBIENT TEMPERATURE, TA (°C)

MAGNITUDE OF GAIN CHANGE ΔGAIN (LSB)

1290 • TPC05

1290 • TPC06

Change in Gain Error vs

Temperature

0.5

ACLK = 4MHz

VCC = 5V 0.4 VREF = 5V

0.3

0.2

0.1

0 –50 –30 –10 10 30 50 70 90 110 130

AMBIENT TEMPERATURE, TA (°C)

1290 • TPC07

1290 • TPC08

Maximum ACLK Frequency vs

Source Resistance

	5		VCC = 5V
(MHz)
			VREF = 5V
	4		TA = 25°C
FREQUENCY*	3	VIN	+ INPUT
		RSOURCE–
			– INPUT
ACLK	2
MAXIMUM	1
	0	1k	10 k	100k
	100
		RSOURCE (Ω)
			1290 • TPC09

*MAXIMUM ACLK FREQUENCY REPRESENTS THE ACLK FREQUENCY AT WHICH A 0.1LSB SHIFT IN THE ERROR AT

ANY CODE TRANSITION FROM ITS 4MHz VALUE IS FIRST DETECTED.

Maximum Filter Resistor vs

Cycle Time

	10k
)	1k
** (Ω
FILTER	100
R
MAXIMUM			RFILTER	+
			VIN
	10		CFILTER ≥ 1 F	–
	1.0	100
	10		1000	10000

CYCLE TIME, tCYC (µs)

1290 • TPC10

**MAXIMUM RFILTER REPRESENTS THE FILTER RESISTOR VALUE AT WHICH A 0.1LSB CHANGE IN FULL-SCALE ERROR FROM ITS VALUE AT RFILTER = 0 IS FIRST DETECTED.

5

LTC1290

TYPICAL PERFORWAUCE CHARACTERISTICS

	Sample-and-Hold Acquisition																			Supply Current (Power Shutdown)
	Time vs Source Resistance																			vs Temperature
	100																		10
s)			VREF = 5V																9			ACLK OFF DURING
			V		CC	= 5V																POWER SHUTDOWN
(
0.02%			TA = 25°C															CC	8
			0V TO 5V INPUT STEP															A)
TIMEAQUISITIONTO																		(	7
																		CURRENT,SUPPLYI
																			6
				VIN		RSOURCE+
	10											+							5
												–
																			4
																			3
H																			2
S &																			1
	1																		0
																									–10							50				90				130
					100									1k		10k			–50 –30								10		30					70				110
												RSOURCE+ (Ω)												AMBIENT TEMPERATURE, TA (°C)
															LTC1290 • TPC11																							1290 • TPC12

Supply Current (Power Shutdown) vs ACLK

	200
	180		VCC = 5V
			CMOS LEVELS
A)	160
(
CC 140
I
CURRENT,	120
	100
SUPPLY	80
	60
	40
	20

0 1.00 2.00 3.00 4.00 ACLK FREQUENCY (MHz)

1290 • TPC13

Input Channel Leakage Current
vs Temperature	Noise Error vs Reference Voltage

	1000
CURRENTLEAKAGE(nA)	900					GUARANTEED			(LSBs)ERRORNOISE
	800
	700
	600
	500
CHANNELINPUT	400								TO-PEAK-PEAK
	300
	200					ON CHANNEL
	100
					OFF CHANNEL
	0					70	90
	–50 –30	–10	10	30	50			110	130
	AMBIENT TEMPERATURE, TA (°C)

2.25

LTC1290 NOISE 200µVP-P

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

0

1

2

3

4

5

REFERENCE VOLTAGE, VREF (V)

1290 • TPC14	1290 • TPC15

PIU FUUCTIOUS

CH0 to CH7 (Pin 1 to Pin 8): Analog Inputs. The analog inputs must be free of noise with respect to AGND.

COM (Pin 9): Common. The common pin defines the zero reference point for all single-ended inputs. It must be free of noise and is usually tied to the analog ground plane.

DGND (Pin 10): Digital Ground. This is the ground for the internal logic. Tie to the ground plane.

AGND (Pin 11): Analog Ground. AGND should be tied directly to the analog ground plane.

V – (Pin 12): Negative Supply. Tie V – to most negative potential in the circuit. (Ground in single supply applications.)

REF –, REF + (Pins 13, 14): Reference Inputs. The reference inputs must be kept free of noise with respect to AGND.

CS (Pin 15): Chip Select Input. A logic low on this input enables data transfer.

DOUT (Pin 16): Digital Data Output. The A/D conversion result is shifted out of this output.

6

LTC1290

PIU FUUCTIOUS

DIN (Pin 17): Digital Data Input. The A/D configuration word is shifted into this input after CS is recognized.

SCLK (Pin 18): Shift Clock. This clock synchronizes the serial data transfer.

ACLK (Pin 19): A/D Conversion Clock. This clock controls the A/D conversion process.

VCC (Pin 20): Positive Supply. This supply must be kept free of noise and ripple by bypassing directly to the analog ground plane.

BLOCK DIAGRAM

	20							18		SCLK
VCC
	17		INPUT			OUTPUT		16		DOUT
DIN			SHIFT			SHIFT
			REGISTER			REGISTER

1
CH0		SAMPLE-
2
		AND-
CH1
3		HOLD	COMP
CH2
4
CH3	ANALOG		12-BIT
5
	INPUT MUX
CH4			SAR
6
CH5			12-BIT
7
			CAPACITIVE
CH6
8			DAC
CH7
9
COM

19

ACLK

										CONTROL	15
	10		11		12		13		14			CS
										AND
DGND		AGND		V–		REF–		REF+		TIMING

LTC1290 • BD

TEST CIRCUITS

On and Off Channel Leakage Current

Load Circuit for tdis and ten

5V

	ION	TEST POINT
	A	ON CHANNEL
	IOFF	3k	5V WAVEFORM 2
	A	DOUT
			WAVEFORM 1
	•	100pF
		OFF
	•	CHANNELS
	•		LTC1290 • TC02
	•
	POLARITY	LTC1290 • TC01

7

LTC1290

TEST CIRCUITS

Voltage Waveforms for DOUT Delay Time, tdDO

SCLK

0.8V

tdDO

2.4V

DOUT

0.4V

LTC1290 • TC03

Voltage Waveform for DOUT Rise and Fall Times, tr, tf

2.4V

DOUT

0.4V

tr								tf	LTC1290 • TC04

Load Circuit for tdDO, tr and tf

DOUT

1.4V

3k

100pF

TEST POINT

1290 • TC05

Voltage Waveforms for ten and tdis

1

2

ACLK

2.0V

CS

DOUT

2.4V

90%

WAVEFORM 1

(SEE NOTE 1)

ten

tdis

DOUT

WAVEFORM 2

0.8V

10%

(SEE NOTE 2)

LTC1290 • TC06

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL. NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.

8

LTC1290

APPLICATIOUS IUFORWATIOU

The LTC1290 is a data acquisition component which contains the following functional blocks:

1.12-bit successive approximation capacitive A/D converter

2.Analog multiplexer (MUX)

3.Sample-and-hold (S/H)

4.Synchronous, full duplex serial interface

5.Control and timing logic

DIGITAL CONSIDERATIONS

Serial Interface

The LTC1290 communicates with microprocessors and other external circuitry via a synchronous, full duplex, four-wire serial interface (see Operating Sequence). The shift clock (SCLK) synchronizes the data transfer with each bit being transmitted on the falling SCLK edge and captured on the rising SCLK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex).

Data transfer is initiated by a falling chip select (CS) signal. After the falling CS is recognized, an 8-bit input word is shifted into the DIN input which configures the LTC1290 for the next conversion. Simultaneously, the result of the previous conversion is output on the DOUT line. At the end

of the data exchange the requested conversion begins and CS should be brought high. After tCONV, the conversion is complete and the results will be available on the next data transfer cycle. As shown below, the result of a conversion is delayed by one CS cycle from the input word requesting it.

DIN

DIN WORD 1

DIN WORD 2

DIN WORD 3

DOUT

DOUT WORD 0

DOUT WORD 1

DOUT WORD 2

DATA

tCONV

DATA

tCONV

TRANSFER

A/D

TRANSFER

A/D

CONVERSION

CONVERSION

LTC1290 • AI01

Input Data Word

The LTC1290 8-bit data word is clocked into the DIN input on the first eight rising SCLK edges after chip select is recognized. Further inputs on the DIN pin are then ignored until the next CS cycle. The eight bits of the input word are defined as follows:

				UNIPOLAR/			WORD
				BIPOLAR			LENGTH
SGL/	ODD/	SELECT	SELECT	UNI	MSBF		WL1	WL0
DIFF	SIGN	1	0
	MUX ADDRESS				MSB-FIRST/
					LSB-FIRST			LTC1290 • AI02

Operating Sequence

(Example: Differential Inputs (CH3-CH2), Bipolar, MSB-First and 12-Bit Word Length)

tCYC

SCLK

1

2

3

4

5

6

7

8

9

10

11

12

DON’T CARE

tSMPL

tCONV

CS

DIN

DON’T CARE

DOUT

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

SHIFT CONFIGURATION

(SB)

SHIFT A/D RESULT OUT AND

WORD IN

NEW CONFIGURATION WORD IN

LTC1290 • AI03

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