Linear Technology LTC1421ISW-2.5, LTC1421ISW, LTC1421IG-2.5, LTC1421CSW, LTC1421CG-2.5 Datasheet

FEATURES

■Allows Safe Board Insertion and Removal from a Live Backplane

■System Reset and Power Good Control Outputs

■Programmable Electronic Circuit Breaker

■User Programmable Supply Voltage Power-Up Rate

■High Side Driver for Two External N-Channels

■Controls Supply Voltages from 3V to 12V

■Connection Inputs Detect Board Insertion or Removal

■Undervoltage Lockout

■Power-On Reset Input

APPLICATIOUS

■Hot Board Insertion

■Electronic Circuit Breaker

, LTC and LT are registered trademarks of Linear Technology Corporation.

Hot Swap is a trademark of Linear Technology Corporation.

LTC1421/LTC1421-2.5

Hot Swap Controller

DESCRIPTIOU

The LTC®1421/LTC1421-2.5 are Hot SwapTM controllers that allow a board to be safely inserted and removed from a live backplane. Using external N-channel pass transistors, the board supply voltages can be ramped up at a programmable rate. Two high side switch drivers control the N- channel gates for supply voltages ranging from 3V to 12V.

A programmable electronic circuit breaker protects against shorts. Warning signals indicate that the circuit breaker has tripped, a power failure has occurred or that the switch drivers are turned off. The reset output can be used to generate a system reset when the power cycles or a fault occurs. The two connect inputs can be used with staggered connector pins to indicate board insertion or removal. The power-on reset input can be used to cycle the board power or clear the circuit breaker.

The trip point of the ground sense comparator is set at 0.1V for LTC1421 and 2.5V for LTC1421-2.5.

The LTC1421/LTC1421-2.5 are available in 24-pin SO and SSOP packages.

TYPICAL APPLICATIOU

VEE

VDD

VCC

STAGGERED CONNECTOR

FAULT

POR

GND

DATA

BUS

Q3

VEE

1/2 Si4936DY

C3

– 12V

R4

1A

0.47µF

20k

+

CLOAD

Q2

R2

5%

VDD

1 0.025Ω 2

1/2 Si4936DY

+

12V

3

4

1A

R1

Q1

CLOAD

1 0.005Ω 2

MTB50N06E

VCC

10k

R6

+

5V

3

4

5A

D1

23

22

21

20

19

18

17

16

C2

20k

CLOAD

1%

VCCLO

SETLO GATELO VOUTLO VCCHI

SETHI

GATEHI VOUTHI

0.1µF

R5

10

R3

RAMP

16k

2

9

5%

1k

CON2

CPON

24

AUXVCC

COMP –

14

R7

C1

COMP +

13

1µF

1µF

LTC1421

8

7.15k

REF

4

11

1%

µP

FAULT

FB

COMPOUT

15

I/O

3

6

POR

PWRGD

I/O

1

CON1

GND

DISABLE

RESET

7

RESET

12

5

1

13

BEA

VCC

BEB

12

DATA BUS

GND

QS3384

1421 TA01

QuickSwitch IS A REGISTERED TRADEMARK

QuickSwitch®

OF QUALITY SEMICONDUCTOR CORPORATION.

BACKPLANE

PC BOARD

1

LTC1421/LTC1421-2.5

ABSOLUTE WAXIWUW RATINGSU

(Note 1)

Supply Voltage (VCCLO, VCCHI, AUXVCC)		.............. 13.2V
Input Voltage (Analog Pins) .....	– 0.3V to (VCCHI + 0.3V)
Input Voltage (Digital Pins)...................		– 0.3V to 13.2V
Output Voltage (Digital Pins) ..	– 0.3V to (VCCLO + 0.3V)
Output Voltage (CPON) .........	– 13.2V to (VCCLO + 0.3V)
Output Voltage (VOUTLO, VOUTHI) ...........		– 0.3V to 13.2V
Output Voltage (GATELO, GATEHI) ...........		– 0.3V to 20V
Operating Temperature Range		0 ° C to 70°C
LTC1421C ...............................................
LTC1421I ...........................................		– 40 ° C to 85°C
Storage Temperature Range ................		– 65 ° C to 150°C
Lead Temperature (Soldering, 10 sec).................		300°C

PACKAGE/ORDER IUFORWATIOU

TOP VIEW

ORDER PART

AUXVCC

NUMBER

CON1

1

24

VCCLO

CON2

2

23

LTC1421CG

POR

3

22

SETLO

LTC1421CSW

FAULT

4

21

GATELO

LTC1421CG-2.5

DISABLE

5

20

VOUTLO

LTC1421CSW-2.5

PWRGD

6

19

VCCHI

LTC1421IG

RESET

7

18

SETHI

LTC1421ISW

REF

8

17

GATEHI

LTC1421IG-2.5

CPON

9

16

VOUTHI

LTC1421ISW-2.5

RAMP

10

15

COMPOUT

COMP –

FB

11

14

COMP +

GND

12

13

G PACKAGE

SW PACKAGE

24-LEAD PLASTIC SSOP 24-LEAD PLASTIC SO

TJMAX =

125°C, θJA = 100°C/W (G)

TJMAX =

125°C, θJA = 85°C/W (SW)

Consult factory for parts specified with wider operating temperature ranges.

ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCCHI = 12V, VCCLO = 5V unless otherwise noted (Note 2).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

DC

Characteristics

ICCLO

VCCLO Supply Current

CON1

=

CON2

= GND,

POR

= VCCLO

●

1.5

3

mA

ICCHI

VCCHI Supply Current

=

= GND,

= VCCLO

0.6

1

mA

CON1

CON2

POR

●

VLKO

Undervoltage Lockout

VCCLO and VCCHI

2.28

2.45

2.60

V

VLKH

Undervoltage Lockout Hysteresis

VCCLO and VCCHI

100

mV

VREF

Reference Output Voltage

No Load

●

1.220

1.232

1.244

V

VLNR

Reference Line Regulation

3V ≤ VCCLO ≤ 12V, No Load

●

4

8

mV

VLDR

Reference Load Regulation

IO =0mA to – 5mA, Sourcing Only

●

1

3

mV

IRSC

Reference Short-Circuit Current

VREF = 0V

– 45

mA

VCOF

Comparator Offset Voltage

0V ≤ VCM ≤(VCCLO − 1.3V)

●

±10

mV

VCPSR

Comparator Power Supply Rejection

0V ≤ VCM ≤(VCCLO − 1.3V), 3V ≤ VCCLO ≤ 12V

●

1

mV/V

VCHST

Comparator Hysteresis

0V ≤ VCM ≤(VCCLO − 1.3V)

7

mV

VRST

Reset Voltage Threshold (VOUTLO)

FB = VOUTLO

●

2.80

2.90

3.00

V

FB = Floating

●

4.50

4.65

4.75

V

FB = GND

●

5.75

5.88

6.01

V

VRHST

Reset Threshold Hysteresis (VOUTLO)

FB = VOUTLO

7

mV

FB = Floating

12

mV

FB = GND

15

mV

RFB

FB Pin Input Resistance

0V ≤ VFB ≤ VCCLO

95

kΩ

VCB

Circuit Breaker Trip Voltage

VCB = (VCCLO – VSETLO) or VCB = (VCCHI – VSETHI)

●

40

50

60

mV

VTRIP

Output Voltage for Re-Power-Up

LTC1421 (Note 3)

0.1

V

LTC1421-2.5 (Note 4)

2.5

V

2

LTC1421/LTC1421-2.5

ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCCHI = 12V, VCCLO = 5V unless otherwise noted (Note 2).

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

IRAMP

RAMP Pin Output Current

Charge Pump On, VRAMP = 0.4V

●

11

17

23

µA

ICP

Charge Pump Output Current

Charge Pump On, GATEHI = 0V

– 600

µA

GATELO = 0V

– 300

µA

VGATEHI

GATEHI N-Channel Gate Drive

VGATEHI − VOUTHI

6

16

V

VGATELO

GATELO N-Channel Gate Drive

VGATELO − VOUTLO

10

16

V

VAUXVCC

Auxiliary VCC Output Voltage

VCCLO = 5V, Unloaded

4.5

V

VIL

Input Low Voltage

0.8

V

CON1,

CON2,

POR

●

VIH

Input High Voltage

2

V

CON1,

CON2,

POR

●

IIN

Input Current

= GND

– 30

– 60

– 90

µA

CON1,

CON2,

POR

●

VOL

Output Low Voltage

COMPOUT, PWRGD, DISABLE,

0.4

V

RESET,

FAULT,

●

IO = 3mA

CPON, IO = 3mA

●

1.45

V

VOH

Output High Voltage

DISABLE, IO = – 3mA

●

4

V

CPON, IO = – 1mA

●

3.4

V

IPU

Logic Output Pull-Up Current

PWRGD,

= GND

– 15

µA

RESET,

FAULT

AC CHARACTERISTICS

t1

CON1

or

CON2

↓to CPON↑

Figure 1, CL = 15pF

●

15

20

30

ms

t2

PWRGD↑to

↑

Figure 1, RL = 10k to VCCLO, CL = 15pF

160

200

240

ms

RESET

●

140

200

280

ms

t3

PWRGD↑to DISABLE↓

Figure 1, CL = 15pF

160

200

240

ms

●

140

200

280

ms

t4

↓ to CPON↓

Figure 1, CL = 15pF

15

20

30

ms

POR

●

t5

PWRGD↓to

↓

Figure 1, RL = 10k to VCCLO, CL = 15pF

32

µs

RESET

t6

↑ to CPON↑

Figure 1, CL = 15pF

50

ns

POR

t7

or

↑to CPON↓

Figure 1, CL = 15pF

50

ns

CON1

CON2

t9

Short-Circuit Detect to

↓

Figure 1, RL = 10k to VCCLO, CL = 15pF

20

µs

FAULT

VCCLO – SETLO = 0mV to 100mV

t10

Short-Circuit Detect to CPON↓

Figure 2, CL = 15pF

20

µs

VCCLO – SETLO = 0mV to 100mV

t11

↑ to

↑

Figure 2, RL = 10k to VCCLO, CL = 15pF

20

ns

POR

FAULT

tCHL

Comparator High to Low

COMP – = 1.232V, 10mV Overdrive

●

0.25

0.5

µs

RL = 10k to VCCLO, CL = 15pF

tCLH

Comparator Low to High

COMP – = 1.232V, 10mV Overdrive

●

1

1.5

µs

RL = 10k to VCCLO, CL = 15pF

Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.

Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are reference to ground unless otherwise specified.

Note 3: After power-on reset, the VOUTLO and VOUTHI have to drop below the VTRIP point before the charge pump is restarted.

Note 4: After power-on reset, the VOUTLO has to drop below the VTRIP point before the charge pump is restarted.

3

LTC1421/LTC1421-2.5

TYPICAL PERFORWAUCE CHARACTERISTICS

	Reference Voltage vs
	Temperature												Gate Voltage vs Temperature
	1.238											24
			VCCLO = 5V											VCCLO = 5V
(V)	1.236		VCCHI = 12V									23		VCCHI = 12V
	1.234										VOLTAGEGATE(V)	22
VOLTAGEREFERENCE
	1.232																GATEHI
												21
	1.230											20
	1.228											19
	1.226											18					GATELO
	1.224											17

– 50 – 25	0	25 50	75 100 125	– 50 – 25	0	25 50	75 100 125
	TEMPERATURE (°C)				TEMPERATURE (°C)
			1421 G01				1421 G02

GATELO Voltage vs VCCLO Voltage

	26
				VCCHI = 12V
(V)	24
	22
VOLTAGE	20
GATELO	18
	16
	14
	12
										8				12		14
	0			2		4		6				10
							VCCLO VOLTAGE (V)
															1421 G04
			ICCHI Supply Current
			vs Temperature
	555
				VCCLO = 5V
( A)	550			VCCHI = 12V
	545
CURRENT
	540
SUPPLY
	535
CCHI	530
I	525
	520
										50				100		125
	– 50 – 25					0		25				75

TEMPERATURE (°C)

1421 G07

GATEHI Voltage vs VCCHI Voltage

	26
			VCCLO = 5V
(V)	24
	22
VOLTAGE
	20
GATEHI	18
	16
	14
	12
								8			12		14
	0		2	4		6			10

VCCHI VOLTAGE (V)

1421 G05

VOL vs ISINK

	600
			VCCLO = 5V
	500		VCCHI = 12V
(mV)	400					COMPOUT
							PWRGD
VOLTAGE	300						RESET
											FAULT
	200
	100
	0
			2			4		6		8				10
	0

SINK CURRENT (mA)

1421 G08

Reference Voltage vs Source Current

	1.245
					VCCLO			=		5V
					VCCHI			=		12V
(V)	1.240
VOLTAGE	1.235
REFERENCE	1.230
	1.225
	1.220
					2										4				6				8				10
	0
										SOURCE CURRENT (mA)
																										1421 G03
	ICCLO Supply Current
	vs Temperature
					VCCLO = 5V
( A)	1500				VCCHI = 12V
CURRENTSUPPLY	1400
CCLO	1300
I
	1200
															25 50								100				125
	– 50 – 25									0									75
											TEMPERATURE (°C)
																										1421 G06
			CPON Voltage vs Sink Current
			(Charge Pump Off)
	2.5
					VCCLO = 5V
					VCCHI = 12V
(V)	2.0
VOLTAGE	1.5
CPON	1.0
	0.5
	0
					0.5					1.0					1.5				2.0				2.5				3.0
	0

SINK CURRENT (mA)

1421 G09

4

LTC1421/LTC1421-2.5

TYPICAL PERFORWMANUCE CHARACTERISTICS

CPON VOLTAGE (V)

CPON Voltage vs Source Current (Charge Pump On)

5

VCCLO = 5V

VCCHI = 12V

4

3

2

1

0

0 – 0.5 – 1.0 – 1.5 – 2.0 – 2.5 – 3.0 SOURCE CURRENT (mA)

1421 G10

ICCLO SUPPLY CURRENT (mA)

ICCLO Supply Current vs VCCLO Voltage

7 VCCHI = 12V

6

5

4

3

2

1

0

0

2

4

6

8

10

12

14

VCCLO VOLTAGE (V)

1421 G11

PIUN FUUNCTIOUNS

CON1 (Pin 1): TTL Level Input with a Pull-Up to VCCLO.

Together with CON2, it is used to indicate board connection. The pin must be tied to ground on the host side of the connector. When using staggered connector pins, CON1 and CON2 must be the shortest and must be placed at opposite corners of the connector. Board insertion is assumed after CON1 and CON2 are both held low for 20ms after power-up.

CON2 (Pin 2): TTL Level Input with a Pull-Up to VCCLO. Together with CON1 it is used to indicate board connec-

tion.

POR (Pin 3): TTL Level Input with a Pull-Up to VCCLO. When the pin is pulled low for at least 20ms, a hard reset

is generated. Both VOUTLO and VOUTHI will turn off at a controlled rate. A power-up sequence will not start until

the POR pin is pulled high. If POR is pulled high before

VOUTLO and VOUTHI are fully discharged, a power-up sequence will not begin until the voltage at VOUTLO and VOUTHI are below VTRIP. The electronic circuit breaker will be reset by pulling POR low.

FAULT (Pin 4): Open Drain Output to GND with a Weak

Pull-Up to VCCLO. The pin is pulled low when an overcurrent fault is detected at VOUTLO or VOUTHI.

DISABLE (Pin 5): CMOS Output. The signal is used to disable the board’s data bus during insertion or removal.

PWRGD (Pin 6): Open Drain Output to GND with a Weak

Pull-Up to VCCLO. The pin is pulled low immediately after VOUTLO falls below its reset threshold voltage. The pin is pulled high immediately after VOUTLO rises above its reset threshold voltage.

RESET (Pin 7): Open Drain Output to GND with a Weak

Pull-Up to VCCLO. The pin is pulled low when a reset condition is detected. A reset will be generated when any

of the following conditions are met: Either CON1 or CON2

is high, POR is pulled low, VCCLO or VCCHI are below their respectiveundervoltagelockoutthresholds,PWRGDgoes

low or an overcurrent fault is detected at VOUTLO or VOUTHI. RESET will go high 200ms after PWRGD goes high. On power failure, RESET will go low 32 s after

PWRGD goes low.

REF (Pin 8): The Reference Voltage Output. VOUT = 1.232V

±1%. The reference can source up to 5mA of current. A 1 F bypass capacitor is recommended.

CPON (Pin 9): CMOS Output That Can Be Pulled Below Ground. CPON is pulled high when the internal charge pumps for GATELO and GATEHI are turned on. CPON is pulled low when the charge pumps are turned off. The pin can be used to control an external MOSFET for a – 5V to

– 12V supply.

5

LTC1421/LTC1421-2.5

PIU FUUCTIOUS

RAMP (Pin 10): Analog Power-Up Ramp Control Pin. By connecting an external capacitor between the RAMP and GATEHI, a positive linear voltage ramp on GATEHI and GATELO is generated on power-up with a slope equal to

20 A/CRAMP. A 10k resistor in series with the capacitor enhances the ESD performance at the GATEHI pin.

FB (Pin 11): Analog Feedback Input. FB is used to set the reset threshold voltage on VCCLO. For a 5V supply leave FB floating. For a 3.3V supply, short FB to VCCLO.

GND (Pin 12): Ground

COMP + (Pin 13): Noninverting Comparator Input.

COMP– (Pin 14): Inverting Comparator Input.

COMPOUT (Pin 15): Open Drain Comparator Output.

VOUTHI (Pin 16): High Supply Voltage Output. This must be the higher of the two supply voltage outputs.

GATEHI (Pin 17): The High Side Gate Drive for the High Supply N-Channel. An internal charge pump guarantees at least 6V of gate drive. The slope of the voltage rise at GATEHI is set by the external capacitor connected between GATEHI and RAMP. When the circuit breaker trips, GATEHI is immediately pulled to GND.

SETHI (Pin 18): The Circuit Breaker Set Pin for the High Supply. With a sense resistor placed in the supply path

between VCCHI and SETHI, the circuit breaker will trip when the voltage across the resistor exceeds 50mV for more

than 20 s. To disable the circuit breaker, VCCHI and SETHI should be shorted together.

VCCHI (Pin 19): The Positive Supply Input. This must be the higher of the two input supply voltages. An undervoltage

lockout circuit disables the chip until the voltage at VCCHI is greater than 2.45V.

VOUTLO (Pin 20): Low Supply Voltage Output. This must be the lower of the two supply voltage outputs.

GATELO (Pin 21): The High Side Gate Drive for the Low Supply N-Channel Pass Transistor. An internal charge pump guarantees at least 10V of gate drive. The slope of the voltage rise at GATELO is set by the external capacitor connected between GATEHI and RAMP. When the circuit breaker trips GATELO is immediately pulled to GND.

SETLO (Pin 22): The Circuit Breaker Set Pin for the Low Supply. With a sense resistor placed in the supply path

between VCCLO and SETLO, the circuit breaker will trip when the voltage across the resistor exceeds 50mV for

more than 20 s. To disable the circuit breaker, VCCLO and SETLO should be shorted together.

VCCLO (Pin 23): The Positive Supply Input. VCCLO must be equal to or lower voltage than VCCHI. An undervoltage

lockout circuit disables the chip until the voltage at VCCLO is greater than 2.45V.

AUXVCC (Pin 24): The supply input for the GATELO and GATEHI discharge circuitry. Connect a 1 F capacitor to

ground. AUXVCC is powered from VCCLO via an internal Schottky diode and series resistor.

6

LTC1421/LTC1421-2.5

BLOCK DIAGRAWM

	23	22	19	18
VCC	VCCLO	SETLO	VCCHI	SETHI
24 AUXVCC
	50mV +–	50mV	+–	AUXVCC

CP1	CP2
VCC
UNDERVOLTAGE
LOCKOUT

9 CPON

VCC

20 A

4 FAULT

DIGITAL CONTROL

1 CON1

2CON2

3POR

5 DISABLE

12

GND

21

10

17

GATELO RAMP GATEHI

CHARGE

PUMP

N2

CP3 +

+ –

+

–

CP4 –

+

1.232V

REFERENCE

RESET

TIMING

+

–

16 20

VOUTHI VOUTLO

N1

73.5k

VTRIP

71.5k FB 11

26.7k

REF 8

VCC

20 A

PWRGD 6

VCC

20 A

RESET 7

CP5

COMPOUT 15

COMP – 14

COMP + 13

1421 BD

SWITCHIUG TIWE WAVEFORWS

t1	t5	t7
t2
CON1
CON2
CPON
PWRGD
RESET
DISABLE
POR		1421 F01
t3	t4	t6

Figure 1. Nominal Operation Switching Waveforms

t5	t11	t2
t9
VCCLO – SETLO
FAULT
CPON
PWRGD
RESET
POR		1421 F02
t10	t6

Figure 2. Fault Detection Switching

7

LTC1421/LTC1421-2.5

APPLICATIOUS IUFORWATIOU

Hot Circuit Insertion

When circuit boards are inserted into a live backplane, the supply bypass capacitors on the board can draw huge transient currents from the backplane power bus as they charge up. The transient currents can cause permanent damage to the connector pins and cause glitches on the system supply, causing other boards in the system to reset. At the same time, the system data bus can be disrupted when the board’s data pins make or break connection.

The LTC1421 is designed to turn a board’s supply voltages on and off in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The chip also provides a disable signal for the board’s data bus buffer during insertion or removal and provides all the necessary supply supervisory functions for the board.

Power Supply Ramping

The power supplies on a board are controlled by placing external N-channel pass transistors in the power path (Figure 3). R1 and R2 provide current fault detection. By ramping the gate of the pass transistor up at a controlled rate, the transient surge current (I = C • dV/dt) drawn from the main backplane supply can be limited to a safe value when the board makes connection.

12V					1	R2	2	Q2			VOUTHI
									+
					3		4
										CLOAD
	R1		Q1
1		2									VOUTLO
5V		4							RRAMP	+
3											CLOAD
23		22	21	20	19		18	17	16

		VCCLO			SETLO GATELO VOUTLO VCCHI	SETHI GATEHI VOUTHI					CRAMP
1					LTC1421	10
		CON1				RAMP
2
		CON2						1421 F03

Figure 3: Supply Control Circuitry

When power is first applied to the chip, the gates of both N-channels, GATELO and GATEHI are pulled low. After the connection sense pins, CON1 and CON2 are both held low for at least 20ms, a 20 A reference current is connected from the RAMP pin to GND. The voltage at GATEHI begins

to rise with a slope equal to 20 A/CRAMP (Figure 4), where CRAMP is an external capacitor connected between the

12V		VOUTHI
		SLOPE = 20 A/CRAMP
5V		VOUTLO
t1	t2	1421 F4a

Figure 4. Supplies Turning On

RAMP and GATEHI pins. The voltage at the GATEHI pin is clamped one Schottky diode drop below GATELO.

The ramp time for each supply is equal to: t = (VCC)

(CRAMP)/20 A. During power down the gates are actively pulled down by two internal NFETs.

A negative supply voltage can be controlled using the CPON pin as shown in Figure 5.

When the board makes connection, the transistor Q3 is turned off because it’s gate is pulled low to –12V by R4. CPON is also pulled to –12V. When the charge pump is

turned on, CPON is pulled to VCCLO and the gate of Q3 will ramp up with a time constant determined by R4, R5 and

C2. When the charge pump is turned off, CPON goes into a high impedance state, the gate of Q3 is discharged to VEE with a time constant determined by R4 and C2, and Q3 turns off.

Q3

–12V FROM

1/2 MMDF3N0HD

VEE

CONNECTOR

R4

–12V

C2

CLOAD

1A

20k

0.047 F

5%

+

B

5V		R5
		16k
CPON
		5%
–12V		9
0V		CPON
B		LTC1421
–12V
0V
VEE
–12V
~1ms	~1ms	1421 F05

Figure 5. Negative Supply Control

8