CTLST CAT93C86U-TE13, CAT93C86U-1.8TE13, CAT93C86SI-TE13, CAT93C86SI-1.8TE13, CAT93C86SA-TE13 Datasheet

1

CAT93C46/56/57/66/86

1K/2K/2K/4K/16K-Bit Microwire Serial E

2

PROM

FEATURES

■ High Speed Operation:

– 93C46/56/57/66: 1MHz

– 93C86: 3MHz

■ Low Power CMOS Technology

■ 1.8 to 6.0 Volt Operation

■ Selectable x8 or x16 Memory Organization

■ Self-Timed Write Cycle with Auto-Clear

■ Hardware and Software Write Protection

■ Power-Up Inadvertant Write Protection

■ 1,000,000 Program/Erase Cycles

■ 100 Year Data Retention

■ Commercial, Industrial and Automotive

Temperature Ranges

■ Sequential Read (except 93C46)

■ Program Enable (PE) Pin (93C86 only)

93C46/56/57/66/86 F02

PIN CONFIGURATION

DIP Package (P)

SOIC Package (J)

CMOS E

2

PROM floating gate technology. The devices

are designed to endure 1,000,000 program/erase cycles

and have a data retention of 100 years. The devices are

available in 8-pin DIP, 8-pin SOIC or 8-pin TSSOP

packages.

DESCRIPTION

The CAT93C46/56/57/66/86 are 1K/2K/2K/4K/16K-bit

Serial E

2

PROM memory devices which are configured

as either registers of 16 bits (ORG pin at V

CC

) or 8 bits

(ORG pin at GND). Each register can be written (or read)

serially by using the DI (or DO) pin. The CAT93C46/56/

57/66/86 are manufactured using Catalyst’s advanced

SOIC Package (S)

93C46/56/57/66/86

F01

PIN FUNCTIONS

Pin Name Function

CS Chip Select

SK Clock Input

DI Serial Data Input

DO Serial Data Output

V

CC

+1.8 to 6.0V Power Supply

GND Ground

ORG Memory Organization

NC No Connection

PE* Program Enable

BLOCK DIAGRAM

Note: When the ORG pin is connected to VCC, the X16 organiza

tion is selected. When it is connected to ground, the X8 pin

is selected. If the ORG pin is left unconnected, then an

internal pullup device will select the X16 organization.

SOIC Package (K)

© 1998 by Catalyst Semiconductor, Inc.

Characteristics subject to change without notice

TSSOP Package (U)

*Only For 93C86

CS

SK

DI

DO

V

CC

NC (PE*)

ORG

GND

1

2

3

4

8

7

6

5

CS

SK

DI

DO

V

CC

ORG

GND

1

2

3

4

8

7

6

5

V

CC

CS

SK

ORG

GND

DO

DI

1

2

3

4

8

7

6

5

CS

SK

DI

DO

V

CC

ORG

GND

1

2

3

4

8

7

6

5

NC (PE*)

NC (PE*) NC (PE*)

8

7

6

5

V

CC

ORG

GND

DI

CS

SK

DO

1

2

3

4

NC (PE*)

V

CC

ADDRESS

DECODER

MEMORY ARRA Y

ORGANIZATION

DATA

REGISTER

MODE DECODE

LOGIC

CLOCK

GENERATOR

OUTPUT

BUFFER

DO

SK

CS

DI

ORG

GND

PE*

Doc. No. 25056-00 2/98 M-1

2

93C46/56/57/66/86

Doc. No. 25056-00 2/98 M-1

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on any Pin with

Respect to Ground

(1)

............ –2.0V to +V

CC

+2.0V

V

CC

with Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C)................................... 1.0W

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current

(2)

........................ 100 mA

*COMMENT

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of

the device at these or any other conditions outside of those

listed in the operational sections of this specification is not

implied. Exposure to any absolute maximum rating for

extended periods may affect device performance and

reliability.

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Reference Test Method

N

END

(3)

Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033

T

DR

(3)

Data Retention 100 Years MIL-STD-883, Test Method 1008

V

ZAP

(3)

ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015

I

LTH

(3)(4)

Latch-Up 100 mA JEDEC Standard 17

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V

CC

+0.5V, which may overshoot to V

CC

+2.0V for periods of less than 20 ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.

(3) This parameter is tested initially and after a design or process change that affects the parameter.

(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V

CC

+1V.

(5) Standby Current (ISB

2

)=0µA (<900nA) for 93C46/56/57/66, (ISB

2

)=2µA for 93C86.

D.C. OPERATING CHARACTERISTICS

V

CC

= +1.8V to +6.0V, unless otherwise specified.

Limits

Symbol Parameter Min. Typ. Max. Units Test Conditions

I

CC1

Power Supply Current 3 mA f

SK

= 1MHz

(Operating Write) V

CC

= 5.0V

I

CC2

Power Supply Current 500 µAf

SK

= 1MHz

(Operating Read) V

CC

= 5.0V

I

SB1

Power Supply Current 10 µA CS = 0V

(Standby) (x8 Mode) ORG=GND

I

SB2

(5)

Power Supply Current 0 µA CS=0V

(Standby) (x16Mode) ORG=Float or V

CC

I

LI

Input Leakage Current 1 µAV

IN

= 0V to V

CC

I

LO

Output Leakage Current 1 µAV

OUT

= 0V to V

CC

,

(Including ORG pin) CS = 0V

V

IL1

Input Low Voltage -0.1 0.8 4.5V≤V

CC

<5.5V

V

IH1

Input High Voltage 2 V

CC

+1

V

IL2

Input Low Voltage 0 V

CC

X0.2 1.8V≤V

CC

<2.7V

V

IH2

Input High Voltage V

CC

X0.7 V

CC

+1

V

OL1

Output Low Voltage 0.4 4.5V≤V

CC

<5.5V

V

OH1

Output High Voltage 2.4 I

OL

= 2.1mA

I

OH

= -400µA

V

OL2

Output Low Voltage 0.2 1.8V≤V

CC

<2.7V

V

OH2

Output High Voltage V

CC

-0.2 I

OL

= 1mA

I

OH

= -100µA

V

V

V

V

V

V

V

3

93C46/56/57/66/86

Doc. No. 25056-00 2/98 M-1

Note:

(1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE

and ERASE commands.

(2) Applicable only to 93C86

(3) This parameter is tested initially and after a design or process change that affects the parameter.

PIN CAPACITANCE

Symbol Test Max. Units Conditions

C

OUT

(3)

OUTPUT CAPACITANCE (DO) 5 pF V

OUT

=OV

C

IN

(3)

INPUT CAPACITANCE (CS, SK, DI, ORG) 5 pF V

IN

=OV

INSTRUCTION SET

Instruction Device Start Opcode Address Data Comments PE

(2)

Type Bit x8 x16 x8 x16

READ 93C46 1 10 A6-A0 A5-A0 Read Address AN–A0

93C56

(1)

1 10 A8-A0 A7-A0

93C66 1 10 A8-A0 A7-A0

93C57 1 10 A7-A0 A6-A0

93C86 1 10 A10-A0 A9-A0 X

ERASE 93C46 1 11 A6-A0 A5-A0 Clear Address AN–A0

93C56

(1)

1 11 A8-A0 A7-A0

93C66 1 11 A8-A0 A7-A0

93C57 1 11 A7-A0 A6-A0

93C86 1 11 A10-A0 A9-A0 I

WRITE 93C46 1 01 A6-A0 A5-A0 D7-D0 D15-D0 Write Address AN–A0

93C56

(1)

1 01 A8-A0 A7-A0 D7-D0 D15-D0

93C66 1 01 A8-A0 A7-A0 D7-D0 D15-D0

93C57 1 01 A7-A0 A6-A0 D7-D0 D15-D0

93C86 1 01 A10-A0 A9-A0 D7-D0 D15-D0 I

EWEN 93C46 1 00

11XXXXX 11XXXX

Write Enable

93C56 1 00

11XXXXXXX 11XXXXXX

93C66 1 00

11XXXXXXX 11XXXXXX

93C57 1 00

11XXXXXX 11XXXXX

93C86 1 00

11XXXXXXXXX 11XXXXXXXX

X

EWDS 93C46 1 00

00XXXXX 00XXXX

Write Disable

93C56 1 00

00XXXXXXX 00XXXXXX

93C66 1 00

00XXXXXXX 00XXXXXX

93C57 1 00

00XXXXXX 00XXXXX

93C86 1 00

00XXXXXXXXX 00XXXXXXXX

X

ERAL 93C46 1 00

10XXXXX 10XXXX

Clear All Addresses

93C56 1 00

10XXXXXXX 10XXXXXX

93C66 1 00

10XXXXXXX 10XXXXXX

93C57 1 00

10XXXXXX 10XXXXX

93C86 1 00

10XXXXXXXXX 10XXXXXXXX

I

WRAL 93C46 1 00

01XXXXX 01XXXX

D7-D0 D15-D0 Write All Addresses

93C56 1 00

01XXXXXXX 01XXXXXX

D7-D0 D15-D0

93C66 1 00

01XXXXXXX 01XXXXXX

D7-D0 D15-D0

93C57 1 00

01XXXXXX 01XXXXX

D7-D0 D15-D0

93C86 1 00

01XXXXXXXXX 01XXXXXXXX

D7-D0 D15-D0 I