CTLST CAT24WC64PI-TE13, CAT24WC64PI-1.8TE13, CAT24WC64PA-1.8TE13, CAT24WC64P-TE13, CAT24WC64P-1.8TE13 Datasheet

Preliminary

CAT24WC32/64

32K/64K-Bit I2C Serial CMOS E2PROM

FEATURES

■400 KHz I2C Bus Compatible*

■1.8 to 6 Volt Read and Write Operation

■Cascadable for up to Eight Devices

■32-Byte Page Write Buffer

■Self-Timed Write Cycle with Auto-Clear

■8-Pin DIP or 8-Pin SOIC

■Schmitt Trigger Inputs for Noise Protection

■ Zero Standby Current

■ Commercial, Industrial and Automotive

Temperature Ranges

■ Write Protection

– Entire Array Protected When WP at V

IH

■1,000,000 Program/Erase Cycles

■100 Year Data Retention

DESCRIPTION

The CAT24WC32/64 is a 32K/64K-bit Serial CMOS E2PROM internally organized as 4096/8192 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The

CAT24WC32/64 features a 32-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin DIP or 8-pin SOIC packages.

PIN CONFIGURATION	BLOCK DIAGRAM
DIP Package (P)	EXTERNAL LOAD

A0	1	8	VCC		DOUT	SENSE AMPS
						SHIFT REGISTERS
A1	2	7	WP		ACK
A2	3	6	SCL	VCC
VSS	4	5	SDA	VSS	WORD ADDRESS	COLUMN
					BUFFERS	DECODERS
							256
SOIC Package (J,K)				SDA	START/STOP
					LOGIC
A0	1	8	VCC
A1	2	7	WP			2	PROM
					XDEC	E
A2	3	6	SCL			128/256 128/256 X 256
VSS	4	5	SDA	WP	CONTROL
					LOGIC
		24WC32/64 F01
PIN FUNCTIONS
Pin Name		Function				DATA IN STORAGE
A0, A1, A2 Device Address Inputs
SDA	Serial Data/Address					HIGH VOLTAGE/
SCL	Serial Clock					TIMING CONTROL
WP	Write Protect			SCL	STATE COUNTERS
VCC	+1.8V to +6V Power Supply			A0	SLAVE
VSS	Ground			A1	ADDRESS
				A2	COMPARATORS
						24WC32/64 F02

* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.

© 1998 by Catalyst Semiconductor, Inc.	Doc. No. 25053-00 2/98 S-1
Characteristics subject to change without notice	1

CAT24WC32/64	Preliminary
ABSOLUTE MAXIMUM RATINGS*	*COMMENT

Temperature Under Bias .................	–55°C to +125°C
Storage Temperature .......................	–65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ...........	–2.0V to +VCC + 2.0V
VCC with Respect to Ground ...............		–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ...................................		1.0W
Lead Soldering Temperature (10 secs)		............ 300°C
Output Short Circuit Current(2) ........................		100mA

RELIABILITY CHARACTERISTICS

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

Symbol	Parameter	Min.	Max.	Units	Reference Test Method
NEND(3)	Endurance	1,000,000		Cycles/Byte	MIL-STD-883, Test Method 1033
TDR(3)	Data Retention	100		Years	MIL-STD-883, Test Method 1008
VZAP(3)	ESD Susceptibility	2000		Volts	MIL-STD-883, Test Method 3015
ILTH(3)(4)	Latch-up	100		mA	JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

			Limits
Symbol	Parameter	Min.		Typ.	Max.	Units	Test Conditions
ICC	Power Supply Current				3	mA	fSCL = 100 KHz
ISB(5)	Standby Current (VCC = 5V)				0	μA	VIN = GND or VCC
ILI	Input Leakage Current				10	μA	VIN = GND to VCC
ILO	Output Leakage Current				10	μA	VOUT = GND to VCC
VIL	Input Low Voltage	–1			VCC x 0.3	V
VIH	Input High Voltage	VCC x 0.7			VCC + 0.5	V
VOL1	Output Low Voltage (VCC = +3.0V)				0.4	V	IOL = 3.0 mA
VOL2	Output Low Voltage (VCC = +1.8V)				0.5	V	IOL = 1.5 mA

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol	Test	Max.	Units	Conditions
CI/O(3)	Input/Output Capacitance (SDA)	8	pF	VI/O = 0V
CIN(3)	Input Capacitance (A0, A1, A2, SCL, WP)	6	pF	VIN = 0V

Note:

(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.

(2)Output shorted for no more than one second. No more than one output shorted at a time.

(3)This parameter is tested initially and after a design or process change that affects the parameter.

(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

(5)Standby current (ISB ) = 0 μA (<900 nA).

Doc. No. 25053-00 2/98 S-1	2

Preliminary

CAT24WC32/64

A.C. CHARACTERISTICS

VCC = +1.8V to +6V, unless otherwise specified

Output Load is 1 TTL Gate and 100pF

Read & Write Cycle Limits

Symbol	Parameter	1.8V, 2.5 V		4.5V-5.5V
		Min.	Max.	Min.	Max.	Units
FSCL	Clock Frequency		100		400	kHz
TI(1)	Noise Suppression Time		200		200	ns
	Constant at SCL, SDA Inputs
tAA	SCL Low to SDA Data Out		3.5		1	μs
	and ACK Out
tBUF(1)	Time the Bus Must be Free Before	4.7		1.2		μs
	a New Transmission Can Start
tHD:STA	Start Condition Hold Time	4		0.6		μs
tLOW	Clock Low Period	4.7		1.2		μs
tHIGH	Clock High Period	4		0.6		μs
tSU:STA	Start Condition Setup Time	4.7		0.6		μs
	(for a Repeated Start Condition)
tHD:DAT	Data In Hold Time	0		0		ns
tSU:DAT	Data In Setup Time	50		50		ns
tR(1)	SDA and SCL Rise Time		1		0.3	μs
tF(1)	SDA and SCL Fall Time		300		300	ns
tSU:STO	Stop Condition Setup Time	4		0.6		μs
tDH	Data Out Hold Time	100		100		ns

Power-Up Timing (1)(2)

Symbol	Parameter	Max.	Units
tPUR	Power-Up to Read Operation	1	ms
tPUW	Power-Up to Write Operation	1	ms

Note:

(1)This parameter is tested initially and after a design or process change that affects the parameter.

(2)tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

Write Cycle Limits

Symbol	Parameter	Min.	Typ.	Max	Units
tWR	Write Cycle Time			10	ms

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus

interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

3	Doc. No. 25053-00 2/98 S-1