CTLST CAT25C33U14A-1.8TE13, CAT25C33U14-TE13, CAT25C33U14-1.8TE13, CAT25C33U-TE13, CAT25C33U-1.8TE13 Datasheet

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CAT25C03/05/09/17/33

2K/4K/8K/16K/32K SPI Serial CMOS E

PROM

FEATURES

■ 10 MHz SPI Compatible

■ 1.8 to 6.0 Volt Operation

■ Hardware and Software Protection

■ Zero Standby Current

■ Low Power CMOS Technology

■ SPI Modes (0,0 &1,1)

■ Commercial, Industrial and Automotive

Temperature Ranges

■ 1,000,000 Program/Erase Cycles

■ 100 Year Data Retention

■ Self-Timed Write Cycle

■ 8-Pin DIP/SOIC, 16-Pin SOIC and 14-Pin TSSOP

■ Page Write Buffer

■ Write Protection

– Protect First Page, Last Page, Any 1/4 Array

or Lower 1/2 Array

PIN CONFIGURATION

DIP Package (P)SOIC Package (S16)

PIN FUNCTIONS

Pin Name Function

SO Serial Data Output

SCK Serial Clock

WP Write Protect

+1.8V to +6.0V Power Supply

Ground

CS Chip Select

SI Serial Data Input

HOLD Suspends Serial Input

NC No Connect

BLOCK DIAGRAM

Characteristics subject to change without notice

Advanced

DESCRIPTION

The CAT25C03/05/09/17/33 is a 2K/4K/8K/16K/32K-Bit

SPI Serial CMOS E

PROM internally organized as

256x8/512x8/1024x8/2048x8/4096x8 bits. Catalyst’s

advanced CMOS Technology substantially reduces de-

vice power requirements. The CAT25C03/05 features a

16-byte page write buffer. The 25C09/17/33 features a

32-byte page write buffer.The device operates via the

SPI bus serial interface and is enabled though a Chip

Select (CS). In addition to the Chip Select, the clock

input (SCK), data in (SI) and data out (SO) are required

to access the device. The HOLD pin may be used to

suspend any serial communication without resetting the

serial sequence. The CAT25C03/05/09/17/33 is de-

signed with software and hardware write protection

features. The device is available in 8-pin DIP, 8-pin

SOIC, 16-pin SOIC, 8-pin TSSOP and 14-pin TSSOP

packages.

TSSOP Package (U14)

SENSE AMPS

SHIFT REGISTERS

SPI

CONTROL

LOGIC

WORD ADDRESS

BUFFERS

I/O

CONTROL

PROM

ARRAY

COLUMN

DECODERS

XDEC

HIGH VOL T A GE/

TIMING CONTROL

25C128 F02

STATUS

BLOCK

PROTECT

LOGIC

CONTROL LOGIC

DATA IN

STORAGE

HOLD

SCK

SOIC Package (S)

HOLD

SCK

HOLD

710

SCK

VCC

HOLDSO

NCNC

HOLD

VCC

NC NC

SCK

TSSOP Package (U)

SCL

HOLD

Doc. No. 25068-00 2/98

CAT25C03/05/09/17/33

Doc. No. 25068-00 2/98

Advanced

D.C. OPERATING CHARACTERISTICS

= +1.8V to +6.0V, unless otherwise specified.

Limits

Symbol Parameter Min. Typ. Max. Units Test Conditions

CC1

Power Supply Current 5 mA V

= 5V @ 5MHz

(Operating Write) SO=open; CS=Vss

CC2

Power Supply Current 0.4 mA V

= 5.5V

(Operating Read) F

CLK

= 5MHz

Power Supply Current 0 µA CS = V

(Standby) V

= V

or V

Input Leakage Current 2 µA

Output Leakage Current 3 µAV

OUT

= 0V to V

CS = 0V

(3)

Input Low Voltage -1 V

x 0.3 V

(3)

Input High Voltage V

x 0.7 V

+ 0.5 V

OL1

Output Low Voltage 0.4 V

OH1

Output High Voltage V

- 0.8 V

OL2

Output Low Voltage 0.2 V 1.8V≤V

<2.7V

OH2

Output High Voltage V

-0.2 V I

= 150µA

= -100µA

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on any Pin with

Respect to Ground

(1)

............ –2.0V to +V

+2.0V

with Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C)................................... 1.0W

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current

(2)

........................ 100 mA

*COMMENT

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation

of the device at these or any other conditions outside of

those listed in the operational sections of this specifica-

tion is not implied. Exposure to any absolute maximum

rating for extended periods may affect device perfor-

mance and reliability.

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Reference Test Method

END

(3)

Endurance 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033

(3)

Data Retention 100 Years MIL-STD-883, Test Method 1008

ZAP

(3)

ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015

LTH

(3)(4)

Latch-Up 100 mA JEDEC Standard 17

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V

+0.5V, which may overshoot to V

+2.0V for periods of less than 20 ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.

(3) This parameter is tested initially and after a design or process change that affects the parameter.

(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V

+1V.

4.5V≤V

<5.5V

= 3.0mA

= -1.6mA

CAT25C03/05/09/17/33

Doc. No. 25068-00 2/98

Advanced

Limits

1.8, 2.5 4.5V-5.5V Test

SYMBOL PARAMETER Min. Max. Min. Max. UNITS Conditions

Data Setup Time 50 10 ns V

= 2.4V

Data Hold Time 50 20 ns C

= 100pF

SCK High Time 200 40 ns V

= 0.8V

SCK Low Time 200 40 ns V

= 2.0v

SCK

Clock Frequency DC 2 DC 10 MHz

HOLD to Output Low Z 50 50 ns

(1)

Input Rise Time 2 2 µs

(1)

Input Fall Time 2 2 µs

HOLD Setup Time 100 40 ns

HOLD HOLD Time 100 40 ns C

= 100pF

Write Cycle Time 10 5 ms

Output Valid from Clock Low 200 80 ns

Output HOLD Time 0 0 ns

DIS

Output Disable Time 250 75 ns

HOLD to Output High Z 100 50 ns

CS High Time 250 100 ns

CSS

CS Setup Time 250 100 ns

CSH

CS HOLD Time 250 100 ns

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

A.C. CHARACTERISTICS

Figure 1. Sychronous Data Timing

= 50pF

VALID IN

CSS

HI-Z

CSH

DIS

HI-Z

SCK

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