CTLST CAT25C64U20I-TE13, CAT25C64U20I-1.8TE13, CAT25C64U20A-TE13, CAT25C64U20A-1.8TE13, CAT25C32U14I-1.8TE13 Datasheet

Advanced Information

CAT25C32/64

32K/64K-Bit SPI Serial CMOS E2PROM

FEATURES

■10 MHz SPI Compatible

■1.8 to 6.0 Volt Operation

■Hardware and Software Protection

■Zero Standby Current

■Low Power CMOS Technology

■SPI Modes (0,0 &1,1)

■Commercial, Industrial and Automotive Temperature Ranges

■1,000,000 Program/Erase Cycles

■100 Year Data Retention

■Self-Timed Write Cycle

■8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOPand 20-Pin TSSOP

■64-Byte Page Write Buffer

■Block Write Protection

– Protect 1/4, 1/2 or all of E2PROM Array

DESCRIPTION

The CAT25C32/64 is a 32K/64K-Bit SPI Serial CMOS E2PROM internally organized as 4Kx8/8Kx8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The CAT25C32/ 64 features a 64-byte page write buffer. The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are

required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C32/64 is designed with software and hardware write protection features including Block write protection. The device is available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and 20-pin TSSOP packages.

PIN CONFIGURATION

BLOCK DIAGRAM

SOIC Package (S) TSSOP Package (U14) TSSOP Package (U20)

														CS		1	14	VCC		1
	CS						1	8					VCC						NC		20	NC
							2	7						SO		2	13	HOLD	CS	2	19	VCC
	SO												HOLD NC			3	12	NC
							3	6											SO	3	18	HOLD
													SCK	NC		4	11	NC			17
	WP																		SO	4		HOLD
VSS							4	5					SI	NC		5	10	NC	NC	5	16	NC
														WP		6	9	SCK	NC	6	15	NC
														VSS		7	8	SI	WP	7	14	SCK

	DIP Package (P)							VSS		8	13		SI
								NC		9	12		NC		SO
	CS			1	8	VCC		NC		10	11		NC			SI
	SO			2	7	HOLD
															CS
				3	6
WP						SCK
														WP
VSS				4	5
						SI
														HOLD
														SCK

PIN FUNCTIONS

Pin Name	Function
SO	Serial Data Output
SCK	Serial Clock
WP	Write Protect
VCC	+1.8V to +6.0V Power Supply
VSS	Ground
CS	Chip Select
SI	Serial Data Input
HOLD	Suspends Serial Input
NC	No Connect

	SENSE AMPS
	SHIFT REGISTERS
WORD ADDRESS	COLUMN
BUFFERS	DECODERS

I/O

CONTROL

CONTROL

E2PROM

SPI

XDEC

ARRAY

CONTROL

LOGIC

LOGIC

BLOCK

PROTECT

LOGIC

DATA IN

STORAGE

HIGH VOLTAGE/

TIMING CONTROL

STATUS

REGISTER

© 1999 by Catalyst Semiconductor, Inc.	Doc No. 25087-00 8/99 SPI-1
Characteristics subject to change without notice

CAT25C32/64	Advanced Information
ABSOLUTE MAXIMUM RATINGS*	*COMMENT

Temperature Under Bias .................	–55°C to +125°C
Storage Temperature .......................	–65°C to +150°C
Voltage on any Pin with
Respect to VSS1) ...................	–2.0V to +VCC +2.0V
VCC with Respect to VSS ................................		–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ...................................		1.0W
Lead Soldering Temperature (10 secs)		............ 300°C
Output Short Circuit Current(2) ........................		100 mA

RELIABILITY CHARACTERISTICS

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

Symbol	Parameter	Min.	Max.	Units	Reference Test Method
NEND(3)	Endurance	1,000,000		Cycles/Byte	MIL-STD-883, Test Method 1033
TDR(3)	Data Retention	100		Years	MIL-STD-883, Test Method 1008
VZAP(3)	ESD Susceptibility	2000		Volts	MIL-STD-883, Test Method 3015
ILTH(3)(4)	Latch-Up	100		mA	JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

			Limits
Symbol	Parameter	Min.	Typ.	Max.	Units	Test Conditions
ICC1	Power Supply Current			10	mA	VCC = 5V @ 10MHz
	(Operating Write)					SO=open; CS=Vss
ICC2	Power Supply Current			2	mA	VCC = 5.0V
	(Operating Read)					FCLK = 10MHz
ISB	Power Supply Current			0	μA	CS = VCC
	(Standby)					VIN = VSS or VCC
ILI	Input Leakage Current			2	μA
ILO	Output Leakage Current			3	μA	VOUT = 0V to VCC,
						CS = 0V
VIL(3)	Input Low Voltage	-1		VCC x 0.3	V
VIH(3)	Input High Voltage	VCC x 0.7		VCC + 0.5	V
VOL1	Output Low Voltage			0.4	V	4.5V≤VCC<5.5V
						IOL = 3.0mA
VOH1	Output High Voltage	VCC - 0.8			V
						IOH = -1.6mA
VOL2	Output Low Voltage			0.2	V	1.8V≤VCC<2.7V
						IOL = 150μA
VOH2	Output High Voltage	VCC-0.2			V
						IOH = -100μA

Note:

(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.

(2)Output shorted for no more than one second. No more than one output shorted at a time.

(3)This parameter is tested initially and after a design or process change that affects the parameter.

(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

Doc. No. 25087-00 8/99 SPI-1	2

Advanced Information

CAT25C32/64

Figure 1. Sychronous Data Timing

VIH

tCS

CS

VIL

tCSS

tCSH

VIH

SCK

tWH

tWL

VIL

tSU

tH

VIH

VALID IN

SI

VIL

tRI

tFI

VOH

tV

tHO

tDIS

HI-Z

HI-Z

SO

VOL

Note: Dashed Line= mode (1, 1) — — — —

A.C. CHARACTERISTICS

Limits

Vcc=

VCC =

VCC =

1.8V-6.0V

2.5V-6.0V

4.5V-5.5V

Test

SYMBOL

PARAMETER

Min.

Max.

Min.

Max.

Min.

Max.

UNITS

Conditions

tSU

Data Setup Time

50

50

20

ns

tH

Data Hold Time

50

50

20

ns

tWH

SCK High Time

250

125

40

ns

tWL

SCK Low Time

250

125

40

ns

fSCK

Clock Frequency

DC

1

DC

3

DC

10

MHz

tLZ

HOLD to Output Low Z

50

50

50

ns

tRI(1)

Input Rise Time

2

2

2

μs

CL = 50pF

tFI(1)

Input Fall Time

2

2

2

μs

tHD

HOLD Setup Time

100

100

40

ns

tCD

HOLD Hold Time

100

100

40

ns

tWC

Write Cycle Time

10

10

5

ms

tV

Output Valid from Clock Low

250

250

80

ns

tHO

Output Hold Time

0

0

0

ns

tDIS

Output Disable Time

250

250

75

ns

tHZ

HOLD to Output High Z

150

100

50

ns

tCS

CS High Time

500

250

200

ns

tCSS

CS Setup Time

500

250

100

ns

tCSH

CS Hold Time

500

250

100

ns

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

3	Doc No. 25087 -00 8/99 SPI-1