CTLST CAT28F102T14I-45T, CAT28F102T14A-90T, CAT28F102T14A-70T, CAT28F102T14A-55T, CAT28F102T14A-45T Datasheet

CAT28F102		Licensed Intel
1 Megabit CMOS Flash Memory		second source

FEATURES

■Fast Read Access Time: 45/55/70/90 ns

■Low Power CMOS Dissipation: –Active: 30 mA max (CMOS/TTL levels)

–Standby: 1 mA max (TTL levels) –Standby: 100μA max (CMOS levels)

■High Speed Programming: –10μs per byte

–1 Sec Typ Chip Program

■0.5 Seconds Typical Chip-Erase

■12.0V ± 5% Programming and Erase Voltage

■Commercial,Industrial and Automotive Temperature Ranges

■64K x 16 Word Organization

■Stop Timer for Program/Erase

■On-Chip Address and Data Latches

■JEDEC Standard Pinouts: –40-pin DIP

–44-pin PLCC –40-pin TSOP

■100,000 Program/Erase Cycles

■10 Year Data Retention

■Electronic Signature

DESCRIPTION

The CAT28F102 is a high speed 64K x 16-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory contents is achieved typically within 0.5 second.

It is pin and Read timing compatible with standard EPROM and E2PROM devices. Programming and Erase are performed through an operation and verify algorithm. The instructions are input via the I/O bus, using a

two write cycle scheme. Address and Data are latched to free the I/O bus and address bus during the write operation.

The CAT28F102 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 40-pin DIP, 44-pin PLCC, or 40-pin TSOP packages.

BLOCK DIAGRAM					I/O0–I/O15
					I/O BUFFERS
		ERASE VOLTAGE
		SWITCH
WE	COMMAND	PROGRAM VOLTAGE		CE, OE LOGIC	DATA	SENSE
	REGISTER	SWITCH			LATCH	AMP
CE
OE		LATCH
					Y-GATING
		ADDRESS	Y-DECODER
A0–A15					1,048,576-BIT
			X-DECODER		MEMORY
					ARRAY
	VOLTAGE VERIFY
	SWITCH

28F101-1

© 1998 by Catalyst Semiconductor, Inc.	Doc. No. 25038-0A 2/98 F-1
Characteristics subject to change without notice	1

CAT28F102

PIN CONFIGURATION

PLCC Package (N)

	13	14	15		CE		PP	NC	CC		WE		15	14
	I/O	I/O	I/O				V		V			NC	A	A
I/O12	7 6	5	4	3		2		1	44 43 42 41 4039						A13
I/O11	8													38	A12
I/O10	9													37	A11
I/O9	10													36	A10
I/O8	11													35	A9
VSS	12													34	VSS
NC	13													33	NC
I/O7	14													32	A8
I/O6	15													31	A7
I/O5	16													30	A6
I/O4	17													29	A5
	18 19 20 21 22 23 24 25 26 27 28
	3	2	1	0			OE	NC	0	1		2	3	4
	I/O	I/O	I/O		I/O				A		A	A	A	A
													28F101-2

DIP Package (P)

VPP		1	40	VCC
	CE	2	39	WE
I/O15		3	38	NC
I/O14		4	37	A15
I/O13		5	36	A14
I/O12		6	35	A13
I/O11		7	34	A12
I/O10		8	33	A11
I/O9		9	32	A10
I/O8		10	31	A9
VSS		11	30	VSS
I/O7		12	29	A8
I/O6		13	28	A7
I/O5		14	27	A6
I/O4		15	26	A5
I/O3		16	25	A4
I/O2		17	24	A3
I/O1		18	23	A2
I/O0		19	22	A1
	OE	20	21	A0

PIN FUNCTIONS

Pin Name			Type	Function
	A0–A15		Input	Address Inputs for
				memory addressing
	I/O0–I/O15		I/O	Data Input/Output
			Input	Chip Enable
	CE
			Input	Output Enable
	OE
			Input	Write Enable
	WE
	VCC			Voltage Supply
	VSS			Ground
	VPP			Program/Erase
				Voltage Supply
	NC			No Connect

TSOP Package (T14)

	A9						1	40			VSS
A10							2	39			A8
A11							3	38			A7
A12							4	37			A6
A13							5	36			A5
A14							6	35			A4
A15							7	34			A3
	NC						8	33			A2
	WE						9	32			A1
VCC							10	31			A0
VPP							11	30				OE
	CE						12	29			I/O0
I/O15							13	28			I/O1
I/O14							14	27			I/O2
I/O13							15	26			I/O3
I/O12							16	25			I/O4
I/O11						17		24			I/O5
I/O10						18		23			I/O6
I/O9						19		22			I/O7
I/O8						20		21			VSS
										28F101-3

Reverse TSOP Package (T14R)

A0					1	40			OE
A1					2	39			I/O0
A2					3	38			I/O1
A3					4	37			I/O2
A4					5	36			I/O3
A5					6	35			I/O4
A6					7	34			I/O5
A7					8	33			I/O6
A8					9	32			I/O7
GND					10	31			GND
A9					11	30			I/O8
A10					12	29			I/O9
A11					13	28			I/O10
A12					14	27			I/O11
A13					15	26			I/O12
A14					16	25			I/O13
A15				17		24			I/O14
NC				18		23			I/O15
WE				19		22			VPP
VCC				20		21			CE

28F102 TSOP2

Doc. No. 25038-0A 2/98 F-1	2

CAT28F102

ABSOLUTE MAXIMUM RATINGS*

*COMMENT

Temperature Under Bias ...................	–55°C to +95°C
Storage Temperature .......................	–65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ...........	–0.6V to +VCC + 2.0V
Voltage on Pin A9 with
Respect to Ground(1) ...................	–2.0V to +13.5V
VPP with Respect to Ground
during Program/Erase(1) ..............	–0.6V to +14.0V
VCC with Respect to Ground(1) ............		–2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ..................................		1.0 W
Lead Soldering Temperature (10 secs)		............ 300°C
Output Short Circuit Current(2) ........................		100 mA

RELIABILITY CHARACTERISTICS

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

Symbol	Parameter	Min.	Max.	Units	Test Method
NEND(3)	Endurance	100K		Cycles/Byte	MIL-STD-883, Test Method 1033
TDR(3)	Data Retention	10		Years	MIL-STD-883, Test Method 1008
VZAP(3)	ESD Susceptibility	2000		Volts	MIL-STD-883, Test Method 3015
ILTH(3)(4)	Latch-Up	100		mA	JEDEC Standard 17

CAPACITANCE TA = 25°C, f = 1.0 MHz

			Limits
Symbol	Test	Min		Max.	Units	Conditions
CIN(3)	Input Pin Capacitance			6	pF	VIN = 0V
COUT(3)	Output Pin Capacitance			10	pF	VOUT = 0V
CVPP(3)	VPP Supply Capacitance			25	pF	VPP = 0V

Note:

(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.

(2)Output shorted for no more than one second. No more than one output shorted at a time.

(3)This parameter is tested initially and after a design or process change that affects the parameter.

(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

3	Doc. No. 25038-0A 2/98 F-1

CAT28F102

D.C. OPERATING CHARACTERISTICS

VCC = +5V ±10%, unless otherwise specified

Limits

Symbol

Parameter

Min.

Max.

Unit

Test Conditions

ILI

Input Leakage Current

±1

μA

VIN = VCC or VSS

VCC = 5.5V,

OE

= VIH

ILO

Output Leakage Current

±1

μA

VOUT = VCC or VSS,

VCC = 5.5V, OE = VIH

ISB1

VCC Standby Current CMOS

100

μA

= VCC ±0.5V,

CE

VCC = 5.5V

ISB2

VCC Standby Current TTL

1

mA

= VIH, VCC = 5.5V

CE

ICC1

VCC Active Read Current

50

mA

VCC = 5.5V,

= VIL,

CE

IOUT = 0mA, f = 6 MHz

ICC2(1)

VCC Programming Current

30

mA

VCC = 5.5V,

Programming in Progress

ICC3(1)

VCC Erase Current

30

mA

VCC = 5.5V,

Erasure in Progress

ICC4(1)

VCC Prog./Erase Verify Current

30

mA

VCC = 5.5V, Program or

Erase Verify in Progress

IPPS

VPP Standby Current

±10

μA

VPP = VPPL

IPP1

VPP Read Current

100

μA

VPP = VPPH

IPP2(1)

VPP Programming Current

50

mA

VPP = VPPH,

Programming in Progress

IPP3(1)

VPP Erase Current

30

mA

VPP = VPPH,

Erasure in Progress

IPP4(1)

VPP Prog./Erase Verify Current

5

mA

VPP = VPPH, Program or

Erase Verify in Progress

VIL

Input Low Level TTL

–0.5

0.8

V

VILC

Input Low Level CMOS

–0.5

0.8

V

VOL

Output Low Level

0.45

V

IOL = 5.8mA, VCC = 4.5V

VIH

Input High Level TTL

2

VCC+0.5

V

VIHC

Input High Level CMOS

VCC*0.7

VCC+0.5

V

VOH1

Output High Level TTL

2.4

V

IOH = –2.5mA, VCC = 4.5V

VOH2

Output High Level CMOS

VCC-0.4

V

IOH = –400μA, VCC = 4.5V

VID

A9 Signature Voltage

11.4

13.0

V

A9 = VID

IID(1)

A9 Signature Current

200

μA

A9 = VID

VLO

VCC Erase/Prog. Lockout Voltage

2.5

V

Supply Characteristics

VCC

VCC Supply Voltage

4.5

5.5

V

28F102-70, 90

VCC

VCC Supply Voltage

4.75

5.25

V

28F102-55, -45

VPPL

VPP During Read Operations

0

6.5

V

VPPH

VPP During Read/Erase/Program

11.4

12.6

V

Doc. No. 25038-0A 2/98 F-1	4

CAT28F102

A.C. CHARACTERISTICS, Read Operation

VCC = +5V ±10%, unless otherwise specified

JEDEC	Standard			28F102-45(7)		28F102-55(7)		28F102-70 (7)		28F10290 (8)
				Vcc=5V+5%		Vcc=5V+5%
Symbol	Symbol	Parameter		Min.	Max.	Min.	Max.	Min.	Max.	Min.	Max	Unit
tAVAV	tRC	Read Cycle Time		45		55		70		90		ns
tELQV	tCE	CE Access Time			45		55		70		90	ns
tAVQV	tACC	Address Access Time			45		55		70		90	ns
tGLQV	tOE	OE Access Time			20		25		28		35	ns
tAXQX	tOH	Output Hold from Address		0		0		0		0		ns
		OE/CE Chan
tGLQX	tOLZ(1)(6)	OE to Output in Low-Z		0		0		0		0		ns
tELQX	tLZ(1)(6)	CE to Output in Low-Z		0		0		0		0		ns
tGHQZ	tDF(1)(2)	OE High to Output High-Z			15		15		18		20	ns
tEHQZ(1)(2)	-	CE High to Output High-Z			15		15		25		30	ns
tWHGL		Write Recovery Time Before		6		6		6		6		μs
		Read

Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5)

2.4 V

									2.0 V
INPUT PULSE LEVELS										REFERENCE POINTS
0.45 V									0.8 V
											5108 FHD F03
Figure 2. A.C. Testing Load Circuit (example)			1.3V
									1N914
									3.3K
	DEVICE									OUT
	UNDER
	TEST								CL = 100 pF
											5108 FHD F04
										CL INCLUDES JIG CAPACITANCE

Figure 3. High Speed A.C. Testing Input/Output Waveform(3)(4)(5)

23V.4 V

		2.0 V
INPUT PULSE LEVELS		1.5V	REFERENCE POINTS
		0.8 V

0.045.0 V

Figure 4. High Speed A.C. Testing Load Circuit (example)

1.3V

1N914

3.3K

DEVICE

OUT

UNDER

TEST

CL =

1003

pF

Note:

CL INCLUDES JIG CAPACITANCE

(1)This parameter is tested initially and after a design or process change that affects the parameter.

(2)Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.

(3)Input Rise and Fall Times (10% to 90%) < 10 ns.

(4)Input Pulse Levels = 0.45V and 2.4V. For high speed input pulse levels 0.0V and 3.0V.

(5)Input and Output Timing Reference = 0.8V and 2.0V. For high speed input and output timing reference=1.5V.

(6)Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.

(7)For Load and Reference Points see Figures 3 and 4

(8)For Load and Reference Points see Figures 1 and 2

5	Doc. No. 25038-0A 2/98 F-1