CTLST CAT28LV256T13I-30T, CAT28LV256T13I-25T, CAT28LV256T13I-20T, CAT28LV256T13A-30T, CAT28LV256T13A-25T Datasheet
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CAT28LV256
256K-Bit CMOS PARALLEL E2PROM
FEATURES
■ 3.0V to 3.6V Supply |
■ CMOS and TTL Compatible I/O |
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■ Read Access Times: 200/250/300 ns |
■ Automatic Page Write Operation: |
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■ Low Power CMOS Dissipation: |
– 1 to 64 Bytes in 10ms |
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– Page Load Timer |
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– Active: 15 mA Max. |
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– Standby: 150 A Max. |
■ End of Write Detection: |
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■ Simple Write Operation: |
– Toggle Bit |
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– DATA Polling |
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– On-Chip Address and Data Latches |
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■ Hardware and Software Write Protection |
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– Self-Timed Write Cycle with Auto-Clear |
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■ Fast Write Cycle Time: |
■ 100,000 Program/Erase Cycles |
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– 10ms Max. |
■ 100 Year Data Retention |
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■ Commercial, Industrial and Automotive |
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Temperature Ranges |
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DESCRIPTION
The CAT28LV256 is a fast, low power, low voltage CMOS Parallel E2PROM organized as 32K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28LV256 features hardware and software write protection.
The CAT28LV256 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC– approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC packages.
BLOCK DIAGRAM |
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A6–A14 |
ADDR. BUFFER |
ROW |
32,768 x 8 |
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& LATCHES |
DECODER |
E2PROM |
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ARRAY |
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VCC |
INADVERTENT |
HIGH VOLTAGE |
64 BYTE PAGE |
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WRITE |
GENERATOR |
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REGISTER |
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PROTECTION |
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CE |
CONTROL |
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OE |
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WE |
LOGIC |
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I/O BUFFERS |
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DATA POLLING |
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TIMER |
AND |
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TOGGLE BIT |
I/O0–I/O7 |
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A0–A5 |
ADDR. BUFFER |
COLUMN |
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DECODER |
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28LV256 F01 |
© 2001 by Catalyst Semiconductor, Inc. |
Doc. No. 25040-00 4/01 P-1 |
Characteristics subject to change without notice |
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CAT28LV256
PIN CONFIGURATION
DIP Package (P)
A14 |
1 |
28 |
VCC |
A12 |
2 |
27 |
WE |
A7 |
3 |
26 |
A13 |
A6 |
4 |
25 |
A8 |
A5 |
5 |
24 |
A9 |
A4 |
6 |
23 |
A11 |
A3 |
7 |
22 |
OE |
A2 |
8 |
21 |
A10 |
A1 |
9 |
20 |
CE |
A0 |
10 |
19 |
I/O7 |
I/O0 |
11 |
18 |
I/O6 |
I/O1 |
12 |
17 |
I/O5 |
I/O2 |
13 |
16 |
I/O4 |
VSS |
14 |
15 |
I/O3 |
PLCC Package (N)
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7 |
12 |
14 |
NC |
CC |
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WE |
13 |
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A |
A |
A |
V |
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A |
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4 |
3 |
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1 |
32 31 30 |
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A6 |
5 |
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29 |
A8 |
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A5 |
6 |
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28 |
A9 |
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A4 |
7 |
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27 |
A11 |
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A3 |
8 |
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26 |
NC |
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A2 |
9 |
TOP VIEW |
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25 |
OE |
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A1 |
10 |
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24 |
A10 |
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A0 |
11 |
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23 |
CE |
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NC |
12 |
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22 |
I/O7 |
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I/O0 |
13 |
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21 |
I/O6 |
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1 |
2 |
SS |
NC |
3 |
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4 |
5 |
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I/O |
I/O |
V |
I/O |
I/O |
I/O |
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28LV256 F02
TSOP Top View (8mm X 13.4mm) (T13)
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OE |
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1 |
28 |
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A10 |
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A11 |
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2 |
27 |
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CE |
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A9 |
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3 |
26 |
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I/O7 |
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A8 |
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4 |
25 |
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I/O6 |
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A13 |
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5 |
24 |
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I/O5 |
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WE |
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6 |
23 |
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I/O4 |
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VCC |
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7 |
22 |
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I/O3 |
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A14 |
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8 |
21 |
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GND |
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A12 |
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20 |
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I/O2 |
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A7 |
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10 |
19 |
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I/O1 |
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A6 |
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11 |
18 |
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I/O0 |
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A5 |
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12 |
17 |
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A0 |
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A4 |
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16 |
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A1 |
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A3 |
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14 |
15 |
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A2 |
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28LV256 F03
PIN FUNCTIONS
Pin Name |
Function |
Pin Name |
Function |
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A0–A14 |
Address Inputs |
WE |
Write Enable |
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I/O0–I/O7 |
Data Inputs/Outputs |
VCC |
3.0 to 3.6 V Supply |
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CE |
Chip Enable |
VSS |
Ground |
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OE |
Output Enable |
NC |
No Connect |
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Doc. No. 25040-00 4/01 P-1 |
2 |
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CAT28LV256
ABSOLUTE MAXIMUM RATINGS* |
*COMMENT |
Temperature Under Bias ................. |
–55° C to +125° C |
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Storage Temperature ....................... |
–65° C to +150° C |
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Voltage on Any Pin with |
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Respect to Ground(2) ........... |
–2.0V to +VCC + 2.0V |
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VCC with Respect to Ground ............... |
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–2.0V to +7.0V |
Package Power Dissipation |
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Capability (Ta = 25° C)................................... |
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1.0W |
Lead Soldering Temperature (10 secs) |
............ 300° C |
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Output Short Circuit Current(3) ........................ |
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100 mA |
RELIABILITY CHARACTERISTICS
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Symbol |
Parameter |
Min. |
Max. |
Units |
Test Method |
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NEND(1) |
Endurance |
100,000 |
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Cycles/Byte |
MIL-STD-883, Test Method 1033 |
TDR(1) |
Data Retention |
100 |
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Years |
MIL-STD-883, Test Method 1008 |
VZAP(1) |
ESD Susceptibility |
2000 |
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Volts |
MIL-STD-883, Test Method 3015 |
ILTH(1)(4) |
Latch-Up |
100 |
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mA |
JEDEC Standard 17 |
CAPACITANCE TA = 25° C, f = 1.0 MHz
Symbol |
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Test |
Max. |
Units |
Conditions |
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CI/O(1) |
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Input/Output Capacitance |
10 |
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pF |
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VI/O = 0V |
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CIN(1) |
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Input Capacitance |
6 |
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pF |
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VIN = 0V |
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MODE SELECTION |
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Mode |
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CE |
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WE |
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OE |
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I/O |
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Power |
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Read |
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L |
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H |
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L |
DOUT |
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ACTIVE |
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Byte Write |
(WE |
Controlled) |
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L |
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H |
DIN |
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ACTIVE |
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L |
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H |
DIN |
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ACTIVE |
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Byte Write (CE |
Controlled) |
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Standby, and Write Inhibit |
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H |
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X |
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X |
High-Z |
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STANDBY |
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Read and Write Inhibit |
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X |
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H |
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H |
High-Z |
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ACTIVE |
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Note:
(1)This parameter is tested initially and after a design or process change that affects the parameter.
(2)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3)Output shorted for no more than one second. No more than one output shorted at a time.
(4)Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
3 |
Doc. No. 25040-00 4/01 P-1 |
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