CTLST CAT28C65BT13I-15T, CAT28C65BNI-15T, CAT28C65BNA-15T, CAT28C65BNA-12T, CAT28C65BN-15T Datasheet
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CAT28C65B
64K-Bit CMOS PARALLEL E2PROM
FEATURES
■ Fast Read Access Times: |
■ Commercial, Industrial and Automotive |
– 120/150ns |
Temperature Ranges |
■ Low Power CMOS Dissipation: |
■ Automatic Page Write Operation: |
– Active: 25 mA Max. |
– 1 to 32 Bytes in 5ms |
– Standby: 100 A Max. |
– Page Load Timer |
■ Simple Write Operation: |
■ End of Write Detection: |
– On-Chip Address and Data Latches |
– Toggle Bit |
– Self-Timed Write Cycle with Auto-Clear |
– DATA Polling |
■ Fast Write Cycle Time: |
– RDY/BUSY |
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– 5ms Max |
■ 100,000 Program/Erase Cycles |
■ CMOS and TTL Compatible I/O |
■ 100 Year Data Retention |
■ Hardware and Software Write Protection |
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DESCRIPTION
The CAT28C65B is a fast, low power, 5V-only CMOS parallel E2PROM organized as 8K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto-clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling, a RDY/BUSY pin and Toggle status bits signal the start and end of the self-timed write cycle.
Additionally, the CAT28C65B features hardware and software write protection.
The CAT28C65B is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDECapproved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32pin PLCC packages.
BLOCK DIAGRAM
A5–A12
VCC
CE
OE
WE
A0–A4
RDY/BUSY 
ADDR. BUFFER |
ROW |
8,192 x 8 |
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DECODER |
E2PROM |
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ARRAY |
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INADVERTENT |
HIGH VOLTAGE |
32 BYTE PAGE |
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WRITE |
GENERATOR |
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REGISTER |
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PROTECTION |
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CONTROL |
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LOGIC |
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I/O BUFFERS |
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DATA POLLING, |
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TIMER |
TOGGLE BIT & |
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RDY/BUSY LOGIC |
I/O0–I/O7 |
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ADDR. BUFFER |
COLUMN |
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& LATCHES |
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DECODER |
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5099 FHD F02 |
© 1999 by Catalyst Semiconductor, Inc. |
Doc. No. 25036-00 2/98 P-1 |
Characteristics subject to change without notice |
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CAT28C65B
PIN CONFIGURATION
DIP Package (P)
RDY/BUSY |
1 |
28 |
VCC |
A12 |
2 |
27 |
WE |
A7 |
3 |
26 |
NC |
A6 |
4 |
25 |
A8 |
A5 |
5 |
24 |
A9 |
A4 |
6 |
23 |
A11 |
A3 |
7 |
22 |
OE |
A2 |
8 |
21 |
A10 |
A1 |
9 |
20 |
CE |
A0 |
10 |
19 |
I/O7 |
I/O0 |
11 |
18 |
I/O6 |
I/O1 |
12 |
17 |
I/O5 |
I/O2 |
13 |
16 |
I/O4 |
VSS |
14 |
15 |
I/O3 |
PLCC Package (N)
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A |
A |
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RDY/BUSY |
NC |
V |
WE |
NC |
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12 |
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CC |
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1 |
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A6 |
5 |
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29 |
A8 |
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A5 |
6 |
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28 |
A9 |
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A4 |
7 |
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27 |
A11 |
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A3 |
8 |
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26 |
NC |
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A2 |
9 |
TOP VIEW |
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25 |
OE |
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A1 |
10 |
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24 |
A10 |
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A0 |
11 |
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23 |
CE |
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NC |
12 |
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22 |
I/O7 |
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I/O0 |
13 |
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21 |
I/O6 |
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2 |
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SS |
NC |
3 |
4 |
5 |
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I/O |
I/O |
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V |
I/O |
I/O |
I/O |
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SOIC Package (J, K)
RDY/BUSY |
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1 |
28 |
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VCC |
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A12 |
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27 |
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WE |
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A7 |
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3 |
26 |
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NC |
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A6 |
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4 |
25 |
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A8 |
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A5 |
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5 |
24 |
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A9 |
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A4 |
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6 |
23 |
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A11 |
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A3 |
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22 |
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OE |
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A2 |
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8 |
21 |
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A10 |
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A1 |
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20 |
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CE |
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A0 |
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10 |
19 |
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I/O7 |
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I/O0 |
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I/O6 |
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I/O1 |
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12 |
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I/O5 |
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I/O2 |
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13 |
16 |
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I/O4 |
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VSS |
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14 |
15 |
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I/O3 |
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TSOP Package (8mm x 13.4mm) (T13)
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OE |
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1 |
28 |
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A10 |
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A11 |
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2 |
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CE |
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A9 |
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3 |
26 |
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I/O7 |
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A8 |
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4 |
25 |
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I/O6 |
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NC |
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5 |
24 |
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I/O5 |
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WE |
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6 |
23 |
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I/O4 |
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VCC |
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7 |
22 |
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I/O3 |
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RDY/BUSY |
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8 |
21 |
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GND |
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A12 |
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20 |
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I/O2 |
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A7 |
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10 |
19 |
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I/O1 |
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A6 |
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11 |
18 |
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I/O0 |
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A5 |
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12 |
17 |
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A0 |
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A4 |
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13 |
16 |
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A1 |
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A3 |
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14 |
15 |
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A2 |
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28C65B F03
PIN FUNCTIONS
Pin Name |
Function |
Pin Name |
Function |
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A0–A12 |
Address Inputs |
WE |
Write Enable |
I/O0–I/O7 |
Data Inputs/Outputs |
VCC |
5 V Supply |
CE |
Chip Enable |
VSS |
Ground |
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OE |
Output Enable |
NC |
No Connect |
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RDY/BSY |
Ready/Busy Status |
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Doc. No. 25036-00 2/98 P-1 |
2 |
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CAT28C65B
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. |
–55° C to +125° C |
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Storage Temperature ....................... |
–65° C to +150° C |
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Voltage on Any Pin with |
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Respect to Ground(2) ........... |
–2.0V to +VCC + 2.0V |
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VCC with Respect to Ground ............... |
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–2.0V to +7.0V |
Package Power Dissipation |
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Capability (Ta = 25° C)................................... |
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1.0W |
Lead Soldering Temperature (10 secs) |
............ 300° C |
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Output Short Circuit Current(3) ........................ |
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100 mA |
RELIABILITY CHARACTERISTICS
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Symbol |
Parameter |
Min. |
Max. |
Units |
Test Method |
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NEND(1) |
Endurance |
105 |
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Cycles/Byte |
MIL-STD-883, Test Method 1033 |
TDR(1) |
Data Retention |
100 |
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Years |
MIL-STD-883, Test Method 1008 |
VZAP(1) |
ESD Susceptibility |
2000 |
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Volts |
MIL-STD-883, Test Method 3015 |
ILTH(1)(4) |
Latch-Up |
100 |
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mA |
JEDEC Standard 17 |
MODE SELECTION
Mode |
CE |
WE |
OE |
I/O |
Power |
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Read |
L |
H |
L |
DOUT |
ACTIVE |
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Byte Write |
(WE |
Controlled) |
L |
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H |
DIN |
ACTIVE |
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Byte Write |
(CE |
Controlled) |
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L |
H |
DIN |
ACTIVE |
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Standby, and Write Inhibit |
H |
X |
X |
High-Z |
STANDBY |
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Read and Write Inhibit |
X |
H |
H |
High-Z |
ACTIVE |
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CAPACITANCE TA = 25° C, F = 1.0 MHZ, VCC = 5V
Symbol |
Test |
Max. |
Units |
Conditions |
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CI/O(1) |
Input/Output Capacitance |
10 |
pF |
VI/O = 0V |
CIN(1) |
Input Capacitance |
6 |
pF |
VIN = 0V |
Note:
(1)This parameter is tested initially and after a design or process change that affects the parameter.
(2)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3)Output shorted for no more than one second. No more than one output shorted at a time.
(4)Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.
3 |
Doc. No. 25036-00 2/98 |
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CAT28C65B
D.C. OPERATING CHARACTERISTICS
VCC = 5V ± 10%, unless otherwise specified.
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Limits |
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Symbol |
Parameter |
Min. |
Typ. |
Max. |
Units |
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Test Conditions |
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ICC |
VCC Current (Operating, TTL) |
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30 |
mA |
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= VIL, |
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CE |
OE |
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f = 1/tRC min, All I/O’s Open |
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ICCC(1) |
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VCC Current (Operating, CMOS) |
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25 |
mA |
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CE = OE = VILC, |
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f = 1/tRC min, All I/O’s Open |
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ISB |
VCC Current (Standby, TTL) |
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1 |
mA |
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= VIH, All I/O’s Open |
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CE |
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ISBC(2) |
VCC Current (Standby, CMOS) |
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100 |
A |
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= VIHC, |
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CE |
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All I/O’s Open |
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ILI |
Input Leakage Current |
–10 |
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10 |
A |
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VIN = GND to VCC |
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ILO |
Output Leakage Current |
–10 |
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10 |
A |
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VOUT = GND to VCC, |
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CE |
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VIH(2) |
High Level Input Voltage |
2 |
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VCC +0.3 |
V |
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VIL(1) |
Low Level Input Voltage |
–0.3 |
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0.8 |
V |
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VOH |
High Level Output Voltage |
2.4 |
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V |
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IOH = –400 A |
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VOL |
Low Level Output Voltage |
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0.4 |
V |
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IOL = 2.1mA |
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VWI |
Write Inhibit Voltage |
3.5 |
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V |
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Note:
(1)VILC = –0.3V to +0.3V.
(2)VIHC = VCC –0.3V to VCC +0.3V.
Doc. No. 25036-00 2/98 P-1 |
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