CTLST CAT28F002T-90TT, CAT28F002T-90BT, CAT28F002T-15TT, CAT28F002T-15BT, CAT28F002T-12TT Datasheet
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CAT28F002 |
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Licensed Intel |
2 Megabit CMOS Boot Block Flash Memory |
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second source |
FEATURES
■Fast Read Access Time: 90/120/150 ns
■On-Chip Address and Data Latches
■Blocked Architecture:
—One 16-KB Protected Boot Block
•Top or Bottom Locations
—Two 8-KB Parameter Blocks
—One 96-KB Main Block
—One 128-KB Main Block
■Hardware Data Protection
■Automated Program and Erase Algorithms
■Automatic Power Savings Feature
■Low Power CMOS Operation
■12.0V ± 5% Programming and Erase Voltage
■Electronic Signature
■100,000 Program/Erase Cycles and 10 Year Data Retention
■Standard Pinouts:
—40-Lead TSOP
—40-Lead PDIP
■High Speed Programming
■Commercial, Industrial and Automotive Temperature Ranges
■Reset/Deep PowerDown Mode
—0.2 μA ICC Typical
—Acts as Reset for Boot Operations
DESCRIPTION
The CAT28F002 is a high speed 256K X 8-bit electrically erasable and reprogrammable Flash memory ideally suited for applications requiring in-system or after sale code updates.
The CAT28F002 has a blocked architecture with one 16 KB Boot Block, two 8 KB Parameter Blocks, one 96 KB Main Block and one 128 KB Main Block. The Boot Block section can be at the top or bottom of the memory map. The Boot Block section includes a reprogramming write lock out feature to guarantee data integrity. It is designed to contain secure code which will bring up the system minimally and download code to other locations of CAT28F002.
The CAT28F002 is designed with a signature mode which allows the user to identify the IC manufacturer and device type. The CAT28F002 is also designed with onChip Address Latches, Data Latches, Programming and Erase Algorithms. A deep power-down mode lowers the total Vcc power consumption 1μw typical.
The CAT28F002 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 10 years. The device is available in JEDEC approved 40-pin TSOP and 40-pin PDIP packages.
BLOCK DIAGRAM |
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I/O0–I/O7 |
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ADDRESS |
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COUNTER |
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I/O BUFFERS |
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WRITE STATE |
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ERASE VOLTAGE |
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MACHINE |
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SWITCH |
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RP |
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STATUS |
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REGISTER |
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WE |
COMMAND |
PROGRAM VOLTAGE |
CE, OE LOGIC |
DATA |
SENSE |
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REGISTER |
SWITCH |
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LATCH |
AMP |
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CE |
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COMPARATOR |
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OE |
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LATCH |
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16K-BYTE BOOT BLOCK |
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Y-GATING |
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ADDRESS |
Y-DECODER |
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A0–A17 |
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128K-BYTE MAIN BLOCK |
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8K-BYTE PARAMETER BLOCK |
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8K-BYTE PARAMETER BLOCK |
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VOLTAGE VERIFY |
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X-DECODER |
96K-BYTE MAIN BLOCK |
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SWITCH |
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28F002 F01 |
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© 1998 |
by Catalyst Semiconductor, Inc. |
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1 |
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Doc. No. 25072-00 2/98 |
F-1 |
Characteristics subject to change without notice |
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CAT28F002
PIN CONFIGURATION
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PDIP Package (P) |
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TSOP Package (T) |
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NC |
1 |
40 |
NC |
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NC |
2 |
39 |
A1 |
A16 |
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1 |
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A0 |
3 |
38 |
A2 |
A15 |
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2 |
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4 |
37 |
A3 |
A14 |
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3 |
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CE |
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GND |
5 |
36 |
A4 |
A13 |
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4 |
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A12 |
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5 |
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OE |
6 |
35 |
A5 |
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A11 |
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6 |
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I/O0 |
7 |
34 |
A6 |
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A9 |
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7 |
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8 |
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I/O1 |
33 |
A7 |
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A8 |
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8 |
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I/O2 |
9 |
32 |
VPP |
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WE |
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9 |
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10 |
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RP |
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10 |
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I/O3 |
31 |
RP |
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VPP |
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11 |
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VCC |
11 |
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30 |
WE |
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DU |
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12 |
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VCC |
12 |
29 |
A8 |
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NC |
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13 |
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I/O4 |
13 |
28 |
A9 |
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A7 |
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14 |
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I/O5 |
14 |
27 |
A11 |
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A6 |
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15 |
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I/O6 |
15 |
26 |
A12 |
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A5 |
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16 |
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A4 |
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17 |
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I/O7 |
16 |
25 |
A13 |
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A3 |
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18 |
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A10 |
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24 |
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17 |
A14 |
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A2 |
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19 |
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GND |
18 |
23 |
A15 |
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A1 |
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20 |
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A17 |
19 |
22 |
A16 |
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NC |
20 |
21 |
NC |
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PIN FUNCTIONS
Pin Name |
Type |
Function |
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A0–A17 |
Input |
Address Inputs for |
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memory addressing |
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I/O0–I/O7 |
I/O |
Data Input/Output |
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CE |
Input |
Chip Enable |
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OE |
Input |
Output Enable |
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WE |
Input |
Write Enable |
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VCC |
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Voltage Supply |
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VSS |
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Ground |
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VPP |
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Program/Erase |
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Voltage Supply |
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Input |
Power Down |
RP |
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DU |
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Do Not Use |
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40 
A17
39 
GND
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NC
37 
NC
36 
A10
35 
I/O7
34 
I/O6
33 
I/O5
32 
I/O4
31 
VCC
30 
VCC
29 
NC
28 
I/O3
27 
I/O2
26 
I/O1
25 
I/O0
24 
OE
23 
GND
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CE
21 
A0
28F002 F03
Doc. No. 25072-00 2/98 F-1 |
2 |
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CAT28F002
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................... |
–55°C to +95°C |
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Storage Temperature ....................... |
–65°C to +150°C |
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Voltage on Any Pin with |
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Respect to Ground(1) ........... |
–2.0V to +VCC + 2.0V |
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Voltage on Pin A9 with |
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Respect to Ground(1) ................... |
–2.0V to +13.5V |
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VPP with Respect to Ground |
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during Program/Erase(1) .............. |
–2.0V to +14.0V |
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VCC with Respect to Ground(1) ............ |
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–2.0V to +7.0V |
Package Power Dissipation |
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Capability (TA = 25°C) .................................. |
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1.0 W |
Lead Soldering Temperature (10 secs) |
............ 300°C |
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Output Short Circuit Current(2) ........................ |
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100 mA |
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS
Symbol |
Parameter |
Min. |
Max. |
Units |
Test Method |
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NEND(3) |
Endurance |
100K |
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Cycles/Byte |
MIL-STD-883, Test Method 1033 |
TDR(3) |
Data Retention |
10 |
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Years |
MIL-STD-883, Test Method 1008 |
VZAP(3) |
ESD Susceptibility |
2000 |
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Volts |
MIL-STD-883, Test Method 3015 |
ILTH(3)(4) |
Latch-Up |
100 |
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mA |
JEDEC Standard 17 |
CAPACITANCE TA = 25°C, f = 1.0 MHz
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Limits |
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Symbol |
Test |
Min |
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Max. |
Units |
Conditions |
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CIN(3) |
Input Pin Capacitance |
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8 |
pF |
VIN = 0V |
COUT(3) |
Output Pin Capacitance |
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12 |
pF |
VOUT = 0V |
CVPP(3) |
VPP Supply Capacitance |
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25 |
pF |
VPP = 0V |
Note:
(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2)Output shorted for no more than one second. No more than one output shorted at a time.
(3)This parameter is tested initially and after a design or process change that affects the parameter.
(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
3 |
Doc. No. 25072-00 2/98 F-1 |
CAT28F002
D.C. OPERATING CHARACTERISTICS
VCC = +5V ±10%, unless otherwise specified
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Limits |
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Symbol |
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Parameter |
Min. |
Max. |
Unit |
Test Conditions |
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ILI |
Input Leakage Current |
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±1.0 |
μA |
VIN = VCC or VSS |
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VCC = 5.5V |
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ILO |
Output Leakage Current |
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±10 |
μA |
VOUT = VCC or VSS, |
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VCC = 5.5V |
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ISB1 |
VCC Standby Current CMOS |
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100 |
μA |
CE = VCC ±0.2V = RP |
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VCC = 5.5V |
ISB2 |
VCC Standby Current TTL |
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1.5 |
mA |
CE = RP = VIH, VCC = 5.5V |
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IPPD |
VPP Deep Powerdown Current |
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5.0 |
μA |
RP = GND±0.2V |
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ICC1 |
VCC Active Read Current |
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55 |
mA |
VCC = 5.5V, CE = GND, |
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IOUT = 0mA, f = 10 MHz |
ICC2(1) |
VCC Programming Current |
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50 |
mA |
VCC = 5.5V, |
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Programming in Progress |
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ICC3(1) |
VCC Erase Current |
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30 |
mA |
VCC = 5.5V, |
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Erase in Progress |
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IPPS |
VPP Standby Current |
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±10 |
μA |
VPP < VCC |
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200 |
μA |
VPP > VCC |
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IPP1 |
VPP Read Current |
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200 |
μA |
VPP = VPPH |
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IPP2(1) |
VPP Programming Current |
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20 |
mA |
VPP = VPPH, |
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Programming in Progress |
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IPP3(1) |
VPP Erase Current |
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15 |
mA |
VPP = VPPH, |
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Erase in Progress |
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VIL |
Input Low Level |
–0.5 |
0.8 |
V |
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VOL |
Output Low Level |
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0.45 |
V |
IOL = 5.8mA, VCC = 4.5V |
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VIH |
Input High Level |
2.0 |
VCC+0.5 |
V |
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VOH1 |
Output High Level TTL |
2.4 |
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V |
IOH = -2.5mA, VCC = 4.5V |
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VID |
A9 Signature Voltage |
10.8 |
13.2 |
V |
A9 = VID |
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IID |
A9 Signature Current |
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500 |
μA |
A9 = VID |
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ICCD |
VCC Deep Powerdown Current |
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1.0 |
μA |
RP = GND±0.2V |
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ICCES |
VCC Erase Suspend Current |
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10 |
mA |
Erase Suspended CE = VIH |
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IPPES |
VPP Erase Suspend Current |
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200 |
μA |
Erase Suspended VPP=VPPH |
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I |
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Boot Block Unlock Current |
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500 |
μA |
RP = VHH |
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RP |
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RP |
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VOH2 |
Output High Level TTL |
0.85 VCC |
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V |
VCC = VCCMIN |
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IOH = -1.5mA |
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Note: |
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(1) This parameter is tested initially and after a design or process change that affects the parameter. |
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Doc. No. 25072-00 2/98 F-1 |
4 |
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CAT28F002 |
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SUPPLY CHARACTERISTICS |
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Limits |
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Symbol |
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Parameter |
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Min |
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Max. |
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Unit |
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VLKO |
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VCC Erase/Write Lock Voltage |
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2.0 |
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V |
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VCC |
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VCC Supply Voltage |
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4.5 |
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5.5 |
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V |
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VPPL |
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VPP During Read Operations |
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0 |
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6.5 |
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V |
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VPPH |
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VPP During Erase/Program |
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11.4 |
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12.6 |
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V |
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VHH |
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RP, OE Unlock Voltage |
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10.8 |
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13.2 |
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V |
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VPPLK |
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VPP Lock-Out Voltage |
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0 |
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6.5 |
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V |
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A.C. CHARACTERISTICS, Read Operation |
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VCC = +5V ±10%, unless otherwise specified |
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JEDEC |
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Standard |
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28F002-90 |
28F002-12 |
28F002-15 |
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Symbol |
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Symbol |
Parameter |
Min. |
Max. |
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Min. |
Max. |
Min. |
Max. |
Unit |
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tAVAV |
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tRC |
Read Cycle Time |
90 |
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120 |
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150 |
ns |
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tELQV |
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tCE |
CE Access Time |
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90 |
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120 |
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150 |
ns |
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tAVQV |
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tACC |
Address Access Time |
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90 |
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120 |
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150 |
ns |
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tGLQV |
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tOE |
OE Access Time |
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40 |
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40 |
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40 |
ns |
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- |
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tOH |
Output Hold from Address OE/CE Change |
0 |
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0 |
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0 |
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ns |
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tGLQX |
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tOLZ(1)(6) |
OE to Output in Low-Z |
0 |
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0 |
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0 |
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ns |
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tELQX |
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tLZ(1)(6) |
CE to Output in Low-Z |
0 |
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0 |
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0 |
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tGHQZ |
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tDF(1)(2) |
OE High to Output High-Z |
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30 |
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30 |
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30 |
ns |
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tEHQZ |
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tHZ(1)(2) |
CE High to Output High-Z |
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30 |
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30 |
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30 |
ns |
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tPHQV |
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tPWH |
RP High to Output Delay |
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300 |
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300 |
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300 |
ns |
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Figure 1. A.C. Testing Input/Output Waveform(3)(4)(5) |
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2.4 V |
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2.0 V |
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INPUT PULSE LEVELS |
REFERENCE POINTS |
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0.45 V |
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0.8 V |
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5108 FHD F03
Figure 2. A.C. Testing Load Circuit (example)
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1.3V |
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1N914 |
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3.3K |
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DEVICE |
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OUT |
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UNDER |
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TEST |
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CL = 100 pF |
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Note: |
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CL INCLUDES JIG CAPACITANCE |
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5108 FHD F04
(1)This parameter is tested initially and after a design or process change that affects the parameter.
(2)Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3)Input Rise and Fall Times (10% to 90%) < 10 ns.
(4)Input Pulse Levels = 0.45V and 2.4V.
(5)Input and Output Timing Reference = 0.8V and 2.0V.
(6)Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
5 |
Doc. No. 25072-00 2/98 F-1 |
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