Advanced Information
CAT93CXXXX (1K-16K)
Supervisory Circuits with Microwire Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer
FEATURES
■Watchdog Timer
■Programmable Reset Threshold
■Built-in Inadvertent Write Protection —V CC Lock Out
■High Speed Operation: 3MHz
■Low Power CMOS Technology
■x 16 or x 8 Selectable Serial Memory
■Self-Timed Write Cycle with Auto-Clear
■Sequential Read
■Fast Nonvolatile Write Cycle: 3ms Max
■Active High or Low Reset Outputs —Precision Power Supply Voltage Monitoring —5V, 3.3V and 3V options
■Hardware and Software Write Protection
■Power-Up Inadvertant Write Protection
■1,000,000 Program/Erase Cycles
■100 Year Data Retention
■Commercial, Industrial, and Automotive Temperature Ranges
■2.7-6.0 Volt Operation
■16 Byte Page Mode
DESCRIPTION
The CAT93CXXXX is a single chip solution to three popular functions of EEPROM memory, precision reset controller and watchdog timer. The serial EEPROM memory of the 93CXXXX can be configured either by 16bits or by 8-bits. Each register can be written (or read) by using the DI (or DO pin).
The reset function of the 93CXXXX protects the system
during brown out and power up/down conditions. During system failure the watchdog timer feature protects the microcontroller with a reset signal. Catalyst's advanced CMOS technology substantially reduces device power requirements. The 93CXXXX is available in 8-pin DIP, 8- pin TSSOP or 8-pin SOIC packages. It is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years.
PIN CONFIGURATION |
BLOCK DIAGRAM |
93CX61X |
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93CX62X |
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93CX63X |
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CS |
1 |
8 |
VCC |
CS |
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1 |
8 |
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VCC |
CS |
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1 |
8 |
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VCC |
SK |
2 |
7 |
RESET(RESET) SK |
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2 |
7 |
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RESET(RESET) |
SK |
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2 |
7 |
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RESET |
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DI |
3 |
6 |
ORG |
DI |
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3 |
6 |
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WDI |
DI |
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3 |
6 |
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RESET |
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DO |
4 |
5 |
GND |
DO |
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4 |
5 |
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GND |
DO |
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4 |
5 |
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GND |
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PIN FUNCTIONS
Pin Name |
Function |
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CS |
Chip Select |
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RESET/RESET |
Reset I/O |
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SK |
Clock Input |
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DI |
Serial Data Input |
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DO |
Serial Data Output |
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VCC |
+2.7 to 6.0V Power Supply |
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GND |
Ground |
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ORG |
Memory Organization |
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Note: When the ORG pin is connected to VCC, the X16 organiza tion is selected. When it is connected to ground, the X8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the X16 organization.
ORG
DI
CS
SK
VCC |
GND |
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MEMORY ARRAY |
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ADDRESS |
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DECODER |
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DATA
REGISTER
OUTPUT
BUFFER
MODE DECODE
LOGIC
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CLOCK |
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DO |
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GENERATOR |
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RESET Controller |
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High |
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WATCHDOG |
Precision |
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Vcc Monitor |
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WDI RESET/RESET
© 1998 by Catalyst Semiconductor, Inc. |
9-85 |
Characteristics subject to change without notice |
CAT93CXXXX |
Advanced Information |
ABSOLUTE MAXIMUM RATINGS* |
COMMENT |
Temperature Under Bias.................... |
–55°C to +125°C |
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Storage Temperature........................ |
–65°C to +150°C |
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Voltage on Any Pin with |
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Respect to Ground(1) .............. |
–2.0V to +VCC + 2.0V |
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VCC with Respect to Ground.................. |
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–2.0V to +7.0V |
Package Power Dissipation |
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Capability (Ta = 25°C)1.0W................................. |
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1.0W |
Lead Soldering Temperature (10 secs) |
...............300°C |
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Output Short Circuit Current(2) .......................... |
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100mA |
D.C. OPERATING CHARACTERISTICS
VCC = +2.7V to +6.0V, unless otherwise specified.
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
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Limits |
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Symbol |
Parameter |
Min. |
Typ. |
Max. |
Units |
Test Conditions |
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ICC1 |
Power Supply Current |
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3 |
mA |
fSK = 1MHz |
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(Write) |
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VCC = 5.0V |
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ICC2 |
Power Supply Current |
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1 |
mA |
fSK = 1MHz |
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(Read) |
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VCC = 5.0V |
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ISB1 |
Power Supply Current |
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10 |
μA |
CS = 0V |
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(Standby) (x8 Mode) |
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ORG=GND |
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ISB2 |
Power Supply Current |
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0 |
μA |
CS=0V |
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(Standby) (x16Mode) |
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ORG=Float or VCC |
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ILI |
Input Leakage Current |
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1 |
μA |
VIN = 0V to VCC |
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ILO |
Output Leakage Current |
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1 |
μA |
VOUT = 0V to VCC, |
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(Including ORG pin) |
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CS = 0V |
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VIL1 |
Input Low Voltage |
-0.1 |
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0.8 |
V |
4.5V≤VCC<5.5V |
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VIH1 |
Input High Voltage |
2 |
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VCC+1 |
V |
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VOL1 |
Output Low Voltage |
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0.4 |
V |
4.5V≤VCC<5.5V |
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VOH1 |
Output High Voltage |
2.4 |
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IOL = 2.1mA |
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V |
IOH = -400μA |
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Note:
(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2)Output shorted for no more than one second. No more than one output shorted at a time.
Stock No. 21084-01 2/98 |
9-86 |
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Advanced Information CAT93CXXXX
RELIABILITY CHARACTERISTICS
Symbol |
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Parameter |
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Min. |
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Max. |
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Units |
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Reference Test Method |
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NEND(1) |
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Endurance |
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1,000,000 |
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Cycles/Byte |
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MIL-STD-883, Test Method 1033 |
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TDR(1) |
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Data Retention |
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100 |
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Years |
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MIL-STD-883, Test Method 1008 |
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VZAP(1) |
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ESD Susceptibility |
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2000 |
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Volts |
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MIL-STD-883, Test Method 3015 |
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ILTH(1)(3) |
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Latch-up |
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100 |
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mA |
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JEDEC Standard 17 |
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A.C. CHARACTERISTICS |
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VCC=2.7V to 6.0V unless otherwise specified. |
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Output Load is 1 TTL Gate and 100pF |
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Limits |
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VCC = |
VCC = |
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2.7V -6V |
4.5V-5.5V |
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Test |
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SYMBOL |
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PARAMETER |
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Min. |
Max. |
Min. |
Max. |
UNITS |
Conditions |
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tCSS |
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CS Setup Time |
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250 |
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50 |
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ns |
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tCSH |
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CS Hold Time |
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0 |
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0 |
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ns |
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tDIS |
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DI Setup Time |
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250 |
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50 |
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ns |
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tDIH |
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DI Hold Time |
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250 |
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50 |
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ns |
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tPD1 |
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Output Delay to 1 |
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0.5 |
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0.1 |
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μs |
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tPD0 |
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Output Delay to 0 |
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0.5 |
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0.1 |
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μs |
CL = 100pF |
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tHZ(1) |
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Output Delay to High-Z |
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500 |
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100 |
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ns |
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tEW |
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Program/Erase Pulse Width |
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5 |
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5 |
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ms |
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tCSMIN |
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Minimum CS Low Time |
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0.5 |
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0.1 |
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μs |
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tSKHI |
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Minimum SK High Time |
0.5 |
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0.1 |
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μs |
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tSKLOW |
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Minimum SK Low Time |
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0.5 |
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0.1 |
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μs |
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tSV |
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Output Delay to Status Valid |
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0.5 |
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0.1 |
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μs |
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SKMAX |
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Maximum Clock Frequency |
DC |
1000 |
DC |
3000 |
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KHZ |
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Power-Up Timing(1)(2)
Symbol |
Parameter |
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Max. |
Units |
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tPUR |
Power-up to Read Operation |
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1 |
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tPUW |
Power-up to Write Operation |
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1 |
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CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V |
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Symbol |
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Test |
Max. |
Units |
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Conditions |
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CI/O(1) |
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Input/Output Capacitance |
8 |
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pF |
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VI/O = 0V |
CIN(1) |
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Input Capacitance |
6 |
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pF |
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VIN = 0V |
Note:
(1)This parameter is tested initially and after a design or process change that affects the parameter.
(2)tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
(3)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
9-87 |
Stock No. 21084-01 2/98 |
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