CTLST CAT24WC256KA-3TE13, CAT24WC256KA-1.8TE13, CAT24WC256K-TE13, CAT24WC256K-3TE13, CAT24WC256K-1.8TE13 Datasheet
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Preliminary
CAT24WC256
256K-Bit I2C Serial CMOS E2PROM
FEATURES
■1MHz I2C Bus Compatible*
■1.8 to 6 Volt Operation
■Low Power CMOS Technology
■64-Byte Page Write Buffer
■Self-Timed Write Cycle with Auto-Clear
■Commercial, Industrial and Automotive Temperature Ranges
■ Write Protect Feature
– Entire Array Protected When WP at V
IH
■100,000 Program/Erase Cycles
■100 Year Data Retention
■8-Pin DIP or 8-Pin SOIC
DESCRIPTION
The CAT24WC256 is a 256K-bit Serial CMOS E2PROM internally organized as 32,768 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The
CAT24WC256 features a 64-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION |
BLOCK DIAGRAM |
DIP Package (P) |
EXTERNAL LOAD |
A0 |
1 |
8 |
VCC |
A1 |
2 |
7 |
WP |
NC |
3 |
6 |
SCL |
VSS |
4 |
5 |
SDA |
SOIC Package (K)
A0 |
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1 |
8 |
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VCC |
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2 |
7 |
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A1 |
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WP |
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3 |
6 |
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NC |
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SCL |
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4 |
5 |
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VSS |
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SDA |
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24WC256 F01 |
PIN FUNCTIONS |
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Pin Name |
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Function |
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A0, A1 |
Address Inputs |
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SDA |
Serial Data/Address |
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SCL |
Serial Clock |
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WP |
Write Protect |
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VCC |
+1.8V to +6.0V Power Supply |
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VSS |
Ground |
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NC |
No Connect |
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DOUT |
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SENSE AMPS |
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SHIFT REGISTERS |
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ACK |
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VCC |
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VSS |
WORD ADDRESS |
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COLUMN |
BUFFERS |
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DECODERS |
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512 |
SDA |
START/STOP |
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LOGIC |
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XDEC |
512 |
E2PROM |
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512X512 |
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WP |
CONTROL |
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LOGIC |
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DATA IN STORAGE |
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HIGH VOLTAGE/
TIMING CONTROL
SCL 
STATE COUNTERS
A0 
SLAVE
A1 
ADDRESS
COMPARATORS
24WC256 F02
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 1998 by Catalyst Semiconductor, Inc. |
Doc. No. 25061-00 6/99 S-1 |
Characteristics subject to change without notice |
1 |
CAT24WC256 |
Preliminary |
ABSOLUTE MAXIMUM RATINGS* |
*COMMENT |
Temperature Under Bias ................. |
–55°C to +125°C |
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Storage Temperature ....................... |
–65°C to +150°C |
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Voltage on Any Pin with |
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Respect to Ground(1) ........... |
–2.0V to +VCC + 2.0V |
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VCC with Respect to Ground ............... |
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–2.0V to +7.0V |
Package Power Dissipation |
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Capability (Ta = 25°C) ................................... |
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1.0W |
Lead Soldering Temperature (10 secs) |
............ 300°C |
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Output Short Circuit Current(2) ........................ |
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100mA |
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
RELIABILITY CHARACTERISTICS
Symbol |
Parameter |
Min. |
Max. |
Units |
Reference Test Method |
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NEND(3) |
Endurance |
100,000 |
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Cycles/Byte |
MIL-STD-883, Test Method 1033 |
TDR(3) |
Data Retention |
100 |
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Years |
MIL-STD-883, Test Method 1008 |
VZAP(3) |
ESD Susceptibility |
2000 |
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Volts |
MIL-STD-883, Test Method 3015 |
ILTH(3)(4) |
Latch-up |
100 |
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mA |
JEDEC Standard 17 |
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
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Limits |
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Symbol |
Parameter |
Min. |
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Typ. |
Max. |
Units |
Test Conditions |
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ICC1 |
Power Supply Current - Read |
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1 |
mA |
fSCL = 100 KHz |
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VCC=5V |
ICC2 |
Power Supply Current - Write |
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3 |
mA |
fSCL = 100KHz |
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VCC=5V |
ISB(5) |
Standby Current |
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0 |
μA |
VIN = GND or VCC |
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VCC=5V |
ILI |
Input Leakage Current |
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1 |
μA |
VIN = GND to VCC |
ILO |
Output Leakage Current |
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1 |
μA |
VOUT = GND to VCC |
VIL |
Input Low Voltage |
–1 |
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VCC x 0.3 |
V |
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VIH |
Input High Voltage |
VCC x 0.7 |
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VCC + 0.5 |
V |
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VOL1 |
Output Low Voltage (VCC = +3.0V) |
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0.4 |
V |
IOL = 3.0 mA |
VOL2 |
Output Low Voltage (VCC = +1.8V) |
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0.5 |
V |
IOL = 1.5 mA |
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol |
Test |
Max. |
Units |
Conditions |
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CI/O(3) |
Input/Output Capacitance (SDA) |
8 |
pF |
VI/O = 0V |
CIN(3) |
Input Capacitance (SCL, WP, A0, A1) |
6 |
pF |
VIN = 0V |
Note:
(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2)Output shorted for no more than one second. No more than one output shorted at a time.
(3)This parameter is tested initially and after a design or process change that affects the parameter.
(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5)Standby current (ISB ) = 0 μA (<900 nA).
Doc. No. 25061-00 6/99 S-1
2
Preliminary |
CAT24WC256 |
A.C. CHARACTERISTICS
VCC = +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol |
Parameter |
VCC=1.8V - 6.0V |
VCC=2.5V - 6.0V |
VCC=3.0V - 5.5V |
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Min. |
Max. |
Min. |
Max. |
Min. |
Max. |
Units |
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FSCL |
Clock Frequency |
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100 |
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400 |
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1000 |
kHz |
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tAA |
SCL Low to SDA Data Out |
0.1 |
3.5 |
0.05 |
0.9 |
0.05 |
0.55 |
μs |
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and ACK Out |
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tBUF(2) |
Time the Bus Must be Free Before |
4.7 |
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1.2 |
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0.5 |
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μs |
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a New Transmission Can Start |
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tHD:STA |
Start Condition Hold Time |
4.0 |
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0.6 |
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0.25 |
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μs |
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tLOW |
Clock Low Period |
4.7 |
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1.2 |
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0.6 |
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μs |
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tHIGH |
Clock High Period |
4.0 |
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0.6 |
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0.4 |
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μs |
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tSU:STA |
Start Condition Setup Time |
4.0 |
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0.6 |
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0.25 |
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μs |
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(for a Repeated Start Condition) |
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tHD:DAT |
Data In Hold Time |
0 |
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0 |
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0 |
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ns |
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tSU:DAT |
Data In Setup Time |
100 |
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100 |
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100 |
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ns |
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tR(2) |
SDA and SCL Rise Time |
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1.0 |
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0.3 |
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0.3 |
μs |
tF(2) |
SDA and SCL Fall Time |
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300 |
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300 |
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100 |
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tSU:STO |
Stop Condition Setup Time |
4.7 |
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0.6 |
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0.25 |
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μs |
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tDH |
Data Out Hold Time |
100 |
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50 |
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50 |
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ns |
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tWR |
Write Cycle Time |
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10 |
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10 |
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5 |
ms |
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Power-Up Timing (2)(3)
Symbol |
Parameter |
Max. |
Units |
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tPUR |
Power-Up to Read Operation |
1 |
ms |
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tPUW |
Power-Up to Write Operation |
1 |
ms |
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Note:
(1)AC measurement conditions:
RL (connects to VCC): 0.3VCC to 0.7 VCC Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 VCC
(2)This parameter is tested initially and after a design or process change that affects the parameter.
(3)tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
3 |
Doc. No. 25061-00 6/99 S-1 |
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