CTLST CAT24WC16PI-TE13, CAT24WC16PI-1.8TE13, CAT24WC16PA-TE13, CAT24WC16PA-1.8TE13, CAT24WC16P-TE13 Datasheet

CAT24WC01/02/04/08/16
1K/2K/4K/8K/16K-Bit Serial E2PROM
FEATURES	■ Self-Timed Write Cycle with Auto-Clear
■ 400 KHZ I2C Bus Compatible*	■ 1,000,000 Program/Erase Cycles
■ 1.8 to 6.0Volt Operation	■ 100 Year Data Retention
■ Low Power CMOS Technology	■ 8-pin DIP, 8-pin SOIC or 8 pin TSSOP
■ Write Protect Feature	■ Commercial, Industrial and Automotive
— Entire Array Protected When WP at VIH		Temperature Ranges
■ Page Write Buffer

DESCRIPTION

The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16Kbit Serial CMOS E2PROM internally organized as 128/ 256/512/1024/2048 words of 8 bits each. Catalyst’s advanced CMOS technology substantially reduces device power requirements. The the CAT24WC01/02/04/

08/16 feature a 16-byte page write buffer. The device operates via the I2C bus serial interface, has a special write protection feature, and is available in 8-pin DIP, 8- pin SOIC or 8-pin TSSOP.

PIN CONFIGURATION

DIP Package (P)							SOIC Package (J)
A0	1	8				VCC	A0							1					8				VCC
	2	7												2					7
A1						WP	A1																WP
	3	6												3					6
A2						SCL	A2																SCL
	4	5												4					5
VSS						SDA	VSS																SDA
																				5020 FHD F01
						TSSOP Package (U)
		(* Available for 24WC01 and 24WC02 only)
	A0					1	8												VCC
						2	7
	A1																		WP
						3	6
	A2																		SCL
						4	5
	VSS																		SDA

PIN FUNCTIONS

Pin Name	Function
A0, A1, A2	Device Address Inputs
SDA	Serial Data/Address
SCL	Serial Clock
WP	Write Protect
VCC	+1.8V to +6.0V Power Supply
VSS	Ground

BLOCK DIAGRAM

EXTERNAL LOAD

		DOUT	SENSE AMPS
			SHIFT REGISTERS
		ACK
	VCC
	VSS	WORD ADDRESS	COLUMN
		BUFFERS	DECODERS
	SDA	START/STOP
		LOGIC
		XDEC	E2PROM
	WP	CONTROL
		LOGIC
			DATA IN STORAGE

HIGH VOLTAGE/

TIMING CONTROL

SCL STATE COUNTERS

A0		SLAVE
A1		ADDRESS
A2		COMPARATORS

* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.		24WCXX F03
© 1999 by Catalyst Semiconductor, Inc.	1	Doc. No. 25051-00 3/98 S-1
Characteristics subject to change without notice

CAT24WC01/02/04/08/16

ABSOLUTE MAXIMUM RATINGS*

*COMMENT

Temperature Under Bias .................	–55° C to +125° C
Storage Temperature .......................	–65° C to +150° C
Voltage on Any Pin with
Respect to Ground(1) ...........	–2.0V to +VCC + 2.0V
VCC with Respect to Ground ...............		–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25° C) ..................................		1.0W
Lead Soldering Temperature (10 secs)		............ 300° C
Output Short Circuit Current(2) ........................		100mA

RELIABILITY CHARACTERISTICS

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

Symbol	Parameter	Min.	Max.	Units	Reference Test Method
NEND(3)	Endurance	1,000,000		Cycles/Byte	MIL-STD-883, Test Method 1033
TDR(3)	Data Retention	100		Years	MIL-STD-883, Test Method 1008
VZAP(3)	ESD Susceptibility	2000		Volts	MIL-STD-883, Test Method 3015
ILTH(3)(4)	Latch-up	100		mA	JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

				Limits
Symbol	Parameter	Min.			Typ.		Max.		Units		Test Conditions
ICC	Power Supply Current					3			mA		fSCL = 100 KHz
ISB(5)	Standby Current (VCC = 5.0V)					0			A		VIN = GND or VCC
ILI	Input Leakage Current					10			A		VIN = GND to VCC
ILO	Output Leakage Current					10			A		VOUT = GND to VCC
VIL	Input Low Voltage	–1				VCC x 0.3			V
VIH	Input High Voltage	VCC x 0.7				VCC + 0.5			V
VOL1	Output Low Voltage (VCC = 3.0V)					0.4			V		IOL = 3 mA
VOL2	Output Low Voltage (VCC = 1.8V)					0.5			V		IOL = 1.5 mA
CAPACITANCE TA = 25° C, f = 1.0 MHz, VCC = 5V
Symbol	Test				Max.		Units				Conditions
CI/O(3)	Input/Output Capacitance (SDA)			8			pF				VI/O = 0V
CIN(3)	Input Capacitance (A0, A1, A2, SCL, WP)			6			pF				VIN = 0V
Note:

(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.

(2)Output shorted for no more than one second. No more than one output shorted at a time.

(3)This parameter is tested initially and after a design or process change that affects the parameter.

(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

(5)Standby Current (ISB) = 0 A (<900nA).

Doc. No. 25051-00 3/98 S-1	2

CAT24WC01/02/04/08/16

A.C. CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

Read & Write Cycle Limits

Symbol	Parameter	1.8V, 2.5V		4.5V-5.5V
		Min.	Max.	Min.	Max.	Units
FSCL	Clock Frequency		100		400	kHz
TI(1)	Noise Suppression Time		200		200	ns
	Constant at SCL, SDA Inputs
tAA	SCL Low to SDA Data Out		3.5		1	s
	and ACK Out
tBUF(1)	Time the Bus Must be Free Before	4.7		1.2		s
	a New Transmission Can Start
tHD:STA	Start Condition Hold Time	4		0.6		s
tLOW	Clock Low Period	4.7		1.2		s
tHIGH	Clock High Period	4		0.6		s
tSU:STA	Start Condition Setup Time	4.7		0.6		s
	(for a Repeated Start Condition)
tHD:DAT	Data In Hold Time	0		0		ns
tSU:DAT	Data In Setup Time	50		50		ns
tR(1)	SDA and SCL Rise Time		1		0.3	s
tF(1)	SDA and SCL Fall Time		300		300	ns
tSU:STO	Stop Condition Setup Time	4		0.6		s
tDH	Data Out Hold Time	100		100		ns

Power-Up Timing(1)(2)

Symbol		Parameter				Max.	Units
tPUR		Power-up to Read Operation				1	ms
tPUW		Power-up to Write Operation				1	ms
Write Cycle Limits
Symbol		Parameter	Min.	Typ.		Max	Units
tWR		Write Cycle Time				10	ms

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus

Note:

interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

(1)This parameter is tested initially and after a design or process change that affects the parameter.

(2)tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

3	Doc. No. 25051-00 3/98 S-1