CTLST CAT25C322U14-45TE13, CAT25C322U14-42TE13, CAT25C322U14-30TE13, CAT25C322U14-28TE13, CAT25C322U14-25TE13 Datasheet

Advanced

CAT25CXXX

Supervisory Circuits with SPI Serial E2PROM, Precision Reset Controller and Watchdog Timer

FEATURES

	■	10 MHz SPI Compatible	■ Watchdog Timer on CS
			■ 1,000,000 Program/Erase Cycles
	■	1.8 to 6.0 Volt Operation
			■ 100 Year Data Retention
	■	Hardware and Software Protection
			■ Self-Timed Write Cycle
	■	Zero Standby Current
			■ 8-Pin DIP/SOIC, 16-Pin SOIC and 14-Pin TSSOP
	■	Low Power CMOS Technology
			■ Page Write Buffer
	■	SPI Modes (0,0 &1,1)
			■ Block Write Protection
	■	Commercial, Industrial and Automotive
			2
		Temperature Ranges	– Protect 1/4, 1/2 or all of EPROM Array
			■ Programmable Watchdog Timer
	■	Active High or Low Reset Outputs
			■ Built-in inadvertent Write Protection
		– Precision Power Supply Voltage Monitoring
		– 5V, 3.3V, 3V and 1.8V Options	– V Lock Out
			CC

DESCRIPTION

The CAT25CXXX is a single chip solution to three popular functions of EEPROM Memory, precision reset controller and watchdog timer. The EEPROM Memory is a 2K/4K/8K/16K/32K-Bit SPI Serial CMOS E2PROM internally organized as 256x8/512x8/1024x8/2048x8/ 4096x8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The 2K/4K devices feature a 16-byte page write buffer. The 8K/16K/32K devices feature a 32-byte page write buffer.The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In

addition to the Chip Select, the clock input (SCK), data in (SI) and data out (SO) are required to access the device. The reset function of the 25CXXX protects the system during brown out and power up/down condtions. During system failure the watchdog timer feature protects the microcontroller with a reset signal. The CAT25CXXX is designed with software and hardware write protection features including Block Lock protection. The device is available in 8-pin DIP, 8-pin SOIC, 16pin SOIC and 14-pin TSSOP packages.

PIN CONFIGURATION

TSSOP Package (U14)					SOIC Package (S16)				SOIC Package (S)				DIP Package (P)
					CS	1	16	VCC
CS		1	14	VCC					CS	1	8	VCC	CS					1	8				VCC
SO		2	13	RESET/RESET	SO	2	15	RESET/RESET	SO	2	7	RESET/RESET	SO					2	7				RESET/RESET
NC		3	12	NC	NC	3	14	NC	WP	3	6	SCK	WP					3	6				SCK
NC		4	11	NC	NC	4	13	NC
									VSS	4	5	SI						4	5
		5	10										V										SI
NC				NC	NC	5	12	NC					SS
WP		6	9	SCK
					NC	6	11	NC
VSS		7	8	SI
					WP	7	10	SCK
					VSS	8	9	SI

© 1998 by Catalyst Semiconductor, Inc.	9-95
Characteristics subject to change without notice

CAT25CXXX

Advanced

PIN FUNCTIONS

Pin Name	Function
SO	Serial Data Output
SCK	Serial Clock
WP	Write Protect
VCC	+1.8V to +6.0V Power Supply
VSS	Ground
CS	Chip Select
SI	Serial Data Input
RESET/RESET	Reset I/O
NC	No Connect

BLOCK DIAGRAM
					SENSE AMPS
					SHIFT REGISTERS
		WORD ADDRESS			COLUMN
		BUFFERS			DECODERS
SO		I/O
SI	CONTROL		CONTROL
CS		SPI		XDEC	E2PROM
WP					ARRAY
	CONTROL
SCK		LOGIC	LOGIC
		BLOCK
	PROTECT
		LOGIC
					DATA IN
					STORAGE
					HIGH VOLTAGE/
					TIMING CONTROL
		STATUS
	REGISTER
			Reset Controller
RESET/RESET		Watchdog		High Precision
				VCC Monitor
					25CXXX F02.1

RELIABILITY CHARACTERISTICS

Symbol			Parameter		Min.	Max.	Units		Reference Test Method
NEND(3)		Endurance			1,000,000		Cycles/Byte		MIL-STD-883, Test Method 1033
TDR(3)		Data Retention			100		Years		MIL-STD-883, Test Method 1008
VZAP(3)		ESD Susceptibility			2000		Volts		MIL-STD-883, Test Method 3015
ILTH(3)(4)		Latch-Up			100		mA		JEDEC Standard 17
Power-Up Timing(1)(2)
Symbol				Parameter					Max.		Units
tPUR			Power-up to Read Operation						1		ms
tPUW			Power-up to Write Operation						1		ms

(1)This parameter is tested initially and after a design or process change that affects the parameter.

(2)tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

(3)This parameter is tested initially and after a design or process change that affects the parameter.

(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

Stock No. 21085-01 4/98	9-96

Advanced

CAT25CXXX

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias .................	–55°C to +125°C
Storage Temperature .......................	–65°C to +150°C
Voltage on any Pin with
Respect to Ground(1) ............	–2.0V to +VCC +2.0V
VCC with Respect to Ground ...............		–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ...................................		1.0W
Lead Soldering Temperature (10 secs)		............ 300°C
Output Short Circuit Current(2) ........................		100 mA

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

*COMMENT

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

			Limits
Symbol	Parameter	Min.	Typ.	Max.	Units	Test Conditions
ICC1	Power Supply Current			5	mA	VCC = 5V @ 5MHz
	(Operating Write)					SO=open; CS=Vss
ICC2	Power Supply Current			0.4	mA	VCC = 5.5V
	(Operating Read)					FCLK = 5MHz
ISB	Power Supply Current			0	μA	CS = VCC
	(Standby)					VIN = VSS or VCC
ILI	Input Leakage Current			2	μA
ILO	Output Leakage Current			3	μA	VOUT = 0V to VCC,
						CS = 0V
VIL(3)	Input Low Voltage	-1		VCC x 0.3	V
VIH(3)	Input High Voltage	VCC x 0.7		VCC + 0.5	V
VOL1	Output Low Voltage			0.4	V	4.5V≤VCC<5.5V
						IOL = 3.0mA
VOH1	Output High Voltage	VCC - 0.8			V
						IOH = -1.6mA
VOL2	Output Low Voltage			0.2	V	1.8V≤VCC<2.7V
						IOL = 150μA
VOH2	Output High Voltage	VCC-0.2			V
						IOH = -100μA

Note:

(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.

(2)Output shorted for no more than one second. No more than one output shorted at a time.

(3)This parameter is tested initially and after a design or process change that affects the parameter.

9-97	Stock No. 21085-01 4/98

CAT25CXXX					Advanced
Figure 1. Sychronous Data Timing					tCS
VIH
CS
VIL					tCSH
	tCSS
VIH
SCK		tWH	tWL
VIL	tSU	tH
VIH	VALID IN
SI
VIL
			tV	tHO	tDIS
VOH	HI-Z				HI-Z
SO
VOL

A.C. CHARACTERISTICS

						Limits
				1.8, 2.5			4.5V-5.5V			Test
SYMBOL	PARAMETER		Min.		Max.		Min.	Max.	UNITS	Conditions
tSU	Data Setup Time		50				10		ns	VIH = 2.4V
tH	Data Hold Time		50				20		ns	CL = 100pF
tWH	SCK High Time		200				40		ns	VOL = 0.8V
tWL	SCK Low Time		200				40		ns	VOH = 2.0v
fSCK	Clock Frequency		DC		2		DC	10	MHz
tLZ	HOLD to Output Low Z				50			50	ns
tRI(1)	Input Rise Time				2			2	μs	CL = 50pF
tFI(1)	Input Fall Time				2			2	μs
tHD	HOLD Setup Time		100				40		ns
tCD	HOLD HOLD Time		100				40		ns	CL = 100pF
tWC	Write Cycle Time				10			5	ms
tV	Output Valid from Clock Low				200			80	ns
tHO	Output HOLD Time		0				0		ns
tDIS	Output Disable Time				250			75	ns
tHZ	HOLD to Output High Z				100			50	ns
tCS	CS High Time		250				100		ns
tCSS	CS Setup Time		250				100		ns
tCSH	CS HOLD Time		250				100		ns

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

Stock No. 21085-01 4/98	9-98