CTLST CAT25C16UA-1.8TE13, CAT25C16U14I-TE13, CAT25C16U14I-1.8TE13, CAT25C16U14A-TE13, CAT25C16U14A-1.8TE13 Datasheet

Advanced Information

CAT25C01/02/04/08/16

1K/2K/4K/8K/16K SPI Serial CMOS E2PROM

FEATURES

■10 MHz SPI Compatible

■1.8 to 6.0 Volt Operation

■Hardware and Software Protection

■Zero Standby Current

■Low Power CMOS Technology

■SPI Modes (0,0 & 1,1)

■Commercial, Industrial and Automotive Temperature Ranges

■1,000,000 Program/Erase Cycles

■100 Year Data Retention

■Self-Timed Write Cycle

■8-Pin DIP/SOIC, 8/14-Pin TSSOP and 8-Pin MSOP

■16/32-Byte Page Write Buffer

■Block Write Protection

– Protect 1/4, 1/2 or all of E2PROM Array

DESCRIPTION

The CAT25C01/02/04/08/16 is a 1K/2K/4K/8K/16K Bit SPI Serial CMOS E2PROM internally organized as 128x8/256x8/512x8/1024x8/2048x8 bits. Catalyst’s advanced CMOS Technology substantially reduces device power requirements. The CAT25C01/02/04 features a 16-byte page write buffer. The 25C08/16 features a 32-byte page write buffer.The device operates via the SPI bus serial interface and is enabled though a Chip Select (CS). In addition to the Chip Select, the clock

input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. The CAT25C01/02/04/08/16 is designed with software and hardware write protection features including Block Write protection. The device is available in 8-pin DIP, 8-pin SOIC, 8-pin MSOP and 8/ 14-pin TSSOP packages.

PIN CONFIGURATION

TSSOP Package (U14)

SOIC Package (S)

CS

1

8

VCC

CS

1

14

VCC

2

7

SO

2

13

HOLD

SO

HOLD

3

6

SCK

NC

3

12

NC

WP

4

5

NC

4

11

NC

VSS

SI

NC

5

10

NC

WP

6

9

SCK

MSOP Package (R)*

VSS

7

8

SI

CS

1

8

VCC

SO

2

7

HOLD

WP

3

6

SCK

VSS

4

5

SI

*CAT 25C01/02 only

PIN FUNCTIONS

Pin Name

Function

SO

Serial Data Output

SCK

Serial Clock

WP

Write Protect

VCC

+1.8V to +6.0V Power Supply

VSS

Ground

CS

Chip Select

SI

Serial Data Input

HOLD

Suspends Serial Input

NC

No Connect

DIP Package (P)					TSSOP Package (U)
	1	8	VCC
CS				CS			1	8				VCC
	2	7					2	7
SO			HOLD	SO								HOLD
							3	6
WP	3	6	SCK	WP								SCL
							4	5
VSS	4	5	SI	VSS								SI

	BLOCK DIAGRAM
					SENSE AMPS
					SHIFT REGISTERS
		WORD ADDRESS			COLUMN
		BUFFERS			DECODERS
	SO	I/O
	SI	CONTROL	CONTROL
	CS	SPI		XDEC	E2PROM
	WP				ARRAY
		CONTROL
	HOLD
		LOGIC	LOGIC
	SCK
		BLOCK
		PROTECT
		LOGIC
					DATA IN
					STORAGE
					HIGH VOLTAGE/
					TIMING CONTROL
		STATUS
		REGISTER			25C128 F02

© 1999 by Catalyst Semiconductor, Inc.	1	Doc. No. 25067-00 5/00
Characteristics subject to change without notice

CAT25C01/02/04/08/16	Advanced Information
ABSOLUTE MAXIMUM RATINGS*	*COMMENT

Temperature Under Bias .................	–55° C to +125° C
Storage Temperature .......................	–65° C to +150° C
Voltage on any Pin with
Respect to VSS(1) ..................	–2.0V to +VCC +2.0V
VCC with Respect to VSS ................................		–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25° C) ...................................		1.0W
Lead Soldering Temperature (10 secs)		............ 300° C
Output Short Circuit Current(2) ........................		100 mA

RELIABILITY CHARACTERISTICS

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

Symbol	Parameter	Min.	Max.	Units	Reference Test Method
NEND(3)	Endurance	1,000,000		Cycles/Byte	MIL-STD-883, Test Method 1033
TDR(3)	Data Retention	100		Years	MIL-STD-883, Test Method 1008
VZAP(3)	ESD Susceptibility	2000		Volts	MIL-STD-883, Test Method 3015
ILTH(3)(4)	Latch-Up	100		mA	JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +1.8V to +6.0V, unless otherwise specified.

			Limits
Symbol	Parameter	Min.	Typ.	Max.	Units	Test Conditions
ICC1	Power Supply Current			5	mA	VCC = 5V @ 5MHz
	(Operating Write)					SO=open; CS=Vss
ICC2	Power Supply Current			3	mA	VCC = 5.5V
	(Operating Read)					FCLK = 5MHz
ISB	Power Supply Current			0	A	CS = VCC
	(Standby)					VIN = VSS or VCC
ILI	Input Leakage Current			2	A
ILO	Output Leakage Current			3	A	VOUT = 0V to VCC,
						CS = 0V
VIL(3)	Input Low Voltage	-1		VCC x 0.3	V
VIH(3)	Input High Voltage	VCC x 0.7		VCC + 0.5	V
VOL1	Output Low Voltage			0.4	V	4.5V≤ VCC<5.5V
						IOL = 3.0mA
VOH1	Output High Voltage	VCC - 0.8			V
						IOH = -1.6mA
VOL2	Output Low Voltage			0.2	V	1.8V≤ VCC<2.7V
VOH2	Output High Voltage	VCC-0.2			V	IOL = 150 A
						IOH = -100 A

Note:

(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.

(2)Output shorted for no more than one second. No more than one output shorted at a time.

(3)This parameter is tested initially and after a design or process change that affects the parameter.

(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

Doc. No. 25067-00 5/00	2

Advanced Information					CAT25C01/02/04/08/16
Figure 1. Sychronous Data Timing
VIH					tCS
CS
VIL					tCSH
	tCSS
VIH			tWL
SCK		tWH
VIL	tSU	tH
VIH	VALID IN
SI
VIL				tRI
				tFI
			tV	tHO	tDIS
VOH	HI-Z				HI-Z
SO

VOL

Note: Dashed Line= mode (1, 1) – – – – –

A.C. CHARACTERISTICS

				Limits
		1.8V-6.0V		2.5V-6.0V		4.5V-5.5V			Test
SYMBOL	PARAMETER	Min.	Max.	Min.	Max.	Min.	Max.	UNITS	Conditions
tSU	Data Setup Time	50		20		20		ns	VIH = 2.4V
tH	Data Hold Time	50		20		20		ns	CL = 100pF
tWH	SCK High Time	250		75		40		ns	VOL = 0.8V
tWL	SCK Low Time	250		75		40		ns	VOH = 2.0v
fSCK	Clock Frequency	DC	1	DC	5	DC	10	MHz
tLZ	HOLD to Output Low Z		50		50		50	ns
tRI(1)	Input Rise Time		2		2		2	s
tFI(1)	Input Fall Time		2		2		2	s
tHD	HOLD Setup Time	100		40		40		ns
tCD	HOLD Hold Time	100		40		40		ns	CL = 100pF
									CL = 50pF
tWC	Write Cycle Time		10		5		5	ms
tV	Output Valid from Clock Low		250		80		80	ns
tHO	Output Hold Time	0		0		0		ns
tDIS	Output Disable Time		250		75		75	ns
tHZ	HOLD to Output High Z		150		50		50	ns
tCS	CS High Time	500		100		100		ns
tCSS	CS Setup Time	500		100		100		ns
tCSH	CS Hold Time	500		100		100		ns
tWPS	WP Setup Time	150		50		50		ns
tWPH	WP Hold Time	150		50		50		ns

NOTE:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

3	Doc. No. 25067-00 5/00