CTLST CAT24C643PA-30TE13, CAT24C643PA-28TE13, CAT24C643PA-25TE13, CAT24C643P-45TE13, CAT24C643P-42TE13 Datasheet

Advanced

CAT24C323(32K), CAT24C643 (64K)

Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer

FEATURES

■Watchdog Timer Input (WDI)

■Programmable Reset Threshold

■400 KHz I2C Bus Compatible

■2.7 to 6 Volt Operation

■Low Power CMOS Technology

■32 - Byte Page Write Buffer

■Built-in inadvertent write protection

—VCC Lock Out

■Active High or Low Reset Outputs

—Precision Power Supply Voltage Monitoring

—5V, 3.3V and 3V options

■1,000,000 Program/Erase Cycles

■100 Year Data Retention

■8-Pin DIP or 8-Pin SOIC

■Commercial, Industrial and Automotive Temperature Ranges

DESCRIPTION

The CAT24C323/643 is a single chip solution to three popular functions of EEPROM memory, precision reset controller and watchdog timer. The 24C323(32K) and 24C643 (64K) feature a I2C Serial CMOS EEPROM Catalyst advanced CMOS technology substantially reduces device power requirements. The 24C323/643 features a 32-byte page and is available in 8-pin DIP or 8-pin SOIC packages.

The reset function of the 24C323/643 protects the system during brown out and power up/down conditions. During system failure the watchdog timer feature protects the microcontroller with a reset signal. 24C323 features active low reset on pin 2 and active high reset on pin 7. 24C323/643 features watchdog timer on the WDI input pin (pin 1).

PIN CONFIGURATION	BLOCK DIAGRAM
24C323/643*	EXTERNAL LOAD

			DOUT	SENSE AMPS
WDI	VCC			SHIFT REGISTERS
			ACK
RESET	RESET	VCC
WP	SCL	VSS	WORD ADDRESS	COLUMN
VSS	SDA		BUFFERS	DECODERS
*All products offered in P	and J packages	SDA	START/STOP
			LOGIC
PIN FUNCITONS			XDEC	E2PROM
Pin Name	Function
			CONTROL
		WP
SDA	Serial Data/Address		LOGIC
RESET/RESET	Reset I/O
SCL	Clock Input			DATA IN STORAGE
Vcc	Power Supply			HIGH VOLTAGE/
VSS	Ground
				TIMING CONTROL
WDI	Watchdog Timer Input		RESET Controller	STATE COUNTERS	SCL
			High
WP	Write Protect
			Precision	SLAVE
			WATCHDOG	ADDRESS
			Vcc Monitor
				COMPARATORS
			WDI RESET/RESET

© 1998 by Catalyst Semiconductor, Inc.	Doc. No. 25084-00 12/98
Characteristics subject to change without notice	1

CAT24C323/643	Advanced
ABSOLUTE MAXIMUM RATINGS*	COMMENT

Temperature Under Bias....................	–55°C to +125°C
Storage Temperature........................	–65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ..............	–2.0V to +V	+ 2.0V
		CC
VCC with Respect to Ground..................	–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)1.0W.................................		1.0W
Lead Soldering Temperature (10 secs)...............		300°C
Output Short Circuit Current(2) ..........................		100mA

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

RELIABILITY CHARACTERISTICS

Symbol	Parameter	Min.	Max.	Units	Reference Test Method
NEND(3)	Endurance	1,000,000		Cycles/Byte	MIL-STD-883, Test Method 1033
TDR(3)	Data Retention	100		Years	MIL-STD-883, Test Method 1008
VZAP(3)	ESD Susceptibility	2000		Volts	MIL-STD-883, Test Method 3015
ILTH(3)(4)	Latch-up	100		mA	JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = +2.7V to +6.0V, unless otherwise specified.

			Limits
Symbol	Parameter	Min.		Typ.	Max.	Units	Test Conditions
ICC	Power Supply Current				3	mA	fSCL = 100 KHz
Isb	Standby Current				40	μA	Vcc=3.3V
					50	μA	Vcc=5
ILI	Input Leakage Current				2	μA	VIN=GND or VCC
ILO	Output Leakage Current				10	μA	VIN=GND or VCC
VIL	Input Low Voltage	–1			VCC x 0.3	V
VIH	Input High Voltage	VCC x 0.7			VCC + 0.5	V
VOL	Output Low Voltage (SDA)				0.4	V	IOL = 3 mA, VCC = 3.0V

CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V

Symbol	Test	Max.	Units	Conditions
CI/O(3)	Input/Output Capacitance (SDA)	8	pF	VI/O = 0V
CIN(3)	Input Capacitance (SCL)	6	pF	VIN = 0V

Note:

(1)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.

(2)Output shorted for no more than one second. No more than one output shorted at a time.

(3)This parameter is tested initially and after a design or process change that affects the parameter.

(4)Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.

Doc. No. 25084-00 12/98	2

Advanced

CAT24C323/643

A.C. CHARACTERISTICS

VCC=2.7V to 6.0V unless otherwise specified.

Output Load is 1 TTL Gate and 100pF

Read & Write Cycle Limits

Symbol	Parameter	VCC=2.7V - 6V		VCC=4.5V - 5.5V
		Min.	Max.	Min.	Max.	Units
FSCL	Clock Frequency		100		400	kHz
TI(1)	Noise Suppression Time		200		200	ns
	Constant at SCL, SDA Inputs
tAA	SCL Low to SDA Data Out		3.5		1	μs
	and ACK Out
tBUF(1)	Time the Bus Must be Free Before	4.7		1.2		μs
	a New Transmission Can Start
tHD:STA	Start Condition Hold Time	4		0.6		μs
tLOW	Clock Low Period	4.7		1.2		μs
tHIGH	Clock High Period	4		0.6		μs
tSU:STA	Start Condition Setup Time	4.7		0.6		μs
	(for a Repeated Start Condition)
tHD:DAT	Data In Hold Time	0		0		ns
tSU:DAT	Data In Setup Time	50		50		ns
tR(1)	SDA and SCL Rise Time		1		0.3	μs
tF(1)	SDA and SCL Fall Time		300		300	ns
tSU:STO	Stop Condition Setup Time	4		0.6		μs
tDH	Data Out Hold Time	100		100		ns

Power-Up Timing(1)(2)

Symbol	Parameter	Max.	Units
tPUR	Power-up to Read Operation	1	ms
tPUW	Power-up to Write Operation	1	ms

Note:

(1)This parameter is tested initially and after a design or process change that affects the parameter.

(2)tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

Write Cycle Limits

Symbol	Parameter	Min.	Typ.	Max	Units
tWR	Write Cycle Time			10	ms

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.

Doc. No. 25084-00 12/98

3

CAT24C323/643								Advanced
RESET CIRCUIT CHARACTERISTICS
	Symbol			Parameter	Min.	Max.	Units
	tGLITCH			Glitch Reject Pulse Width		100	ns
	VRT			Reset Threshold Hystersis	15		mV
	VOLRS			Reset Output Low Voltage (IOLRS=1mA)		0.4	V
	VOHRS			Reset Output High Voltage	Vcc-0.75		V
				Reset Threshold (Vcc=5V)	4.50	4.75
				(24CXXX-45)
				Reset Threshold (Vcc=5V)	4.25	4.50
				(24CXXX-42)			V
	VTH			Reset Threshold (Vcc=3.3V)	3.00	3.15
				(24CXXX-30)
				Reset Threshold (Vcc=3.3V)	2.85	3.00
				(24CXXX-28)
				Reset Threshold (Vcc=3V)	2.55	2.70
				(24CXXX-25)
	tPURST			Power-Up Reset Timeout	130	270	ms
	tRPD			V to RESET Output Delay		5	μs
				TH
	VRVALID			RESET Output Valid	1		V

Doc. No. 25084-00 12/98	4