CTLST CAT28C256PI-12T, CAT28C256PA-15T, CAT28C256PA-12T, CAT28C256P-12T, CAT28C256NI-15T Datasheet

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CAT28C256

32K-Bit Parallel E2PROM

FEATURES

■Fast Read Access Times: 120/150ns

■Low Power CMOS Dissipation:

–Active: 25 mA Max. –Standby: 150μA Max.

■Simple Write Operation:

–On-Chip Address and Data Latches –Self-Timed Write Cycle with Auto-Clear

■Fast Write Cycle Time: –5ms Max

■CMOS and TTL Compatible I/O

■Hardware and Software Write Protection

■Automatic Page Write Operation: –1 to 64 Bytes in 5ms

–Page Load Timer

■End of Write Detection: –Toggle Bit

–DATA Polling

■100,000 Program/Erase Cycles

■100 Year Data Retention

■Commerical, Industrial and Automotive Temperature Ranges

DESCRIPTION

The CAT28C256 is a fast, low power, 5V-only CMOS parallel E2PROM organized as 32K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with autoclear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the selftimed write cycle. Additionally, the CAT28C256 features hardware and software write protection.

The CAT28C256 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC packages.

BLOCK DIAGRAM
A6–A14	ADDR. BUFFER	ROW	32,768 x 8
A6–A14	& LATCHES	DECODER	E2PROM
			ARRAY
VCC	INADVERTENT	HIGH VOLTAGE	64 BYTE PAGE
	WRITE	GENERATOR	64 BYTE PAGE
	WRITE	GENERATOR	REGISTER
	PROTECTION		REGISTER
	PROTECTION
CE	CONTROL
OE	CONTROL
WE	LOGIC
WE			I/O BUFFERS
			I/O BUFFERS
		DATA POLLING
	TIMER	AND
		TOGGLE BIT	I/O0–I/O7
			I/O0–I/O7
A0–A5	ADDR. BUFFER	COLUMN
A0–A5	& LATCHES	COLUMN
	& LATCHES	DECODER
		DECODER
			5096 FHD F02

© 1998 by Catalyst Semiconductor, Inc.	Doc. No. 25020-0A 2/98
Characteristics subject to change without notice	1

CAT28C256

PIN CONFIGURATION

DIP Package (P)					PLCC Package (N)
A14	1	28	VCC		7	12	14	NC	CC		WE	13
					7	12	14		CC			13
					A	A	A		V			A
					A	A	A		V			A
A12	2	27	WE
A7	3	26	A13		4	3	2	1	32 31 30
A6	4	25	A8	A6	5							29	A8
A5	5	24	A9	A5	6							28	A9
A4	6	23	A11	A4	7							27	A11
A3	7	22	OE	A3	8							26	NC
A2	8	21	A10	A2	9							25	OE
A1	9	20	CE	A1	10							24	A10
A0	10	19	I/O7	A0	11							23	CE
I/O0	11	18	I/O6	NC	12							22	I/O7
I/O1	12	17	I/O5	I/O0	13							21	I/O6
I/O2	13	16	I/O4		14 15 16 17 18 19 20
I/O2	13	16	I/O4
VSS	14	15	I/O3		1	2	SS	NC	3	4		5
					1	2	SS		3	4		5
					I/O	I/O	V		I/O		I/O	I/O

5096 FHD F01

TSOP Package (8mm X 13.4mm) (T13)

A10

A11

I/O7

I/O6

A13

I/O5

I/O4

VCC

I/O3

A14

GND

A12

I/O2

I/O1

I/O0

28C256 F03

PIN FUNCTIONS

Pin Name

Function

Pin Name

Function

A0–A14

Address Inputs

Write Enable

I/O0–I/O7

Data Inputs/Outputs

VCC

5V Supply

Chip Enable

VSS

Ground

Output Enable

No Connect

Doc. No. 25020-0A 2/98	2

CAT28C256

ABSOLUTE MAXIMUM RATINGS*

*COMMENT

Temperature Under Bias .................	–55°C to +125°C
Storage Temperature .......................	–65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) ...........	–2.0V to +VCC + 2.0V
VCC with Respect to Ground ...............		–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)...................................		1.0W
Lead Soldering Temperature (10 secs)		............ 300°C
Output Short Circuit Current(3) ........................		100 mA

RELIABILITY CHARACTERISTICS

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

Symbol	Parameter	Min.	Max.	Units	Test Method

NEND(1)	Endurance	104 or 105		Cycles/Byte	MIL-STD-883, Test Method 1033
TDR(1)	Data Retention	100		Years	MIL-STD-883, Test Method 1008
VZAP(1)	ESD Susceptibility	2000		Volts	MIL-STD-883, Test Method 3015
ILTH(1)(4)	Latch-Up	100		mA	JEDEC Standard 17

D.C. OPERATING CHARACTERISTICS

VCC = 5V ±10%, unless otherwise specified.

Limits

Symbol

Parameter

Min.

Typ.

Max.

Units

Test Conditions

ICC

VCC Current (Operating, TTL)

= VIL, f=8MHz

All I/O’s Open

ICCC(5)

VCC Current (Operating, CMOS)

= VILC, f=8MHz

All I/O’s Open

ISB

VCC Current (Standby, TTL)

= VIH, All I/O’s Open

ISBC(6)

VCC Current (Standby, CMOS)

150

μA

= VIHC,

All I/O’s Open

ILI

Input Leakage Current

–10

μA

VIN = GND to VCC

ILO

Output Leakage Current

–10

μA

VOUT = GND to VCC,

= VIH

VIH(6)

High Level Input Voltage

VCC +0.3

VIL(5)

Low Level Input Voltage

–0.3

0.8

VOH

High Level Output Voltage

2.4

IOH = –400μA

VOL

Low Level Output Voltage

0.4

IOL = 2.1mA

VWI

Write Inhibit Voltage

3.5

Note:

(1)This parameter is tested initially and after a design or process change that affects the parameter.

(2)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.

(3)Output shorted for no more than one second. No more than one output shorted at a time.

(4)Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.

(5)VILC = –0.3V to +0.3V.

(6)VIHC = VCC –0.3V to VCC +0.3V.

3	Doc. No. 25020-0A 2/98

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