CTLST CAT28LV64T13I-35T, CAT28LV64T13I-30T, CAT28LV64T13I-25T, CAT28LV64T13A-35T, CAT28LV64T13A-30T Datasheet

Preliminary

CAT28LV64

64K-Bit CMOS PARALLEL E2PROM

FEATURES

	■ 3.0V to 3.6 V Supply	■ CMOS and TTL Compatible I/O
	■ Read Access Times:	■ Automatic Page Write Operation:
	– 250/300/350ns	– 1 to 32 Bytes in 5ms
	■ Low Power CMOS Dissipation:	– Page Load Timer
		■ End of Write Detection:
	– Active: 8 mA Max.
	– Standby: 100μA Max.	– Toggle Bit
	■ Simple Write Operation:	–DATA Polling
		■ Hardware and Software Write Protection
	– On-Chip Address and Data Latches
	– Self-Timed Write Cycle with Auto-Clear	■ 100,000 Program/Erase Cycles
	■ Fast Write Cycle Time:	■ 100 Year Data Retention
	– 5ms Max.
	■ Commercial, Industrial and Automotive
	Temperature Ranges

DESCRIPTION

The CAT28LV64 is a low voltage, low power, CMOS parallel E2PROM organized as 8K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with autoclear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bit signal the start and end of the selftimed write cycle. Additionally, the CAT28LV64 features hardware and software write protection.

The CAT28LV64 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32pin PLCC packages.

	BLOCK DIAGRAM
	A5–A12	ADDR. BUFFER	ROW	8,192 x 8
		& LATCHES	DECODER	E2PROM
				ARRAY
	VCC	INADVERTENT	HIGH VOLTAGE	32 BYTE PAGE
		WRITE	GENERATOR
				REGISTER
		PROTECTION
	CE	CONTROL
	OE
	WE	LOGIC
				I/O BUFFERS
			DATA POLLING
		TIMER	AND
			TOGGLE BIT	I/O0–I/O7
	A0–A4	ADDR. BUFFER	COLUMN
		& LATCHES
			DECODER

5094 FHD F02

© 1998 by Catalyst Semiconductor, Inc.	Doc. No. 25035-00 2/98
Characteristics subject to change without notice	1

CAT28LV64 Preliminary

PIN CONFIGURATION

	DIP Package (P)					SOIC Package (J, K)
	NC	1	28	VCC		NC			1	28					VCC
	A12	2	27	WE		A12			2	27					WE
	A7	3	26	NC		A7			3	26					NC
	A6	4	25	A8		A6			4	25					A8
	A5	5	24	A9		A5			5	24					A9
	A4	6	23	A11		A4			6	23					A11
	A3	7	22	OE		A3			7	22					OE
	A2	8	21	A10		A2			8	21					A10
	A1	9	20	CE		A1			9	20					CE
	A0	10	19	I/O7		A0			10	19					I/O7
	I/O	11	18	I/O	6	I/O0			11	18					I/O6
	0					I/O1			12	17					I/O5
	I/O	12	17	I/O	5
	1					I/O2			13	16					I/O4
	I/O2	13	16	I/O4
	VSS	14	15	I/O3		VSS			14	15					I/O3

PLCC Package (N)

	7	12	NC	NC	CC		WE	NC
	A	A			V
	4	3	2	1	32 31 30
A6	5							29	A8
A5	6							28	A9
A4	7							27	A11
A3	8							26	NC
A2	9	TOP VIEW						25	OE
A1	10							24	A10
A0	11							23	CE
NC	12							22	I/O7
I/O0	13							21	I/O6
	14 15 16 17 18 19 20
	1	2	SS	NC	3		4	5
	I/O	I/O	V		I/O		I/O	I/O

TSOP Top View (8mm x 13.4mm) (T13)

	OE				1	28					A10
A11					2	27					CE
	A9				3	26					I/O7
	A8				4	25					I/O6
	NC				5	24					I/O5
	WE				6	23					I/O4
VCC					7	22					I/O3
	NC				8	21					GND
A12					9	20					I/O2
	A7				10	19					I/O1
	A6				11	18					I/O0
	A5				12	17					A0
	A4				13	16					A1
	A3				14	15					A2
							28LV64 F03

5094 FHD F01

PIN FUNCTIONS

Pin Name	Function	Pin Name	Function
A0–A12	Address Inputs	WE	Write Enable
I/O0–I/O7	Data Inputs/Outputs	VCC	3.0 to 3.6 V Supply
CE	Chip Enable	VSS	Ground
OE	Output Enable	NC	No Connect

Doc. No. 25035-00 2/98	2

Preliminary	CAT28LV64
ABSOLUTE MAXIMUM RATINGS*	*COMMENT

Temperature Under Bias .................	–55°C to +125°C
Storage Temperature .......................	–65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) ...........	–2.0V to +VCC + 2.0V
VCC with Respect to Ground ...............		–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ...................................		1.0W
Lead Soldering Temperature (10 secs)		............ 300°C
Output Short Circuit Current(3) ........................		100 mA

RELIABILITY CHARACTERISTICS

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.

Symbol	Parameter	Min.	Max.	Units	Test Method
NEND(1)	Endurance	105		Cycles/Byte	MIL-STD-883, Test Method 1033
TDR(1)	Data Retention	100		Years	MIL-STD-883, Test Method 1008
VZAP(1)	ESD Susceptibility	2000		Volts	MIL-STD-883, Test Method 3015
ILTH(1)(4)	Latch-Up	100		mA	JEDEC Standard 17

MODE SELECTION

Mode					CE	WE	OE	I/O	Power
Read					L	H	L	DOUT	ACTIVE
Byte Write		(WE		Controlled)	L		H	DIN	ACTIVE
Byte Write	(CE		Controlled)			L	H	DIN	ACTIVE
Standby, and Write Inhibit					H	X	X	High-Z	STANDBY
Read and Write Inhibit					X	H	H	High-Z	ACTIVE

CAPACITANCE TA = 25°C, f = 1.0 MHz

Symbol	Test	Max.	Units	Conditions
CI/O(1)	Input/Output Capacitance	10	pF	VI/O = 0V
CIN(1)	Input Capacitance	6	pF	VIN = 0V

Note:

(1)This parameter is tested initially and after a design or process change that affects the parameter.

(2)The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.

(3)Output shorted for no more than one second. No more than one output shorted at a time.

(4)Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.

3	Doc. No. 25035-00 2/98