Sony CXD2443Q Datasheet

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CXD2443Q

Timing Generator for LCD Panels

Description

The CXD2443Q is a timing generator for the LCD panel LCX011 and LCX019 driver. This chip has a built-in serial interface circuit which allows various settings to be performed through external control from a microcomputer, etc.

Features

•Generates the LCD panel LCX011/LCX019 drive pulse

•Supports NTSC/PAL

(PAL supported by scanning line conversion of video signal to 525H or pulse eliminate.)

•Supports WIDE mode (when driving the LCX011)

•Supports HD mode (when driving the LCX011)

•Supports up/down and/or right/left inversion

•Supports 3-panel projectors

•Generates timing signal of external sample-and- hold circuit

•Generates line inversion and field inversion signals

•AC drive of LCD panels during no signal

•Line double-speed display realized with a built-in double-speed controller (NTSC/PAL) (4:3 mode only) (Line memory µPD485505: NEC)

Applications

LCD projectors, etc.

Structure

Silicon CMOS IC

100 pin QFP (Plastic)

Absolute Maximum Ratings (Ta = 25°C, VSS = 0V)

• Supply voltage	VDD VSS – 0.5 to +7.0			V
• Input voltage	VI	VSS – 0.5 to VDD + 0.5		V
• Output voltage	VO	VSS – 0.5 to VDD + 0.5		V
• Operating temperature
	Topr		–20 to +75	°C
• Storage temperature Tstg			–55 to +150	°C

Recommended Operating Conditions

• Supply voltage VDD 4.5 to 5.5 V

• Operating temperature

Topr

–20 to +75

°C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E96X31-PS

CXD2443Q

Block Diagram

TC1

TC2

TC3

CKSL CKI5

CKI3

CKO3

CKI2

CKO2

CKI1

CKO1

98 99

PWM1

RPD1

PWM2

RPD2

16 : 9

4 : 3

LOOP

PWM3

RPD3

FILTER

PEO1

PHASE

FPD1

COMPARATOR

PEO2

FPD2

MASTER CLOCK

PEO3

FPD3

PLL COUNTER

HSYNC

H-SYNC DETECTOR

DECODER

100

HDR

VSYNC

V-SYNC SEPARATOR

HSTA

HCK1A

HCK2A

V-CONTROL COUNTER

ENB

VCK

V-POSITION COUNTER

FIELD & LINE

FRP

VST

XFRP

DECODER

CONTROLLER

FLDO

PCG1

VWA

V-TIMING PULSE

XCLP1

GENERATOR

VWB

H-POSITION COUNTER

XCLP2

DECODER

PCG2

PULSE ELIMINATOR

SH1A

H-TIMING PULSE

SH2A

SCTR

GENERATOR

SH3A

SCLK

SERIAL I/F

SH4A

SDAT

SH5A

PRE

SH6A

DOUBLE SCAN

SH7A

H-SYNC DETECTOR

CONVERTER

HSTB

HCK1B

RPD4

HCK2B

FPD4

PHASE

SH1B

COMPARATOR

TC4

SH2B

CLOCK2

SH3B

PLL COUNTER2

SH4B

LOOP

DIRECT

SH5B

DECODER

FILTER

CLEAR

SH6B

SH7B

RCK

RSTR

WCK

RSTW

CKI4

CKO4

PEO4

PWM4

RGT

XRGT

DWN

XCLR

TEST: 12, 20, 22, 23, 24, 25, 26, 27, 33, 60, 69

VDD: 3, 28, 53, 78

VSS: 4, 15, 29, 40, 54, 65, 79, 90

– 2 –

				CXD2443Q

Pin Description

Pin	Symbol	I/O	Description	Input pin for
No.	Symbol	I/O	Description	open status
No.				open status

1	XCLR	I	System clear (Low: All clear)	H

2	VWB	O	V window pulse B output	—

3	VDD	—	Power supply	—

4	VSS	—	GND	—

5	TC1	I/O	FPD1 output pulse width adjustment (NTSC/PAL 4:3)	—

6	FPD1	O	Phase comparator 1 output (NTSC/PAL 4:3)	—

7	PEO1	I/O	Loop filter integrator 1 output (NTSC/PAL 4:3)	—

8	PWM1	O	Loop filter integrator 1 input (NTSC/PAL 4:3)	—

9	RPD1	O	Phase comparator 1 output (NTSC/PAL 4:3)	—

10	CKO1	I/O	Oscillation cell 1 output (NTSC/PAL 4:3)	—

11	CKI1	I	Oscillation cell 1 input (NTSC/PAL 4:3)	—

12	TEST2	I	Test (Not connected.)	—

13	HSYNC	I	Horizontal sync signal input (Polarity set by serial data HPOL.)	—

14	VSYNC	I	Vertical sync signal input (Polarity set by serial data VPOL.)	—

15	VSS	—	GND	—

16	SCTR	I	Chip select input (serial transfer block)	—

17	SCLK	I	Serial clock input (serial transfer block)	—

18	SDAT	I	Serial data input (serial transfer block)	—

19	PRE	I	Preset setting (Set to NTSC 4:3 mode when Low.)	H

20	TEST11	—	Test (Not connected.)	—

21	FLDO	O	Field discrimination signal output	—

22	TEST1	—	Test (Not connected.)	—

23	TEST3	—	Test (Not connected.)	—

24	TEST4	—	Test (Not connected.)	—

25	TEST5	—	Test (Not connected.)	—

26	TEST6	—	Test (Not connected.)	—

27	TEST7	—	Test (Connect to GND.)	—

28	VDD	—	Power supply	—

29	VSS	—	GND	—

30	VWA	O	V window pulse A output	—

31	PCG1	O	PCG1 pulse output (positive polarity)	—

32	DWN	O	Up/down inversion identification signal output (High: Down, Low: Up)	—

33	TEST8	—	Test (Not connected.)	—

34	VST	O	V start pulse output (positive polarity)	—

35	VCK	O	V clock pulse output	—

– 3 –

				CXD2443Q


Pin	Symbol	I/O	Description	Input pin for
No.	Symbol	I/O	Description	open status
No.				open status

36	ENB	O	ENB pulse output (negative polarity)	—

37	HCK2A	O	H clock 2A pulse output	—

38	HCK1A	O	H clock 1A pulse output	—

39	HCK2B	O	H clock 2B pulse output	—

40	VSS	—	GND	—

41	HCK1B	O	H clock 1B pulse output	—

42	HSTB	O	H start B pulse output (positive polarity)	—

43	HSTA	O	H start A pulse output (positive polarity)	—

44	RGT	O	Right/left inversion identification signal output (High: Right, Low: Left)	—

45	XRGT	O	Right/left inversion identification signal output (Low: Left, High: Right)	—

46	PCG2	O	PCG2 pulse output (positive polarity)	—

47	XCLP1	O	Pedestal clamp pulse 1 output (negative polarity)	—

48	XCLP2	O	Pedestal clamp pulse 2 output (negative polarity)	—

49	FRP	O	AC drive inversion timing output	—

50	XFRP	O	AC drive inversion timing output (reverse polarity of FRP)	—

51	SH1A	O	Sample-and-hold pulse 1A output (positive polarity)	—

52	SH2A	O	Sample-and-hold pulse 2A output (positive polarity)	—

53	VDD	—	Power supply	—

54	VSS	—	GND	—

55	SH3A	O	Sample-and-hold pulse 3A output (positive polarity)	—

56	SH4A	O	Sample-and-hold pulse 4A output (positive polarity)	—

57	SH5A	O	Sample-and-hold pulse 5A output (positive polarity)	—

58	SH6A	O	Sample-and-hold pulse 6A output (positive polarity)	—

59	SH7A	O	Sample-and-hold pulse 7A output (positive polarity)	—

60	TEST9	—	Test (Not connected.)	—

61	SH1B	O	Sample-and-hold pulse 1B output (positive polarity)	—

62	SH2B	O	Sample-and-hold pulse 2B output (positive polarity)	—

63	SH3B	O	Sample-and-hold pulse 3B output (positive polarity)	—

64	SH4B	O	Sample-and-hold pulse 4B output (positive polarity)	—

65	VSS	—	GND	—

66	SH5B	O	Sample-and-hold pulse 5B output (positive polarity)	—

67	SH6B	O	Sample-and-hold pulse 6B output (positive polarity)	—

68	SH7B	O	Sample-and-hold pulse 7B output (positive polarity)	—

69	TEST10	—	Test (Not connected.)	—

70	RCK	O	Read clock output (for line buffer)	—

– 4 –

				CXD2443Q


Pin	Symbol	I/O	Description	Input pin for
No.	Symbol	I/O	Description	open status
No.				open status

71	RSTR	O	Read reset output (for line buffer, negative polarity)	—

72	WCK	O	Write clock output (for line buffer)	—

73	RSTW	O	Write reset output (for line buffer, negative polarity)	—

74	CKO4	I/O	Oscillation cell 4 output (line double-speed controller)	—

75	CKI4	I	Oscillation cell 4 input (line double-speed controller)	—

76	RPD4	O	Phase comparator 4 output (line double-speed controller)	—

77	FPD4	O	Phase comparator 4 output (line double-speed controller)	—

78	VDD	—	Power supply	—

79	VSS	—	GND	—

80	PEO4	I/O	Loop filter integrator 4 output (line double-speed controller)	—

81	PWM4	O	Loop filter integrator 4 input (line double-speed controller)	—

82	TC4	I/O	FPD4 output pulse width adjustment (line double-speed controller)	—

83	TC2	I/O	FPD2 output pulse width adjustment (NTSC/PAL 16:9)	—

84	FPD2	O	Phase comparator 2 output (NTSC/PAL 16:9)	—

85	PEO2	I/O	Loop filter integrator 2 output (NTSC/PAL 16:9)	—

86	PWM2	O	Loop filter integrator 2 input (NTSC/PAL 16:9)	—

87	RPD2	O	Phase comparator 2 output (NTSC/PAL 16:9)	—

88	CKO2	I/O	Oscillation cell 2 output (NTSC/PAL 16:9)	—

89	CKI2	I	Oscillation cell 2 input (NTSC/PAL 16:9)	—

90	VSS	—	GND	—

91	CKO3	I/O	Oscillation cell 3 output (HD)	—

92	CKI3	I	Oscillation cell 3 input (HD)	—

93	RPD3	O	Phase comparator 3 output (HD)	—

94	PEO3	I/O	Loop filter integrator 3 output (HD)	—

95	PWM3	O	Loop filter integrator 3 input (HD)	—

96	FPD3	O	Phase comparator 3 output (HD)	—

97	TC3	I/O	FPD3 output pulse width adjustment (HD)	—

98	CKSL	I	PLL system switching (High: Built-in PLL, Low: External PLL)	H

99	CKI5	I	External clock input (for external phase comparison)	—

100	HDR	O	Phase comparator output (for external phase comparison)	—

			H: Pull up, L: Pull down

– 5 –

CXD2443Q

Electrical Characteristics

1. DC characteristics			(VDD = 5.0 ± 0.5V, VSS = 0V, Topr = –20 to +75°C)

Item	Symbol	Conditions	Min.	Typ.	Max.	Unit	Applicable pins

Supply voltage	VDD		4.5	5.0	5.5	V

Input, output voltages	VI, Vo		Vss		VDD	V

Input voltage 1	VIH	CMOS input	0.7VDD			V	1

	VIL				0.3VDD
	VIL				0.3VDD

	Vt+	TTL Schmitt	2.2				HSYNC, SCTR,
Input voltage 2
	Vt–				0.8	V
							VSYNC, SCLK,
		trigger input					VSYNC, SCLK,
		trigger input					SDAT
	Vt+ – Vt–			0.4			SDAT
	Vt+ – Vt–			0.4

	Vt+	CMOS Schmitt	0.8VDD
Input voltage 3							TC1, TC2, TC3,
	Vt–				0.2VDD	V	TC1, TC2, TC3,
	Vt–	trigger input			0.2VDD	V	TC4

	Vt+ – Vt–			0.6
	Vt+ – Vt–			0.6

Output voltage 1	VOH	IOH = –2mA	VDD – 0.8			V	2

	VOL	IOL = 4mA			0.4
	VOL	IOL = 4mA			0.4

Output voltage 2	VOH	IOH = –4mA	VDD – 0.8			V	3

	VOL	IOL = 8mA			0.4
	VOL	IOL = 8mA			0.4

Output voltage 3	VOH	IOH = –4mA	VDD – 0.8			V	RCK, WCK

	VOL	IOL = 6mA			0.4
	VOL	IOL = 6mA			0.4

Output voltage 4	VOH	IOH = –3mA	VDD/2			V	PEO1, PEO2, PEO3,
							PEO1, PEO2, PEO3,
	VOL	IOL = 3mA			VDD/2		PEO4, CKO4
	VOL	IOL = 3mA			VDD/2		PEO4, CKO4

Output voltage 5	VOH	IOH = –12mA	VDD/2			V	CKO1, CKO2,
							CKO1, CKO2,
	VOL	IOL = 12mA			VDD/2		CKO3
	VOL	IOL = 12mA			VDD/2		CKO3

	II	4	–10		10		5

Input leak current	IIL	6	–40	–100	–240	µA	7
Input leak current	IIL		–40	–100	–240	µA
	II	8	–40		40		9

Output leak current	IOZ	10	–40		40	µA	11

Current consumption	IDD	12			110	mA	At a 30pF load 13

456789

10111213

XCLR, PRE, CKSL, CKI1, CKI2, CKI3, CKI4, CKI5, CKO1, CKO2, CKO3, CKO4, PWM1, PWM2, PWM3, PWM4, PEO1, PEO2, PEO3, PEO4

HDR, ENB, PCG1, PCG2, XCLP1, XCLP2, VST, FRP, XFRP, VCK, DWN, FLDO, RGT, XRGT, VWA, VWB, RPD1, RPD2, RPD3, RPD4, FPD1, FPD2, FPD3, FPD4, TC1, TC2, TC3, TC4, RSTR, RSTW HSTA, HCK1A, HCK2A, SH1A, SH2A, SH3A, SH4A, SH5A, SH6A, SH7A, HSTB, HCK1B, HCK2B, SH1B, SH2B, SH3B, SH4B, SH5B, SH6B, SH7B

Normal input pins (VIN = VSS or VDD) HSYNC, VSYNC, SCLK, SDAT, SCTR, CKI5 Pins with pull-up resistors (VIN = VSS)

PRE, XCLR, CKSL

Bidirectional pins (input status, VIN = VSS or VDD)

CKO1, CKO2, CKO3, CKO4, PEO1, PEO2, PEO3, PEO4, TC1, TC2, TC3, TC4 At high impedance (VIN = VSS or VDD)

RPD1, RPD2, RPD3, RPD4, FPD1, FPD2, FPD3, FPD4 fclk = 67MHz, VDD = 5.5V

HSTA, HSTB, HCK1A, HCK2A, HCK1B, HCK2B, SH1A, SH2A, SH3A, SH4A, SH5A, SH6A, SH7A, SH1B, SH2B, SH3B, SH4B, SH5B, SH6B, SH7B, VCK, ENB, FRP, PCG1, PCG2, XCLP1, XCLP2, RGT, DWN

– 6 –

						CXD2443Q

2. AC characteristics		(VDD = 5.0 ± 0.5V, Vss = 0V, Topr = –20 to +75°C)

Item	Symbol	Applicable pins	Min.	Typ.	max.	Conditions	Unit

		CKI1	21.3

		CKI2	16.0

Clock input cycle		CKI3	15

		CKI4	28.2

		CKI5	15					ns

Output rise time	tr	All outputs			20	CL = 30pF
Output rise time	tr	All outputs			20	CL = 30pF

Output fall time	tf	All outputs			20	CL = 30pF

Cross-point time difference	t	1	–10		10	CL = 30pF
Cross-point time difference	t		–10		10	CL = 30pF

Output rise delay time	tpr	All outputs			15	CL = 30pF

Output fall delay time	tpf	All outputs			15	CL = 30pF

HCK1 Duty	tH/(tH + tL)	HCK1A, HCK1B	48		52	CL = 30pF
								%
HCK2 Duty	tL/(tH + tL)	HCK2A, HCK2B	48		52	CL = 30pF		%
HCK2 Duty	tL/(tH + tL)	HCK2A, HCK2B	48		52	CL = 30pF

1 HCK1A, 2A HCK1B, 2B

3. Serial transfer AC characteristics		(VDD = 5.0 ± 0.5V, Vss = 0V, Topr = –20 to +75°C)

Symbol	Item		Min.	Typ.	Max.	Unit

ts0	SCTR setup time, activated by rise of SCLK		4T

ts1	SDAT setup time, activated by rise of SCLK		2T

th0	SCTR hold time, activated by rise of SCLK		4T

th1	SDAT hold time, activated by rise of SCLK		2T			ns

tw1L	SCLK pulse width		2T
tw1L	SCLK pulse width		2T

tw1H	SCLK pulse width		2T

tw2			5T

tw3			5T

				T: Master clock cycle (ns)

– 7 –

CXD2443Q

4. Timing definitions

AC characteristics

CKI1, CKI2	100%
CKI1, CKI2
CKI3, CKI4
Output
Output

HCK1A

HCK1B

HCK2A

HCK2B

HCK1A

50%

HCK1B

VDD

tpr

90%

10%

VDD

90%

VDD

10%

tpf

VDD

50%50%

VDD

50% 50%

50%	50%
tH	tL

Note) HCK2 is the reverse phase of HCK1.

Serial transfer AC characteristics

	ts0						th0	tw3
SCTR	50%							50%
	tw1L		tw1H			tw2
SCLK	50%						50%
	ts1		th1		ts1	th1
SDAT	50%	D15	D14	D9	D8	D7	D0	D15

Note) See "Serial transfer timing" on P. 17 for the timing relationship between D15 to D0 and each pulse.

– 8 –

LCX011 Dot Arrangement (1) (4:3 display)

The dot arrangement is a delta arrangement. Also, the shaded region in the diagram is not displayed.

R1 corresponds to SIG2, G1 to SIG1, B1 to SIG3, R2 to SIG5, G2 to SIG4 and B2 to SIG6.

ODD = 1626 dots

EVEN = 1626 dots

ODD = 13 dots

ODD = 200 dots

ODD = 1200 dots

ODD = 200 dots

ODD = 13 dots

EVEN = 14 dots

EVEN = 200 dots

EVEN = 1199 dots

EVEN = 200 dots

EVEN = 13 dots

(effective 23.7501mm)

DL1

DL2

•

• •

•

• •

•

234

•

• •

•

267

•

• •

•

DR1

DR2

GATE SW

• • • •

GATE SW

dots2

–9–

dots480 6701mm).31(effective

479

480

dots

SID

PCX

VDD

VSS

WDX

JTN

JTP

CXD2443Q

LCX011 Dot Arrangement (2) (16:9 display)

The dot arrangement is a delta arrangement. Also, the shaded region in the diagram is not displayed.

R1 corresponds to SIG2, G1 to SIG1, B1 to SIG3, R2 to SIG5, G2 to SIG4 and B2 to SIG6.

ODD = 1626 dots

EVEN = 1626 dots

ODD = 13 dots

ODD = 1600 dots

ODD = 13 dots

EVEN = 14 dots

EVEN = 1599 dots

EVEN = 13 dots

(effective 31.6701mm)

DL1

DL2

•

• •

•

• •

•

234

•

• •

•

267

•

• •

•

DR1

DR2

GATE SW

• • • •

GATE SW

dots2

–10–

dots480 6701mm)(effective31.

479

480

dots2

SID

PCX

VDD

VSS

WDX

JTN

JTP

CXD2443Q

LCX019 Dot Arrangement

The dot arrangement is a delta arrangement. Also, the shaded region in the diagram is not displayed.

R1 corresponds to SIG2, G1 to SIG1, B1 to SIG3, R2 to SIG5, G2 to SIG4 and B2 to SIG6.

ODD = 1200 dots

EVEN = 1199 dots

DR1

DR2

201

DL2

DR1

GATE SW

dots2

– 11 –

dots480

dots2

R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B

1 R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B

2R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B

3 R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B

4R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B

R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B

R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B

479 R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B

480R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B

R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B R G B

PSIG

CXD2443Q

Input Signal Protocol

1. Horizontal sync signal

•A double-speed HSYNC or standard HSYNC (or CSYNC) should be input for NTSC and PAL display modes. Double-speed HSYNC and standard HSYNC input switching is set by the serial data (SNSL).

Note) The double-speed HSYNC should have a cycle and width 1/2 that of the standard HSYNC.

•The signal obtained by cutting off only the bottom of the ternary SYNC should be input for HD display mode.

•The input sync signal polarity is not fixed, and is set by the serial data (HPOL).

•When using the built-in line double-speed controller, set serial data SNSL to Low. The built-in line doublespeed controller supports only the standard HSYNC (or CSYNC).

2. Vertical sync signal

•A normal-speed VSYNC (or CSYNC) should be input for NTSC and PAL display modes.

•A VSYNC that has been sync separated by SYNC SEP. should be input for HD display mode.

•The input sync signal polarity is not fixed, and is set by the serial data (VPOL).

•The phase relationship between HSYNC and VSYNC is specified as follows for the CXD2443Q.

(1) Double-speed NTSC

Double-speed HSYNC

VSYNC Sync signal phase reference

(2) Double-speed PAL

Double-speed HSYNC

VSYNC Sync signal phase reference

(3) NTSC (CSYNC input)

ODD FIELD

CSYNC

EVEN FIELD

Sync signal phase reference

CSYNC

(4) PAL (CSYNC input)

ODD FIELD
CSYNC

EVEN FIELD	Sync signal phase reference
CSYNC

(5) HD

ODD FIELD

	HSYNC
	VSYNC	Sync signal phase
	VSYNC	reference
		reference
	EVEN FIELD
	HSYNC
	VSYNC	Sync signal phase
		reference
		– 12 –

CXD2443Q

Description of Operation

Clock input

The CXD2443Q supports two types of PLL circuits.

PLL switching is performed by CKSL (Pin 98). (High: Built-in PLL, Low: External PLL)

Note) The built-in line double-speed controller PLL is supported only by the built-in PLL.

(1)Built-in PLL (CKI1, CKI2, CKI3, CKI4)

A PLL circuit is comprised by the built-in phase comparator and an external VCO circuit. There are four clock inputs which support the following modes.

CKI1: NTSC/PAL 4:3 CKI2: NTSC/PAL 16:9

CKI3: HD CKI4: For built-in line double-speed controller

The PLL lock for this system is adjusted by setting the RPD and FPD transition points so that they fall at the center of the windows as shown in the diagram below. (See the Application Circuit.)

a a

HSYNC

RPD

b b

Output waveform during PLL lock FPD

800ns

(2)External PLL (CKI5)

The CKI5 pin is the clock input pin when using an external PLL IC. The 1/N frequency divider output is output from the HDR pin (frequency division ratio N/2) for the PLL IC. Set CKSL (Pin 98) to Low to switch to

the external PLL.

N fH

HSYNC

N/2 fH

HDR

AC driving of LCD panels for no signal

The following measures have been adopted to allow AC driving of LCD panels even when there is no signal.

•Horizontal direction pulse

The PLL is set to free running status. The frequency of the horizontal direction pulse at this time is dependent on the PLL free running frequency.

•Vertical direction pulse

The number of lines is counted by an internal counter and the vertical direction pulses (VST, FRP) are output at a specified cycle. For the CXD2443Q, no signal (free running) status is judged if there is no VSYNC input for longer than the following (free running detection) periods.

Mode	V cycle for no signal	Free running detection

NTSC	544H (272H)
		1024H (512H)
PAL	640H (320H)	1024H (512H)

HD	576H

Note) Numbers in parentheses are for when using the built-in line double-speed controller.

– 13 –

CXD2443Q

Right/left and/or up/down inversion

In delta arrangement LCD panels, the same signal lines are separated by 1.5 dots for each horizontal line. Therefore, a 1.5 dot offset is added between lines to the LCD's horizontal direction start pulses HST and HCK and sample-and-hold pulse (SH).

When driving an LCD panel with right and left inversed, the dot arrangement is asymmetrical so an offset is attached to HST, HCK and SH. When driving with up and down inversed, the relationship between the panel's odd and even line offsets is reversed.

MCK

HST

Down scan

SCANNERV

Up scan

Right scan

Left scan

H SCANNER

Effective display area

1.5fH 1.5fH

Down scan, odd line

Up scan, even line

Right and down scan, even line

Right and up scan, odd line

Left and down scan, even line

Left and up scan, odd line

– 14 –

CXD2443Q

When using three LCD panels

B outputs (HSTB, HCK1B, HCK2B, SH1B to 7B) are provided for driving three LCD panels with and without right/left inversion at the same time. These B outputs are the right/left inversed timings of the A outputs (HSTA, HCK1A, HCK2A, SH1A to 7A).

XRGT (RGT inversed output) is also provided for right/left inversion scanning.

Application circuit (driving three LCD panels)

Right scan (A outputs)

Left scan (B outputs)

Common

SH1A	51
SH2A	52	Panel 1
SH3A	55	(right scan)
SH3A	55
SH4A	56	SIGNAL DRIVER
SH5A	57
SH6A	58	SIGNAL DRIVER
SH7A	59
HSTA	43
HCK1A	38	Panel 2
HCK2A	37	(right scan)
HCK2A	37
RGT 44
SH1B	61
SH2B	62
SH3B	63
SH4B	64	SIGNAL DRIVER
SH5B	66	Panel 3
SH5B	66	(left scan)
SH6B	67
SH7B	68
HSTB	42
HCK1B	41
HCK2B	39
XRGT 45
DWN	32
ENB	36
VCK	35
PCG1	31
or
PCG2	46	Note) All three panels face the same direction.
VST	34

– 15 –

CXD2443Q

Built-in line double-speed controller

This controller is designed to use the µPD485505 (NEC/high-speed line buffer) as the system line memory IC, and generates the double-speed processing pulses RSTW (reset write), WCK (write clock), RSTR (reset read) and RCK (read clock).

Operation is as follows. Write operation is started at the RSTW timing, and this memory information is read twice at double speed at the RSTR timing which is delayed by 1/2H and 1H from the RSTW timing. The write and read clock frequencies at this time are generated by the built-in PLL (CKI4).

See the specifications for a detailed description of µPD485505 operation.

R, G, B IN	ADC			LINE Mem.		DAC
				LINE Mem.
				µPD485505
		RSTW			RSTR
		RSTW			RSTR
		WCK			RCK
	HSYNC			CXD2443Q
	VSYNC			CXD2443Q
	VSYNC
	CSYNC			MCK : f
				MCK : f
			Double-speed display system block

HSYNC

RSTW

WCK

f/2

RSTR

RCK

HSYNC

RSTW

RSTR

Double-speed display timing

Note) See the timing charts for details.

– 16 –

CXD2443Q

XCLR pin

The CXD2443Q should be forcibly reset during power on in order to initialize the serial transfer block and other internal circuits.

Serial transfer operation

1. Control method

The CXD2443Q operation timing is controlled by serial data.

The control data is comprised of an 8-bit address and 8-bit data, and the individual data is fetched at the rise of SCLK. This fetching operation starts from the fall of SCTR and is completed at the next rise of SCTR.

Serial transfer timing

SCTR

SCLK

SDAT

D15

D14

D13

D12

D11

D10

Address

Data

2. Control data

When using the CXD2443Q, set the control data corresponding to each signal source according to the formats in the table below.

				Address									Data					Function

	D15	D14D13			D12D11D10			D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
	D15	D14D13			D12D11D10			D9	D8	D7	D6	D5	D4	D3	D2	D1	D0

	0	0	0		0	0	0	0	0	HP8	HP7	HP6	HP5	HP4	HP3	HP2	HP1	(A) H-POSITION

	0	0	0		0	0	0	0	1	—	—	—	—	VP4	VP3	VP2	VP1	(B) V-POSITION

	0	0	0		0	0	0	1	0	—	—	—	—	SLSH4	SLSH3	SLSH2	SLSH1	(C) SH-POSITION

	0	0	0		0	0	0	1	1	—	—	—	—	—	—	CP2	CP1	(D) XCLP-POSITION

	0	0	0		0	0	1	0	0	—	—	—	—	—	—	PCGW2	PCGW1	(E) PCG-POSITION

	0	0	0		0	0	1	0	1	—	—	—	—	—	—	VM9J	VM8J

	0	0	0		0	0	1	1	0	VM7J	VM6J	VM5J	VM4J	VM3J	VM2J	VM1J	VM0J	(F) VWA-POSITION
	0	0	0		0	0	1	1	1	—	—	—	—	—	—	VM9K	VM8K	(VWA pulse)
	0	0	0		0	0	1	1	1	—	—	—	—	—	—	VM9K	VM8K

	0	0	0		0	1	0	0	0	VM7K	VM6K	VM5K	VM4K	VM3K	VM2K	VM1K	VM0K

	0	0	0		0	1	0	0	1	—	—	—	—	—	—	TEST1	SLBA	(G) Double-speed
																		setting
	0	0	0		0	1	0	1	0	—	—	—	—	—	—	MA	TEST2	(H) Double-speed
																		PAL pulse eliminate
	0	0	0		0	1	0	1	1	—	—	—	—	—	—	DWN	RGT	(I) Right/left and/or
	0	0	0		0	1	0	1	1	—	—	—	—	—	—	DWN	RGT	up/down inversion
																		up/down inversion

	0	0	0		0	1	1	0	0	—	—	TEST4	TEST3	SL3B	VPOL	HPOL	SLFR	(J) Various settings

	0	0	0		0	1	1	0	1	—	—	—	—	—	—	SLVWB	SLEG
	0	0	0		0	1	1	0	1	—	—	—	—	—	—	SLVWB	SLEG

	0	0	0		0	1	1	1	0	—	—	—	—	SNSL	XHD	XWID	NT-PAL	(K) Mode settings

Note)			1. Set "High" as the TEST1, TEST2, TEST3 and TEST4 data.
			2. "—" indicates not set.										– 17 –
													– 17 –

CXD2443Q

Serial settings during power on

The CXD2443Q should be forcibly reset during power on using the XCLR pin. After being forcibly reset, the master clock for the CXD2443Q is supplied from CKI3. The initial serial data after power on is loaded to the CXD2443Q using the clock from CKI3.

Serial settings during PLL free running

When the PLL is in free running status, the serial clock cycle (F ns) may be less than F ≥ 2T with respect to the master clock cycle (T ns). Take care that the serial clock cycle setting is such that F ≥ 2T during PLL free running.

Each control data is described in detail below.

(A)H-POSITION

(HP1, HP2, HP3, HP4, HP5, HP6, HP7, HP8)

These bits set the horizontal display start position. The minimum adjustment width is 1 dot, and adjustment of up to ±128 dots is possible with respect to the design center value. (data: 8 bits)

Design center value		HP1		HP2	HP3	HP4	HP5		HP6	HP7	HP8
			L	L	L	L		L	L	L	H

	MODE		Variable time (±128fH)

	NTSC (4:3)			±2.8µs

	NTSC (16:9)			±2.1µs

	PAL (4:3)			±2.7µs

	PAL (16:9)			±2.0µs

	HD			±1.9µs

(B)V-POSITION

(VP1, VP2, VP3, VP4)

These bits set the vertical display start position. The minimum adjustment width is 1H, and adjustment of up to ±8H is possible with respect to the design center value. (data: 4 bits)

Design center value VP1	VP2	VP3	VP4
L	L	L	H

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