Sony CXP85232A, CXP85228A, CXP85224A, CXP85220A, CXP85116B Datasheet
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CXP85112B/85116B
CXP85220A/85224A/85228A/85232A
CMOS 8-bit Single-chip Microcomputer
Description
The CXP85112B/85116B, CXP85220A/85224A/ 85228A/85232A is a CMOS 8-bit single chip microcomputer integrating on a single chip an A/D converter, serial interface, timer/counter, time base timer, vector interruption, on-screen display function, I2C bus interface, PWM generator, remote control reception circuit, HSYNC counter, power source frequency counter and watch dog timer besides the basic configurations of 8-bit CPU, ROM, RAM, and l/O port.
The CXP85112B/85116B, CXP85220A/85224A/ 85228A/85232A also provides a power-on reset function and a sleep function that enables lower power consumption.
64 pin SDIP (Plastic) |
64 pin QFP (Plastic) |
Structure
Silicon gate CMOS IC
Features
•Wide-range instruction system (213 instructions) to cover various types of data
— 16-bit arithmetic/multiplication and division/boolean bit operation instructions
• Minimum instruction cycle |
1µs at 4MHz operation |
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• Incorporated ROM capacity |
12K bytes (CXP85112B) |
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16K bytes (CXP85116B) |
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20K bytes (CXP85220A) |
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24K bytes (CXP85224A) |
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28K bytes (CXP85228A) |
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• Incorporated RAM capacity |
32K bytes (CXP85232A) |
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352 bytes (CXP85112B/85116B) |
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• Peripheral functions |
448 bytes (CXP85220A/85224A/85228A/85232A) |
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12 × 16 dots, 128 types |
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— On-screen display function |
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21 words × 4 Iines (more than 4 Iines possible) |
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Double scan mode compatible, jitter elimination circuit |
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— I 2C bus interface |
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— PWM output |
14 bits, 1 channel |
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6 bits, 8 channels |
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— Remote control reception circuit |
8-bit pulse measurement counter with on-chip 6-stage FIFO |
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— A/D converter |
4 bits, 4channels, successive approximation method |
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(Conversion time of 40µs/4MHz) |
—HSYNC counter
—Power supply frequency counter
—Watch dog timer
— Serial I/O |
8-bit clock synchronization |
— Timer |
8-bit timer, 8-bit timer/counter, 19-bit time base timer |
• Interruption |
14 factors, 14 vectors, multi-interruption possible |
• Standby mode |
Sleep |
• Package |
64-pin plastic SDIP/QFP |
• Piggyback/evaluation chip |
CXP85100A, CXP85190 (Custom font compatible) |
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CXP85200A, CXP85290 (Custom font compatible) |
Purchase of Sony's2IC components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E93Z17B86
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
SS |
V |
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DD |
V |
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PM |
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TSR |
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LATX |
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LATXE |
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/0DPINT2 1TNI/1EP /0EPINT0
PA0 to PA7 |
PB0 to PB7 |
PC0 to PC7 |
PD0 to PD7 |
PE0 to PE5 |
PE6 to PE7 |
PF0 to PF7 |
A TROP |
B TROP |
C TROP |
D TROP |
E TROP |
F TROP |
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CLOCK GEN./ |
SYSTEM CONTROL |
RAM 352/448 BYTES |
PRESCALER/ |
TIME BASE TIMER |
SPC700 |
CPU CORE |
ROM 12K/16K/20K/24K/28K/32K BYTES |
WATCHDOG TIMER |
6 BIT PWM 8CH |
RELLORTNOC TPURRETNI |
14 BIT PWM |
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2 |
2 |
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7MWP/7FP ot 0MWP/0FP
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SCREENONDISPLAY |
SERIALI/O |
TIMER/COUNTER |
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REMOCONFIFO |
COUNTERHSYNC |
TIMERAC |
CONVERTERA/D |
I |
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INTERFACEC UNIT |
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2 |
Block Diagram |
EXLC XLC B G R BLK HSYNC VSYNC |
PD3/SI PD2/SO PD1/SCK |
PD7/EC |
PE7/TO |
PD6/RMC |
PD4/HSI |
PD5/ACI |
PE2/AN0 to PE5/AN3 |
PF4/SCL0 PF5/SCL1 PF6/SDA0 PF7/SDA1 |
– 2 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Pin Assignment 1 (Top View) 64 pin SDIP Package
PA7 |
1 |
64 |
VDD |
PA6 |
2 |
63 |
NC |
PA5 |
3 |
62 |
VSS |
PA4 |
4 |
61 |
MP |
PA3 |
5 |
60 |
PF0/PWM0 |
PA2 |
6 |
59 |
PF1/PWM1 |
PA1 |
7 |
58 |
PF2/PWM2 |
PA0 |
8 |
57 |
PF3/PWM3 |
PB7 |
9 |
56 |
PF4/PWM4/SCL0 |
PB6 |
10 |
55 |
PF5/PWM5/SCL1 |
PB5 |
11 |
54 |
PF6/PWM6/SDA0 |
PB4 |
12 |
53 |
PF7/PWM7/SDA1 |
PB3 |
13 |
52 |
BLK |
PB2 |
14 |
51 |
R |
PB1 |
15 |
50 |
G |
PB0 |
16 |
49 |
B |
PC7 |
17 |
48 |
VSYNC |
PC6 |
18 |
47 |
HSYNC |
PC5 |
19 |
46 |
EXLC |
PC4 |
20 |
45 |
XLC |
PC3 |
21 |
44 |
PE0/INT0 |
PC2 |
22 |
43 |
PE1/INT1 |
PC1 |
23 |
42 |
PE2/AN0 |
PC0 |
24 |
41 |
PE3/AN1 |
PD7/EC |
25 |
40 |
PE4/AN2 |
PD6/RMC |
26 |
39 |
PE5/AN3 |
PD5/ACI |
27 |
38 |
PE6/PWM |
PD4/HSI |
28 |
37 |
PE7/TO |
PD3/SI |
29 |
36 |
RST |
PD2/SO |
30 |
35 |
EXTAL |
PD1/SCK |
31 |
34 |
XTAL |
VSS |
32 |
33 |
PD0/INT2 |
Note) 1. NC (Pin 63) must be connected to VDD.
2.Vss for both Pins 32 and 62 must be grounded.
3.MP (Pin 61) must be connected to GND.
–3 –
CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
Pin Assignment 2 (Top View) 64 pin QFP Package
2AP |
3AP |
4AP |
5AP |
6AP |
7AP |
VSS |
VDD |
CN |
PM |
0MW P/0F P |
1MW P/1F P |
2MW P/2F P |
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64 |
63 |
62 |
61 |
60 |
59 |
58 |
57 |
56 |
55 |
54 |
53 |
52 |
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PA1 |
1 |
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51 |
PF3/PWM3 |
PA0 |
2 |
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50 |
PF4/PWM4/SCL0 |
PB7 |
3 |
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49 |
PF5/PWM5/SCL1 |
PB6 |
4 |
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48 |
PF6/PWM6/SDA0 |
PB5 |
5 |
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47 |
PF7/PWM7/SDA1 |
PB4 |
6 |
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46 |
BLK |
PB3 |
7 |
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45 |
R |
PB2 |
8 |
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44 |
G |
PB1 |
9 |
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43 |
B |
PB0 |
10 |
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42 |
VSYNC |
PC7 |
11 |
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41 |
HSYNC |
PC6 |
12 |
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40 |
EXLC |
PC5 |
13 |
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39 |
XLC |
PC4 |
14 |
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38 |
PE0/INT0 |
PC3 |
15 |
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37 |
PE1/INT1 |
PC2 |
16 |
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36 |
PE2/AN0 |
PC1 |
17 |
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35 |
PE3/AN1 |
PC0 |
18 |
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34 |
PE4/AN2 |
PD7/EC |
19 |
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33 |
PE5/AN3 |
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20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
28 |
29 |
30 |
31 |
32 |
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CMR /6D P |
ICA /5D P |
ISH /4D P |
IS/3 DP |
OS/2 DP |
KCS /1D P |
SS V
2TN I/0D P |
LAT X |
LAT XE |
TSR |
OT/7 EP |
MWP /6E P |
Note) 1. NC (Pin 56) must be connected to VDD.
2.Vss for both Pins 26 and 58 must be grounded.
3.MP (Pin 55) must be connected to GND.
–4 –
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CXP85112B/85116B, CXP85220A/85224A/85228A/85232A |
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Pin Description |
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Symbol |
I/O |
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Description |
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(Port A) |
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PA0 to PA7 |
I/O |
8-bit I/O port. I/O can be set in a unit of single bits. |
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(8 pins) |
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(Port B) |
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PB0 to PB7 |
I/O |
8-bit I/O port. I/O can be set in a unit of single bits. |
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(8 pins) |
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(Port C) |
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PC0 to PC7 |
I/O |
8-bit I/O port. I/O can be set in a unit of single bits. |
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(8 pins) |
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External interruption request input. |
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PD0/INT2 |
I/O/Input |
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Active at falling edge. |
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I/O/I/O |
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Serial clock I/O. |
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PD1/SCK |
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(Port D) |
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Serial data output. |
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PD2/SO |
I/O/Output |
8-bit I/O port. |
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I/O can be set ina a |
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PD3/SI |
I/O/Input |
Serial data input. |
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unit of single bits. |
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HSYNC counter input. |
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PD4/HSI |
I/O/Input |
Capable of driving |
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12mA sink current. |
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PD5/ACI |
I/O/Input |
Input for power supply frequency counter. |
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(8 pins) |
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PD6/RMC |
I/O/Input |
Input for remote control reception circuit. |
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I/O/Input |
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External event input for timer/counter. |
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PD7/EC |
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External interruption request inputs. |
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PE0/INT0 |
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Input/Input |
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Active at falling edge. |
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PE1/INT1 |
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(2 pins) |
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PE2/AN0 |
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(Port E) |
Analog inputs for A/D converter. |
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to |
Input/Input |
8-bit port. Lower |
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(4 pins) |
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PE5/AN3 |
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6 bits are for inputs; |
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upper 2 bits are for |
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14-bit PWM output. |
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PE6/PWM |
Output/Output |
outputs. |
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(CMOS output) |
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PE7/TO |
Output/Output |
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Rectangular waveform output for Timer 1. |
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(Duty output 50%) |
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PF0/PWM0 |
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(Port F) |
6-bit PWM outputs. |
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to |
Output/Output |
8-bit output port, |
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(8 pins) |
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PF3/PWM3 |
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operating as N-ch |
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open drain output |
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PF4/PWM4/ |
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for high current |
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Transfer clock I/Os for I2C bus |
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SCL0 |
Output/Output/ |
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(12mA). |
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PF5/PWM5/ |
I/O |
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interface. |
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Lower 4 bits are |
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SCL1 |
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medium voltage |
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PF6/PWM6/ |
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drive outputs (12V), |
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SDA0 |
Output/Output/ |
upper 4bits are 5V |
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Transfer data I/Os for I2C data bus. |
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PF7/PWM7/ |
I/O |
drive outputs. |
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SDA1 |
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(8 pins) |
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R, G, B, BLK |
Output |
4-bit outputs for CRT display. |
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HSYNC |
Input |
Horizontal synchronizing signal input for CRT display. |
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VSYNC |
Input |
Vertical synchronizing signal input for CRT display. |
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– 5 –
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CXP85112B/85116B, CXP85220A/85224A/85228A/85232A |
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Symbol |
I/O |
Description |
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EXLC |
Input |
Clock oscillation I/Os for CRT display. |
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XLC |
Output |
Oscillation frequency is set using the external L and C. |
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EXTAL |
Input |
Crystai connectors for system clock oscillation. When the clock is |
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supplied externally, input to EXTAL; opposite phase clock should be |
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XTAL |
Output |
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input to XTAL. |
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I/O |
Low-level active, system reset. |
RST |
is an I/O, from whlch Low level is |
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RST |
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output when the built-in power-on reset function is activated at the rise |
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of power on. (Mask option) |
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MP |
Input |
Microprocessor mode input. For this device, this pin must be grounded. |
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VDD |
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Vcc supply. |
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Vss |
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GND. Both Vss must be grounded. |
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– 6 –
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