Philips LVT22V10-DN, LVT22V10-DD, LVT22V10-DA, LVT22V10-BN, LVT22V10-BD Datasheet

INTEGRATED CIRCUITS

LVT22V10

3V high speed, universal PLD device

Product specification

1998 Feb 10

Supersedes data of 1996 Mar 12

IC13 Data Handbook

m n r

Philips Semiconductors	Product specification
3V high speed, universal PLD device	LVT22V10

FEATURES

•Fastest 3V PLD

•Supports 3/5V mixed systems

•Low ground bounce (<1.1V worst case)

•Live insertion/extraction permitted

•Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs

•Metastable hardened device

•High output drive capability: 32mA/±16mA

•Varied product term distribution with up to 16 product terms per output for complex functions

•Programmable output polarity

•Available in 300 mil-wide 24-pin Plastic Small Outline Package

•Design support provided for third party CAD development and programming hardware

DESCRIPTION

The LVT22V10 is a versatile PAL device fabricated on the Philips BiCMOS QUBiC process.

The QUBiC process produces very high speed 3V devices (7.5ns) which have excellent noise characteristics. Ground bounce of an output held low while the remaining 9 outputs switch from high to low is typically less than 0.7V. VCC bounce of an output held high while the remaining 9 outputs switch from low to high is typically less than 1.0V.

The LVT22V10 was designed to support mixed 3/5V systems. The inputs are capable of handling 7V while the outputs can be pulled up to 7V.

The designer can interface directly from 5V outputs (CMOS full rail or totem pole) to a 3V LVT input. A 3V LVT output can drive a 5V TTL input directly, or in the case of a CMOS input, the LVT output can interface with the use of an external pull-up resistor. Finally, no external pull-up resistors are needed on unused input pins due to a bus-hold data structure designed into the LVT input.

The LVT22V10 has been designed with high drive outputs (32mA sink and 16mA source currents), which allows for direct connection to a backplane bus. This feature eliminates the need for additional, standalone bus drivers, which are traditionally required to boost the drive of a standard PLDs.

The LVT22V10 outputs are designed to support Live Insertion/Extraction into powered up systems. The output is specially designed so that during VCC ramp, the output remains 3-Stated until VCC 2.1V. At that time the outputs become fully functional depending upon device inputs. (See DC Electrical

Characteristics, Symbol IPU/PD, Page 5). In addition when an LVT22V10 output is tied to a 5V bus, no bus current is loaded.

The LVT22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations.

This device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an ªOutput Macro Cellº (OMC) which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.

PIN CONFIGURATIONS

D and N Packages

I0/CLK	1		24	VCC
				F9
I1	2		23
				F8
I2	3		22
				F7
I3	4		21
				F6
I4	5		20
				F5
I5	6		19
				F4
I6	7		18
				F3
I7	8		17
				F2
I8	9		16
				F1
I9	10		15
				F0
I10	11		14
				I11
GND	12		13

N = Plastic Dual In-Line Package (300mil-wide)

D = Plastic Small Outline Large (300mil-wide) Package

A Package (standard)

			I2	I1	CLK/	NC	VCC F9		F8
					I0
			4	3	2	1	28	27	26
I3	5									25	F7
I4	6									24	F6
I5	7									23	F5
NC	8									22 NC
I6	9									21	F4
GND	10									20	F3
I8	11									19	F2
	12			13	14	15	16	17	18
			I9	I10 GND NC I11				F0	F1

A = Plastic Leaded Chip Carrier

A Package (evolutionary)

CLK/

I2 I1 I0 VCCVCC F9 F8

4 3 2 1 28 27 26

I3	5								25	F7
I4	6								24	F6
I5	7								23	F5
GND	8								22	GND
I6	9								21	F4
I7	10								20	F3
I8	11								19	F2
	12		13	14	15	16	17	18
		I9	I10 GNDGND I11 F0					F1

A = Plastic Leaded Chip Carrier

SP00436

PAL is a registered trademark of Advanced Micro Devices, Inc.

1998 Feb 10

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853-1759 18947

Philips Semiconductors	Product specification
3V high speed, universal PLD device	LVT22V10

ORDERING INFORMATION

PACKAGES	ORDER CODE		DWG NUMBER
24-Pin Plastic DIP (300mil)	LVT22V10-7N	(8.0ns device)	SOT222-1
28-Pin PLCC (standard pinout)	LVT22V10B7A	(7.5ns device)	SOT261-3
28-Pin PLCC (evolutionary pinout)	LVT22V10-7A	(7.5ns device)	SOT261-3
24-Pin Plastic SOL	LVT22V10-7D	(8.0ns device)	SOT137-1

PIN LABEL DESCRIPTIONS

SYMBOL	DESCRIPTION
I1 ± I11	Dedicated Input
F0 ± F9	Macro Cell Input/Output
CLK/I0	Clock Input/Dedicated Input
VCC	Supply Voltage
GND	Ground
NC	No Connection

THERMAL RATINGS

TEMPERATURE

Maximum junction	150°C
Maximum ambient	75°C
Allowable thermal rise ambient to junction	75°C

OPERATING RANGES

	SYMBOL	PARAMETER	RATINGS		UNIT
			MIN	MAX
	VCC	Supply voltage	+3.0	+3.6	VDC
	Tamb	Operating free-air	0	+75	°C
		temperature

ABSOLUTE MAXIMUM RATINGS1

SYMBOL		PARAMETER	RATINGS		UNIT
			MIN	MAX
V	Supply voltage2		±0.5	+4.6	V	DC
CC
V	Input voltage2		±0.5	7	V	DC
IN
V	Output voltage3		±0.5	5.5	V	DC
OUT
IIN	Input currents		±30	+30	mA
IOUT	Output currents			+100	mA
Tstg	Storage temperature range		±65	+150	°C

NOTES:

1.Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied.

2.Except in programming mode.

3.Outputs can be pulled up to 7V via external pull-up resistor.

1998 Feb 10

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Philips Semiconductors	Product specification
3V high speed, universal PLD device	LVT22V10

TEST CIRCUIT AND WAVEFORMS

6.0V

		VCC
				OPEN	90%	tW	AMP (V)
							90%
	VIN	VOUT	RL	GND	NEGATIVE	VM	VM
PULSE					PULSE	10%	10%
		D.U.T.
							0V
GENERATOR
	RT	CL	RL			tTHL (tF)	tTLH (tR)
						tTLH (tR)	tTHL (tF)
						90%	AMP (V)
	Test Circuit for 3-State Outputs						90%
					POSITIVE	VM	VM
					PULSE
SWITCH POSITION					10%	tW	10%
TEST	SWITCH						0V
						VM = 1.5V
tPLH/tPHL	Open
						Input Pulse Definition
tPLZ/tPZL	6V
tPHZ/tPZH	GND

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value.

RT = Termination resistance should be equal to ZOUT of pulse generators.

	FAMILY	INPUT PULSE REQUIREMENTS
		Amplitude	Rep. Rate	tW	tR	tF
	LVT	3.0V	10MHz	500ns	2.5ns	2.5ns

SP00385

1998 Feb 10

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Philips Semiconductors	Product specification
3V high speed, universal PLD device	LVT22V10

DC ELECTRICAL CHARACTERISTICS

Over operating ranges.

SYMBOL

PARAMETER

TEST CONDITIONS1

LIMITS

UNIT

MIN

MAX

Input voltage

VIL

Low

VCC = MIN

0.8

V

VIH

High

VCC = MAX

2.0

V

VI

Clamp

VCC = MIN, IIN = ±18mA

±1.2

V

Output voltage

VCC = MIN to MAX, VI = VIH or VIL

IOH = ±100 μA

VCC±0.2

V

VOH

High-level output voltage

VCC = MIN, VI = VIH

or VIL

IOH = ±16mA

2.0

V

IOH = ±5.5 mA

2.4

V

VCC = MIN to MAX, VI = VIH or VIL

IOL = 100μA

0.2

V

VOL

Low-level output voltage

VCC = MIN, VI = VIH or VIL

IOL = 32 mA

0.5

V

IOL = 16 mA

0.4

V

Input current

IIL

Low

VCC = MAX, VIN = 0.0V

±10

μA

IIH

High

VCC = MAX, VIN = VCC

10

μA

II

Max input current

VCC = MAX, VIN = 5.5V

10

μA

II

Pin 1 (program)

VCC = MAX, VIN = 5.5V

20

μA

I

Bus hold low sustaining current2

V

CC

= 3V, V

= 0.8V

75

μA

BHL

I

I

Bus hold high sustaining current3

V

CC

= 3V, V

I

= 2V

±75

μA

BHH

I

Bus hold low overdrive current4, 9

V

CC

= 3.6V

500

μA

BHLO

I

Bus hold high overdrive current5, 9

V

CC

= 3.6V

±500

μA

BHHO

Output current

IOFF

Output off current

VCC = 0V, VI or VO = 0 to 4.5V

±10

μA

IEX

Current into an output in high state

VO = 5.5V, VCC = 3.0V

±100

μA

when VO > VCC

IPU/PD

Power-up/down 3-State output

VCC <1.2V; VO = 0.5V to VCC;

100

μA

current8

V = GND or V

= X

CC

; OE/OE

I

VCC = MAX

I

Output leakage6

V

= V

IL

or V

IH

, V

OUT

= 5.5V

10

μA

OZH

IN

I

Output leakage6

V

IN

= V

IL

or V

IH

, V

OUT

=0V

±10

μA

OZL

I

Short circuit7

V

= 0.5V

±30

±220

mA

SC

OUT

ICC

VCC supply current

VCC = 3.6V, Outputs enabled, VI = VCC or GND; IO = 0

170

mA

Ground/VCC Bounce

MIN

TYP

MAX

UNIT

VOHV

Maximum dynamic VOH

VCC = 3.0V, 25°C,

2.2

2.3

V

CL = 50pF (including jig capacitance)

VOLP

Maximum dynamic VOL

VCC = 3.3V, 25°C, CL = 50pF

LVT22V10-7

0.7

1.1

V

(including jig capacitance)

LVT22V10B7

1.0

1.1

V

NOTES:

1.These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.

2.The bus hold circuit can sink at least the minimum low sustaining current at VIL MAX. IBHL should be measured after lowering VIN to GND and then raising it to VIL MAX.

3.The bus hold circuit can source at least the minimum high sustaining current at VIH MIN. IBHL should be measured after raising VIN to VCC and then lowering it to VIH MIN.

4.An external driver must source at least IBHLO to switch this node from low to high.

5.An external driver must sink at least IBHHO to switch this node from high to low.

6.I/O pin leakage is the worst case of IOZX or IIX (where X = H or L).

7.No more than one output should be tested at a time. Duration of the short-circuit test should not exceed one second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation.

8.This parameter is valid for any VCC between 0V and 1.2 V with a transition time up to 10 mS. From VCC = 1.2 to VCC = 3.3V ±0.3V a transition time of 100 μS is permitted. X = Don't care.

9.These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where input current may be affected.

1998 Feb 10

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Philips Semiconductors	Product specification
3V high speed, universal PLD device	LVT22V10

AC ELECTRICAL CHARACTERISTICS

Over commercial operating temperature range.

SYMBOL

PARAMETER

TEST CONDITIONS1

LIMITS

UNIT

MIN

TYP

MAX

Input or feedback to non-registered output2

Active-LOW

7.5

ns

tPD

PLCC package

Active-HIGH

7.5

ns

Input or feedback to non-registered output2

Active-LOW

8.0

ns

DIP and SOL packages

Active-HIGH

8.0

ns

tS

Setup time from input, feedback or SP to Clock

5.5

ns

tH

Hold time

0

ns

tCO

Clock to output

5.0

ns

t

Clock to feedback3

3.0

ns

CF

tAR

Asynchronous Reset to registered output

12.0

ns

tARW

Asynchronous Reset width

5.0

ns

tARR

Asynchronous Reset recovery time

5.0

ns

tSPR

Synchronous Preset recovery time

5.0

ns

tWL

Width of Clock LOW

3.0

ns

tWH

Width of Clock HIGH

3.0

ns

Maximum frequency;

)4

95

MHz

External feedback 1/(t

S

+ t

fMAX

CO

Maximum frequency;

)4

118

MHz

Internal feedback 1/(t

S

+ t

CF

t

Input to Output Enable5

8.5

ns

EA

t

Input to Output Disable5

8.5

ns

ER

Capacitance6

CIN

Input Capacitance (Pin 1)

VIN = 2.0V

VCC = 3.3V,

6

pF

VIN = 2.0V

Input Capacitance (Others)

Tamb = 25°C,

6

pF

f = 1MHz

COUT

Output Capacitance

VOUT = 2.0V

8

pF

NOTES:

1.Test Conditions: R1 = 500Ω, R2 =500Ω

2.tPD is tested with switch S1 open and CL = 50pF (including jig capacitance). VIH = 3V, VIL = 0V, VT = 1.5V.

3.Calculated from measured fMAX internal.

4.These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected.

5.For 3-State output; output enable times are tested with CL = 50pF to the 1.5V level, and S1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with CL = 5pF. High-to-High impedance tests are made to an output voltage of VT = (VOH ± 0.3V) with S1 open, and Low-to-High impedance tests are made to the VT = (VOL + 0.3V) level with S1 closed.

6.These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected.

1998 Feb 10

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