INTEGRATED CIRCUITS
LPC2114/2124/2212/2214
USER MANUAL
Preliminary |
2004 May 03 |
Supersedes data of 2004 Feb 03 |
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P s
on o s
Philips Semiconductors |
Preliminary User Manual |
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ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
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2 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
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Table of Contents |
List of Figures . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 |
List of Tables . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 |
Document Revision History . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 |
Introduction . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 |
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ARM7TDMI-S Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 On-Chip Flash Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 On-Chip Static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 LPC2114/2124/2212/2214 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
LPC2114/2124/2212/2214 Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
33 |
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
33 |
LPC2114/2124/2212/2214 Memory Re-mapping and Boot Block . . . . . . . . . . . . . . . . . . . . . . . . . |
37 |
Prefetch Abort and Data Abort Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
40 |
External Memory Controller (EMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
41 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Typical Bus Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
External Memory Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
System Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
49 |
Summary of System Control Block Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
External Interrupt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Memory Mapping Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PLL (Phase Locked Loop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Power Control Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
VPB Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Wakeup Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Memory Accelerator Module (MAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
73 |
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Memory Accelerator Module Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
MAM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
MAM Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
Vectored Interrupt Controller (VIC) . . . . . . . . . . . . . . . . . . . . . . . . |
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Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
VIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Spurious Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
VIC Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
93 |
LPC2114/2124 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Pin Description for LPC2114/2124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 LPC2212/2214 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Pin Description for LPC2212/2214 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Pin Connect Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Boot Control on 144-pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
115 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
GPIO Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
UART0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
147 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
4 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
|
|
ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
|
|
Timer0 and Timer1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Example Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Pulse Width Modulator (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
179 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
193 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Pin DescriptionS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
197 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
197 |
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
197 |
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
198 |
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
198 |
RTC Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
200 |
Miscellaneous Register Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
201 |
Consolidated Time Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
204 |
Time Counter Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
206 |
Alarm Register Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
207 |
RTC Usage Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
207 |
Reference Clock Divider (Prescaler) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
208 |
Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
211 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Usage Notes on Watchdog Reset and External Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Flash Memory System and Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Flash Memory System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Flash boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Boot process FlowChart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Sector Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Code Read Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 JTAG FLASH Programming interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240
5 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
EmbeddedICE Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . 241 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Reset State of Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
245 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Reset State of Multiplexed Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
249 |
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
249 |
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
249 |
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
249 |
How to Enable RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
253 |
RealMonitor build options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
259 |
6 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
|
|
ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
|
|
List of Figures
Figure 1: LPC2114/2124/2212/2214 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 2: System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 3: Peripheral Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 4: AHB Peripheral Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 5: VPB Peripheral Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 6: Map of lower memory is showing re-mapped and re-mappable areas (128 kB Flash). . . . . . . . 39 Figure 7: 32 Bit Bank External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 8: 16 Bit Bank External Memory Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 9: 8 Bit Bank External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 10: External memory read access (WST1=0 and WST1=1 examples) . . . . . . . . . . . . . . . . . . . . . . 46 Figure 11: External memory write access (WST2=0 and WST2=1 examples) . . . . . . . . . . . . . . . . . . . . . . 46 Figure 12: Oscillator modes and models: a) slave mode of operation, b) oscillation mode of operation,
c) external crystal model used for CX1/X2 evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Figure 13: FOSC selection algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Figure 14: External Interrupt Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Figure 15: PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Figure 16: Reset Block Diagram including Wakeup Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 17: VPB Divider Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 18: Simplified Block Diagram of the Memory Accelerator Module . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 19: Block Diagram of the Vectored Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 20: LPC2114/2124 64-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Figure 21: LPC2212/2214 144-pin package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Figure 22: UART0 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Figure 23: UART1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Figure 24: I2C Bus Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 25: Slave Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Figure 26: Format in the master transmitter mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 27: Format of master receiver mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 28: A master receiver switch to master transmitter after sending repeated START. . . . . . . . . . . . 150 Figure 29: Slave Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Figure 30: Format of slave receiver mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Figure 31: Format of slave transmitter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Figure 32: I2C Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Figure 33: SPI Data Transfer Format (CPHA = 0 and CPHA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Figure 34: SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Figure 35: A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled.. . . 176 Figure 36: A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled. . . . 176 Figure 37: Timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Figure 38: PWM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Figure 39: Sample PWM waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Figure 40: RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Figure 41: RTC Prescaler block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Figure 42: Watchdog Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Figure 43: Map of lower memory after any reset (128 kB Flash part).. . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Figure 44: Boot Process flowchart (Bootloader revisions before 1.61) . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Figure 45: Boot Process flowchart (Bootloader revisions 1.61 and later) . . . . . . . . . . . . . . . . . . . . . . . . . 222 Figure 46: IAP Parameter passing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Figure 47: EmbeddedICE Debug Environment Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Figure 48: ETM Debug Environment Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Figure 49: RealMonitor components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Figure 50: RealMonitor as a state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Figure 51: Exception Handlers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254
7 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
|
|
ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
|
|
8 |
May 03, 2004 |
Philips Semiconductors |
|
|
Preliminary User Manual |
ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
||
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List of Tables |
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Table 1: |
LPC2114/2124/2212/2214 device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 16 |
|
Table 2: |
LPC2114/2124/2212/2214 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 20 |
|
Table 3: |
ARM Exception Vector Locations. |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . 37 |
Table 4: |
LPC2114/2124/2212/2214 Memory Mapping Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 37 |
|
Table 5: |
Address Ranges of External Memory Banks (LPC2212/2214 only) . . . . . . . . . . . . . . . . . |
. . . . . 41 |
|
Table 6: |
External Memory Controller Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 42 |
|
Table 7: |
External Memory Controller Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 42 |
|
Table 8: |
Bank Configuration Registers 0-3 |
(BCFG0-3 - 0xFFE00000-0C) . . . . . . . . . . . . . . . . . . . |
. . . . . 43 |
Table 9: |
Default memory widths at Reset . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 43 |
Table 10: External memory and system requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 47 |
||
Table 11: Pin summary . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 49 |
|
Table 12: Summary of System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 51 |
||
Table 13: Recommended values for CX1/X2 in oscillation mode |
|
||
|
(crystal and external components parameters) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 52 |
|
Table 14: External Interrupt Registers . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 54 |
|
Table 15: External Interrupt Flag Register (EXTINT - 0xE01FC140). . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 55 |
||
Table 16: External Interrupt Wakeup Register (EXTWAKE - 0xE01FC144) . . . . . . . . . . . . . . . . . . . |
. . . . . 56 |
||
Table 17: External Interrupt Mode Register (EXTMODE - 0xE01FC148) . . . . . . . . . . . . . . . . . . . . . |
. . . . . 56 |
||
Table 18: External Interrupt Polarity Register (EXTPOLAR - 0xE01FC14C). . . . . . . . . . . . . . . . . . . |
. . . . . 57 |
||
Table 19: MEMMAP Register. . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 59 |
|
Table 20: Memory Mapping Control Register (MEMMAP - 0xE01FC040). . . . . . . . . . . . . . . . . . . . . |
. . . . . 59 |
||
Table 21: PLL Registers. . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 60 |
|
Table 22: PLL Control Register (PLLCON - 0xE01FC080) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 62 |
||
Table 23: PLL Configuration Register (PLLCFG - 0xE01FC084) . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 62 |
||
Table 24: PLL Status Register (PLLSTAT - 0xE01FC088) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 63 |
||
Table 25: PLL Control Bit Combinations . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 63 |
|
Table 26: PLL Feed Register (PLLFEED - 0xE01FC08C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 64 |
||
Table 27: PLL Divider Values. . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 65 |
|
Table 28: PLL Multiplier Values . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 65 |
|
Table 29: Power Control Registers . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 66 |
|
Table 30: Power Control Register (PCON - 0xE01FC0C0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 66 |
||
Table 31: Power Control for Peripherals Register for LPC2114/2124 (PCONP - 0xE01FC0C4) . . . |
. . . . . 67 |
||
Table 32: Power Control for Peripherals Register for LPC2212/2214 (PCONP - 0xE01FC0C4) . . . |
. . . . . 67 |
||
Table 33: VPBDIV Register Map . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 70 |
|
Table 34: VPB Divider Register (VPBDIV - 0xE01FC100). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 70 |
||
Table 35: MAM Responses to Program Accesses of Various Types. . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 75 |
||
Table 36: MAM Responses to Data and DMA Accesses of Various Types. . . . . . . . . . . . . . . . . . . . |
. . . . . 75 |
||
Table 37: Summary of System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 76 |
||
Table 38: MAM Control Register (MAMCR - 0xE01FC000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 77 |
||
Table 39: MAM Timing Register (MAMTIM - 0xE01FC004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 77 |
||
Table 40: VIC Register Map. . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . 80 |
|
Table 41: Software Interrupt Register (VICSoftInt - 0xFFFFF018, Read/Write) . . . . . . . . . . . . . . . . |
. . . . . 82 |
||
Table 42: Software Interrupt Clear Register (VICSoftIntClear - 0xFFFFF01C, Write Only). . . . . . . . |
. . . . . 82 |
||
Table 43: Raw Interrupt Status Register (VICRawIntr - 0xFFFFF008, Read-Only) . . . . . . . . . . . . . . |
. . . . . 82 |
||
Table 44: Interrupt Enable Register (VICINtEnable - 0xFFFFF010, Read/Write) . . . . . . . . . . . . . . . |
. . . . . 83 |
||
Table 45: Software Interrupt Clear Register (VICIntEnClear - 0xFFFFF014, Write Only) . . . . . . . . . |
. . . . . 83 |
||
Table 46: Interrupt Select Register (VICIntSelect - 0xFFFFF00C, Read/Write) . . . . . . . . . . . . . . . . |
. . . . . 83 |
||
Table 47: IRQ Status Register (VICIRQStatus - 0xFFFFF000, Read-Only) . . . . . . . . . . . . . . . . . . . |
. . . . . 83 |
||
Table 48: IRQ Status Register (VICFIQStatus - 0xFFFFF004, Read-Only) . . . . . . . . . . . . . . . . . . . |
. . . . . 84 |
||
Table 49: Vector Control Registers (VICVectCntl0-15 - 0xFFFFF200-23C, Read/Write) . . . . . . . . . |
. . . . . 84 |
||
Table 50: Vector Address Registers (VICVectAddr0-15 - 0xFFFFF100-13C, Read/Write) . . . . . . . . |
. . . . . 84 |
||
Table 51: Default Vector Address Register (VICDefVectAddr - 0xFFFFF034, Read/Write) . . . . . . . |
. . . . . 84 |
||
Table 52: Vector Address Register (VICVectAddr - 0xFFFFF030, Read/Write) . . . . . . . . . . . . . . . . |
. . . . . 85 |
||
Table 53: Protection Enable Register (VICProtection - 0xFFFFF020, Read/Write). . . . . . . . . . . . . . |
. . . . . 85 |
||
Table 54: Connection of Interrupt Sources to the Vectored Interrupt Controller . . . . . . . . . . . . . . . . |
. . . . . 86 |
||
9 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
|
|
ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
|
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Table 55: Pin description for LPC2114/2124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 56: Pin description for LPC2212/2214 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Table 57: Pin Connect Block Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 58: Pin Function Select Register 0 for LPC2114/2124/2212/2214 (PINSEL0 - 0xE002C000) . . . . 110 Table 59: Pin Function Select Register 1 for LPC2114/2124/2212/2214 (PINSEL1 - 0xE002C004) . . . . 110 Table 60: Pin Function Select Register 2 for LPC2114/2124 (PINSEL2 - 0xE002C014) . . . . . . . . . . . . . 111 Table 61: Pin Function Select Register 2 for LPC2212/2214 (PINSEL2 - 0xE002C014) . . . . . . . . . . . . . 112 Table 62: Pin Function Select Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 63: Boot Control on BOOT1:0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 64: GPIO Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 65: GPIO Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 66: GPIO Pin Value Register (IO0PIN - 0xE0028000, IO1PIN - 0xE0028010,
IO2PIN - 0xE0028020, IO3PIN - 0xE0028030) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 67: GPIO Output Set Register (IO0SET - 0xE0028004, IO1SET - 0xE0028014,
IO2SET - 0xE0028024, IO3SET - 0xE0028034) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 68: GPIO Output Clear Register (IO0CLR - 0xE002800C, IO1CLR - 0xE002801C,
IO2CLR - 0xE002802C, IO3CLR - 0xE002803C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 69: GPIO Direction Register (IO0DIR - 0xE0028008, IO1DIR - 0xE0028018,
IO2DIR - 0xE0028028, IO3DIR - 0xE0028038) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Table 70: UART0 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 71: UART0 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 72: UART0 Receiver Buffer Register (U0RBR - 0xE000C000 when DLAB = 0, Read Only). . . . . . 123 Table 73: UART0 Transmit Holding Register (U0THR - 0xE000C000 when DLAB = 0, Write Only). . . . . 123 Table 74: UART0 Divisor Latch LSB Register (U0DLL - 0xE000C000 when DLAB = 1). . . . . . . . . . . . . . 123 Table 75: UART0 Divisor Latch MSB Register (U0DLM - 0xE000C004 when DLAB = 1). . . . . . . . . . . . . 123 Table 76: UART0 Interrupt Enable Register Bit Descriptions (U0IER - 0xE000C004 when DLAB = 0) . . 124 Table 77: UART0 Interrupt Identification Register Bit Descriptions (U0IIR - 0xE000C008, Read Only) . . 124 Table 78: UART0 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Table 79: UART0 FIFO Control Register Bit Descriptions (U0FCR - 0xE000C008) . . . . . . . . . . . . . . . . . 126 Table 80: UART0 Line Control Register Bit Descriptions (U0LCR - 0xE000C00C). . . . . . . . . . . . . . . . . . 127 Table 81: UART0 Line Status Register Bit Descriptions (U0LSR - 0xE000C014, Read Only) . . . . . . . . . 128 Table 82: UART0 Scratchpad Register (U0SCR - 0xE000C01C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 83: UART1 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Table 84: UART1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Table 85: UART1 Receiver Buffer Register (U1RBR - 0xE0010000 when DLAB = 0, Read Only) . . . . . . 135 Table 86: UART1 Transmit Holding Register (U1THR - 0xE0010000 when DLAB = 0, Write Only) . . . . . 135 Table 87: UART1 Divisor Latch LSB Register (U1DLL - 0xE0010000 when DLAB = 1) . . . . . . . . . . . . . . 135 Table 88: UART1 Divisor Latch MSB Register (U1DLM - 0xE0010004 when DLAB = 1) . . . . . . . . . . . . . 136 Table 89: UART1 Interrupt Enable Register Bit Descriptions (U1IER - 0xE0010004 when DLAB = 0) . . . 136 Table 90: UART1 Interrupt Identification Register Bit Descriptions (IIR - 0xE0010008, Read Only) . . . . . 137 Table 91: UART1 Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 92: UART1 FCR Bit Descriptions (U1FCR - 0xE0010008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 93: UART1 Line Control Register Bit Descriptions (U1LCR - 0xE001000C) . . . . . . . . . . . . . . . . . . 140 Table 94: UART1 Modem Control Register Bit Descriptions (U1MCR - 0xE0010010) . . . . . . . . . . . . . . . 141 Table 95: UART1 Line Status Register Bit Descriptions (U1LSR - 0xE0010014, Read Only). . . . . . . . . . 142 Table 96: UART1 Modem Status Register Bit Descriptions (U1MSR - 0x0xE0010018) . . . . . . . . . . . . . . 143 Table 97: UART1 Scratchpad Register (U1SCR - 0xE001001C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Table 98: I2C Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Table 99: I2C Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Table 100: I2C Control Set Register (I2CONSET - 0xE001C000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 101: I2C Control Clear Register (I2CONCLR - 0xE001C018). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Table 102: I2C Status Register (I2STAT - 0xE001C004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 103: I2C Data Register (I2DAT - 0xE001C008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 104: I2C Slave Address Register (I2ADR - 0xE001C00C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Table 105: I2C SCL High Duty Cycle Register (I2SCLH - 0xE001C010) . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 106: I2C SCL Low Duty Cycle Register (I2SCLL - 0xE001C014) . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Table 107: I2C Clock Rate Selections for VPB Clock Divider = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
10 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
|
|
ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
|
|
Table 108: I2C Clock Rate Selections for VPB Clock Divider = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 109: I2C Clock Rate Selections for VPB Clock Divider = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 110: SPI Data To Clock Phase Relationship. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Table 111: SPI Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Table 112: SPI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Table 113: SPI Control Register (S0SPCR - 0xE0020000, S1SPCR - 0xE0030000). . . . . . . . . . . . . . . . . 164 Table 114: SPI Status Register (S0SPSR - 0xE0020004, S1SPSR - 0xE0030004). . . . . . . . . . . . . . . . . . 165 Table 115: SPI Data Register (S0SPDR - 0xE0020008, S1SPDR - 0xE0030008). . . . . . . . . . . . . . . . . . . 165 Table 116: SPI Clock Counter Register (S0SPCCR - 0xE002000C, S1SPCCR - 0xE003000C) . . . . . . . . 165 Table 117: SPI Interrupt Register (S0SPINT - 0xE002001C, S1SPINT - 0xE003001C). . . . . . . . . . . . . . . 166 Table 118: Pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 119: TIMER0 and TIMER1 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 120: Interrupt Register (IR: TIMER0 - T0IR: 0xE0004000; TIMER1 - T1IR: 0xE0008000) . . . . . . . . 172 Table 121: Timer Control Register
(TCR: TIMER0 - T0TCR: 0xE0004004; TIMER1 - T1TCR: 0xE0008004) . . . . . . . . . . . . . . . . . 172 Table 122: Match Control Register
(MCR: TIMER0 - T0MCR: 0xE0004014; TIMER1 - T1MCR: 0xE0008014). . . . . . . . . . . . . . . . 173 Table 123: Capture Control Register
(CCR: TIMER0 - T0CCR: 0xE0004028; TIMER1 - T1CCR: 0xE0008028) . . . . . . . . . . . . . . . . 174 Table 124: External Match Register
(EMR: TIMER0 - T0EMR: 0xE000403C; TIMER1 - T1EMR: 0xE000803C) . . . . . . . . . . . . . . . 175 Table 125: External Match Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Table 126: Set and Reset inputs for PWM Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Table 127: Pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Table 128: Pulse Width Modulator Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Table 129: PWM Interrupt Register (PWMIR - 0xE0014000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Table 130: PWM Timer Control Register (PWMTCR - 0xE0014004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Table 131: PWM Match Control Register (PWMMCR - 0xE0014014) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Table 132: PWM Control Register (PWMPCR - 0xE001404C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Table 133: PWM Latch Enable Register (PWMLER - 0xE0014050). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Table 134: A/D Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Table 135: A/D Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Table 136: A/D Control Register (ADCR - 0xE0034000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Table 137: A/D Data Register (ADDR - 0xE0034004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Table 138: Real Time Clock Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Table 139: Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Table 140: Interrupt Location Register Bits (ILR - 0xE0024000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Table 141: Clock Tick Counter Bits (CTC - 0xE0024004). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Table 142: Clock Control Register Bits (CCR - 0xE0024008). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 Table 143: Counter Increment Interrupt Register Bits (CIIR - 0xE002400C) . . . . . . . . . . . . . . . . . . . . . . . 202 Table 144: Alarm Mask Register Bits (AMR - 0xE0024010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Table 145: Consolidated Time Register 0 Bits (CTIME0 - 0xE0024014) . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Table 146: Consolidated Time Register 1 Bits (CTIME1 - 0xE0024018) . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Table 147: Consolidated Time Register 2 Bits (CTIME2 - 0xE002401C) . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Table 148: Time Counter Relationships and Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Table 149: Time Counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 Table 150: Alarm Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Table 151: Reference Clock Divider registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Table 152: Prescaler Integer Register (PREINT - 0xE0024080). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Table 153: Prescaler Fraction Register (PREFRAC - 0xE0024084). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Table 154: Prescaler cases where the Integer Counter reload value is incremented . . . . . . . . . . . . . . . . . 210 Table 155: Watchdog Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Table 156: Watchdog Mode Register (WDMOD - 0xE0000000). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Table 157: Watchdog Feed Register (WDFEED - 0xE0000008) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Table 158: Watchdog Timer Value Register (WDTV - 0xE000000C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Table 159: Sectors in a device with 128K bytes of Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Table 160: ISP Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
11 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
|
|
ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
|
|
Table 161: ISP Unlock command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Table 162: ISP Set Baud Rate command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Table 163: Correlation between possible ISP baudrates and external crystal frequency (in MHz). . . . . . . 226 Table 164: ISP Echo command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Table 165: ISP Write to RAM command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Table 166: ISP Read Memory command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 Table 167: ISP Prepare sector(s) for write operation command description. . . . . . . . . . . . . . . . . . . . . . . . 229 Table 168: ISP Copy RAM to Flash command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Table 169: ISP Go command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Table 170: ISP Erase sector command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Table 171: ISP Blank check sector(s) command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Table 172: ISP Read Part ID command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Table 173: ISP Read Boot Code version command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Table 174: ISP Compare command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Table 175: ISP Return Codes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Table 176: IAP Command Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Table 177: IAP Prepare sector(s) for write operation command description. . . . . . . . . . . . . . . . . . . . . . . . 236 Table 178: IAP Copy RAM to Flash command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Table 179: IAP Erase Sector(s) command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Table 180: IAP Blank check sector(s) command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 181: IAP Read Part ID command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 182: IAP Read Boot Code version command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 Table 183: IAP Compare command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Table 184: IAP Status Codes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Table 185: EmbeddedICE Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 Table 186: EmbeddedICE Logic Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Table 187: ETM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Table 188: ETM Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Table 189: ETM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Table 190: RealMonitor stack requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
12 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
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ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
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DOCUMENT REVISION HISTORY |
|
2003 Dec 03:
•Prototype LPC2114/2124/2212/2214 User Manual created from the design specification. 2003 Dec 09:
•External Memory Controller and Pin Connect Block chapters updated.
2003 Dec 15/16:
•System Control Block chapter updated. 2003 Dec 18:
•A/D Converter Block chapter updated. 2004 Jan 07:
•PLL related material updated.
2004 Jan 26:
• System Control Block (Crystal Oscillator section - new frequencies added) updated. 2004 Feb 03:
•Introduction chapter (register list) updated. 2004 May 03:
•P0.16 description in "Pin Connect Block" chapter corrected from "Reserved" to "Capture 0.2 (TIMER0)".
•LPC2212 Flash size corrected in "Introduction" chapter corrected from 256 to 128 kB.
•Interrupt source #17 in "Vectored Interrupt Controller (VIC)" corrected from "EINT2" to "EINT3".
•Parallel ports 2 and 3 related registers added to "Introduction" and "GPIO" chapters
•Trigger levels determined by bits 7 and 6 in U0FCR and U1FCR ("UART0" and "UART1" chapters) now showed in both decimal and hexadecimal notations
•References to DBGSEL pin removed from entire document (pin does not exist in this family of microcontrollers)
•Pin 20 in figure showing 64-pin package ("Pin Configuration" chapter) corrected from "1.3" to "1.31"
•VddA replaced with V3A in "A/D Converter" chapter and V3A description updated in "Pin Configuration" chapter
•Warning on analog input levels added to "A/D Converter" chapter
•On-chip upper RAM boundary corrected from 0x4000 1FFF to 0x4000 3FFF in "LPC2114/2124/2212/2214 Memory Addressing" chapter
•Port pin tolerance, pull-up presence and voltage considerations added in "Pin Configuration" and "A/D Converter" chapter
•Baudrates in "Flash Memory System and Programming" corrected: 115200 and 230400 instead of 115000 and 230000
•Number of the on-chip Flash erase and write cycles added into "Introduction" and "Flash Memory System and Programming" chapters
•Pins capable of providing an External Interrupt functionality are acounted and listed in "System Control Block" chapter
•Access to ports with respect to GPIO configured pins clarified in "GPIO" and "Pin Connect Block" chapters
•Description of Code Read Protection feature added in "Flash Memory System and Programming" chapter
•IOPIN0 and IOPIN1 tyopografic errors corrected in "System Control Block" chapter
•PINSEL2 added to to "Introduction" chapter
13 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
|
|
ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
|
|
•T0IR, T0CCR, T0TCR, T1TCR, T0EMR and PCONP updated in "Introduction" chapter
•EXTMODE and EXTPOLAR registers added in "Introduction" chapter and updated in "System Control Block" chapter
•Power Control Usage Notes for reducing the total power added to "System Control Block" chapter
•PINSEL2 register as well as booting procedure updated in "Pin Connect Block" and "Watchdog" chapters
•references to the pclk in "External Memory Controller (EMC)" chapter corrected to the cclk
•LPC2212/2214 PINSEL2 table in "Pin Connect Block" chapter corrected
•A/D pin description in "A/D Converter" chapter rephrased
•Information on Spurious Interrupts added into "Vectored Interrupt Controller (VIC)" chapter
•Details on the checksum generation in case of Read Memory and Write to RAM ISP commands added in "Flash Memory System and Programming" chapter
14 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
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ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
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1. INTRODUCTION
GENERAL DESCRIPTION
The LPC2114/2124/2212/2214 are based on a 16/32 bit ARM7TDMI-STM CPU with real-time emulation and embedded trace support, together with 128/256 kilobytes (kB) of embedded high speed flash memory. A 128-bit wide internal memory interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. For critical code size applications, the alternative 16-bit Thumb Mode reduces code by more than 30% with minimal performance penalty.
With their comapct 64 and 144 pin packages, low power consumption, various 32-bit timers, combination of 4-channel 10-bit ADC or 8-channel 10-bit ADC (64 and 144 pin packages respectively), and up to 9 external interrupt pins these microcontrollers are particularly suitable for industrial control, medical systems, access control and point-of-sale.
Number of available GPIOs goes up to 46 in 64 pin package. In 144 pin packages number of available GPIOs tops 76 (with external memory in use) through 112 (single-chip application). Being equipped wide range of serial communications interfaces, they are also very well suited for communication gateways, protocol converters and embedded soft modems as well as many other general-purpose applications.
FEATURES
•16/32-bit ARM7TDMI-S microcontroller in a 64 or 144 pin package.
•16 kB on-chip Static RAM
•128/256 kB on-chip Flash Program Memory (at least 10,000 erate/write cycles over the whole temperature range). 128-bit wide interface/accelerator enables high speed 60 MHz operation.
•External 8, 16 or 32-bit bus (144 pin package only)
•In-System Programming (ISP) and In-Application Programming (IAP) via on-chip boot-loader software. Flash programming takes 1 ms per 512 byte line. Single sector or full chip erase takes 400 ms.
•EmbeddedICE-RT interface enables breakpoints and watch points. Interrupt service routines can continue to execute whilst the foreground task is debugged with the on-chip RealMonitor software.
•Embedded Trace Macrocell enables non-intrusive high speed real-time tracing of instruction execution.
•Four/eight channel (64/144 pin package) 10-bit A/D converter with conversion time as low as 2.44 ms.
•Two 32-bit timers (with 4 capture and 4 compare channels), PWM unit (6 outputs), Real Time Clock and Watchdog.
•Multiple serial interfaces including two UARTs (16C550), Fast I2C (400 kbits/s) and two SPIs™ .
•60 MHz maximum CPU clock available from programmable on-chip Phase-Locked Loop.
•Vectored Interrupt Controller with configurable priorities and vector addresses.
•Up to forty-six (64 pin) and hundred-twelve (144 pin package) 5 V tolerant general purpose I/O pins. Up to 12 independent external interrupt pins available (EIN and CAP functions).
•On-chip crystal oscillator with an operating range of 1 MHz to 30 MHz.
•Two low power modes, Idle and Power-down.
•Processor wake-up from Power-down mode via external interrupt.
•Individual enable/disable of peripheral functions for power optimization.
•Dual power supply.
-CPU operating voltage range of 1.65V to 1.95V (1.8V +/- 8.3%).
-I/O power supply range of 3.0V to 3.6V (3.3V +/- 10%).
Introduction |
15 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
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ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
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APPLICATIONS
•Industrial control
•Medical systems
•Access control
•Point-of-sale
•Communication gateway
•Embedded soft modem
•general purpose applications
DEVICE INFORMATION
Table 1: LPC2114/2124/2212/2214 device information
Device |
No. of pins |
On-chip RAM |
On-chip |
No. of 10-bit |
Note |
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FLASH |
AD Channels |
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LPC2114 |
64 |
16 kB |
128 kB |
4 |
- |
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LPC2124 |
64 |
16 kB |
256 kB |
4 |
- |
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LPC2212 |
144 |
16 kB |
128 kB |
8 |
with external memory interface |
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LPC2214 |
144 |
16 kB |
256 kB |
8 |
with external memory interface |
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Introduction |
16 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
|
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ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
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ARCHITECTURAL OVERVIEW
The LPC2114/2124/2212/2214 consists of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to on-chip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI Peripheral Bus (VPB, a compatible superset of ARM’s AMBA Advanced Peripheral Bus) for connection to on-chip peripheral functions. The LPC2114/2124/2212/2214 configures the ARM7TDMI-S processor in little-endian byte order.
AHB peripherals are allocated a 2 megabyte range of addresses at the very top of the 4 gigabyte ARM memory space. Each AHB peripheral is allocated a 16 kilobyte address space within the AHB address space. LPC2114/2124/2212/2214 peripheral functions (other than the interrupt controller) are connected to the VPB bus. The AHB to VPB bridge interfaces the VPB bus to the AHB bus. VPB peripherals are also allocated a 2 megabyte range of addresses, beginning at the 3.5 gigabyte address point. Each VPB peripheral is allocated a 16 kilobyte address space within the VPB address space.
The connection of on-chip peripherals to device pins is controlled by a Pin Connection Block. This must be configured by software to fit specific application requirements for the use of peripheral functions and pins.
ARM7TDMI-S PROCESSOR
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core.
Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue.
The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets:
•The standard 32-bit ARM instruction set.
•A 16-bit THUMB instruction set.
The THUMB set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code.
THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.
The ARM7TDMI-S processor is described in detail in the ARM7TDMI-S Datasheet that can be found on official ARM website.
ON-CHIP FLASH MEMORY SYSTEM
The LPC2114/2212 incorporate a 128 kB Flash memory system, while LPC2124/2214 incorporate a 256 kB Flash memory system. This memory may be used for both code and data storage. Programming of the Flash memory may be accomplished in several ways: over the serial built-in JTAG interface, using In System Programming (ISP) and UART0, or by means of In Application Programming (IAP) capabilities. The application program, using the In Application Programming (IAP) functions, may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc.
Introduction |
17 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
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ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
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ON-CHIP STATIC RAM
The LPC2114/2124/2212/2214 provide a 16 kB static RAM memory that may be used for code and/or data storage. The SRAM supports 8-bit, 16-bit, and 32-bit accesses.
The SRAM controller incorporates a write-back buffer in order to prevent CPU stalls during back-to-back writes. The write-back buffer always holds the last data sent by software to the SRAM. This data is only written to the SRAM when another write is requested by software (the data is only written to the SRAM when software does another write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write request (i.e. after a "warm" chip reset, the SRAM does not reflect the last write operation). Any software that checks SRAM contents after reset must take this into account. Two identical writes to a location guarantee that the data will be present after a Reset. Alternatively, a dummy write operation before entering idle or power-down mode will similarly guarantee that the last data written will be present in SRAM after a subsequent Reset.
Introduction |
18 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
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ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
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BLOCK DIAGRAM |
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1 |
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1 |
1 |
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1 |
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RESET |
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TRST |
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1 |
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TMS |
TCK |
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TDI |
TDO |
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Xtal1 |
Xtal2 |
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Test/Debug Interface |
EmulationTrace |
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Module |
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PLL |
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System |
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Functions |
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System |
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Clock |
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AHB Bridge |
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Vectored Interrupt |
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AMBA AHB |
Controller |
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ARM7 Local Bus |
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(Advanced High-performance Bus) |
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Internal SRAM |
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Internal Flash |
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Controller |
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Controller |
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AHB to VPB |
VPB |
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16 kB |
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128/256 kB |
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Bridge |
Divider |
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FLASH |
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Peripheral Bus) |
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EINT3:0 |
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8 x CAP0 |
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TIMER 0 & 1 |
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Ain3:0 |
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Ain7:42 |
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Converter |
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P0.30:0 |
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General |
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P1.31:16, 1:02 |
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P2.31:02 |
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PWM6:1 |
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PWM0 |
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Real Time
Clock
* Shared with GPIO
1When Test/Debug Interface is used, GPIO/other functions sharing these pins are not available 2LPC2212/2214 only.
|
AHB |
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Decoder |
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CS3:0* |
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External Memory |
A23:0* |
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BLS3:0* |
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Controller2 |
OE, WE* |
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D31:0* |
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I2C Serial |
SCL |
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SDA |
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Interface |
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SCK0,1 |
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SPI Serial |
MOSI0,1 |
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Interfaces 0 & 1 |
MISO0,1 |
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SSEL0,1 |
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TxD0,1 |
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UART 0 & 1 |
RxD0,1 |
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DSR1,CTS1,D |
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CD1, RI1 |
Watchdog
Timer
System
Control
Figure 1: LPC2114/2124/2212/2214 Block Diagram
Introduction |
19 |
May 03, 2004 |
Philips Semiconductors |
Preliminary User Manual |
|
|
ARM-based Microcontroller |
LPC2114/2124/2212/2214 |
|
|
LPC2114/2124/2212/2214 REGISTERS
Accesses to registers in LPC2114/2124/2212/2214 is restricted in the following ways:
1)user must NOT attempt to access any register locations not defined.
2)Access to any defined register locations must be strictly for the functions for the registers.
3)Register bits labeled ’-’, ’0’ or ’1’ can ONLY be written and read as follows:
-’-’ MUST be written with ’0’, but can return any value when read (even if it was written with ’0’). It is a reserved bit and may be used in future derivatives.
-’0’ MUST be written with ’0’, and will return a ’0’ when read.
-’1’ MUST be written with ’1’, and will return a ’1’ when read.
The following table shows all registers available in LPC2114/2124/2212/2214 microcontroller sorted according to the address.
Access to the specific one can be categorized as either read/write, read only or write only (R/W, RO and WO respectively).
"Reset Value" field refers to the data stored in used/accessible bits only. It does not include reserved bits content. Some registers may contain undetermined data upon reset. In this case, reset value is categorized as "undefined". Classification as "NA" is used in case reset value is not applicable. Some registers in RTC are not affected by the chip reset. Their reset value is marked as * and these registers must be initialized by software if the RTC is enabled.
Registers in LPC2114/2124/2212/2214 are 8, 16 or 32 bits wide. For 8 bit registers shown in Table 2, bit residing in the MSB (The Most Significant Bit) column corresponds to the bit 7 of that register, while bit in the LSB (The Least Significant Bit) column corresponds to the bit 0 of the same register.
If a register is 16/32 bit wide, the bit residing in the top left corner of its description, is the bit corresponding to the bit 15/31 of the register, while the bit in the bottom right corner corresponds to bit 0 of this register.
Examples: bit "ENA6" in PWMPCR register (address 0xE001404C) represents the bit at position 14 in this register; bits 15, 8, 7 and 0 in the same register are reserved. Bit "Stop on MR6" in PWMMCR register (0xE0014014) corresponds to the bit at position 20; bits 31 to 21 of the same register are reserved.
Unused (reserved) bits are marked with "-" and represented as gray fields. Access to them is restricted as already described.
Table 2: LPC2114/2124/2212/2214 Registers
Address |
Name |
Description |
MSB |
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LSB |
Access |
Reset |
Offset |
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Value |
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WD |
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0xE0000000 |
WD |
Watchdog |
- |
- |
- |
- |
WD |
WD |
WDRE |
WDEN |
R/W |
0 |
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MOD |
mode register |
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INT |
TOF |
SET |
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Watchdog |
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0xE0000004 |
WDTC |
timer |
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32 bit data |
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R/W |
0xFF |
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constant |
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Watchdog |
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0xE0000008 |
WD |
feed |
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8 bit data (0xAA fallowed by 0x55) |
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WO |
NA |
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FEED |
sequence |
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register |
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Introduction |
20 |
May 03, 2004 |
Philips Semiconductors |
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Preliminary User Manual |
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ARM-based Microcontroller |
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LPC2114/2124/2212/2214 |
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Table 2: LPC2114/2124/2212/2214 Registers |
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Address |
Name |
Description |
MSB |
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LSB |
Access |
Reset |
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Offset |
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Value |
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Watchdog |
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0xE000000C |
WDTV |
timer value |
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32 bit data |
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RO |
0xFF |
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register |
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TIMER0 |
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0xE0004000 |
T0IR |
T0 Interrupt |
CR3 |
CR2 |
CR1 |
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CR0 |
MR3 |
MR2 |
MR1 |
MR0 |
R/W |
0 |
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Register |
Int. |
Int. |
Int. |
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Int. |
Int. |
Int. |
Int. |
Int. |
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0xE0004004 |
T0TCR |
T0 Control |
- |
- |
- |
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- |
- |
- |
CTR |
CTR |
R/W |
0 |
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Register |
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Reset |
Enable |
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0xE0004008 |
T0TC |
T0 Counter |
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32 bit data |
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RW |
0 |
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0xE000400C |
T0PR |
T0 Prescale |
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32 bit data |
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R/W |
0 |
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Register |
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0xE0004010 |
T0PC |
T0 Prescale |
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32 bit data |
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R/W |
0 |
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Counter |
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Stop |
Reset |
Int. on |
Stop |
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4 reserved (-) bits |
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on |
on |
on |
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T0 Match |
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MR3 |
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MR3 |
MR3 |
MR2 |
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R/W |
0 |
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0xE0004014 |
T0MCR |
Control |
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Reset |
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Stop |
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Reset |
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Stop |
Reset |
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Register |
Int. on |
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Int. on |
Int. on |
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on |
on |
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on |
on |
on |
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MR2 |
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MR1 |
MR0 |
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MR2 |
MR1 |
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MR1 |
MR0 |
MR0 |
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0xE0004018 |
T0MR0 |
T0 Match |
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32 bit data |
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R/W |
0 |
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Register 0 |
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0xE000401C |
T0MR1 |
T0 Match |
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32 bit data |
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R/W |
0 |
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Register 1 |
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0xE0004020 |
T0MR2 |
T0 Match |
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32 bit data |
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R/W |
0 |
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Register 2 |
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0xE0004024 |
T0MR3 |
T0 Match |
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32 bit data |
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R/W |
0 |
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Register 3 |
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Int. on |
Int. on |
Int. on |
Int. on |
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4 reserved (-) bits |
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Cpt.3 |
Cpt.3 |
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||||
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T0 Capture |
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Cpt.3 |
Cpt.2 |
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falling |
rising |
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0xE0004028 |
T0CCR |
Control |
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R/W |
0 |
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Int. on |
Int. on |
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Int. on |
Int. on |
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Int. on |
Int. on |
|
|||||
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Register |
Int. on |
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Int. on |
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||||||
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Cpt.2 |
Cpt.2 |
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Cpt.1 |
Cpt.1 |
Cpt.0 |
Cpt.0 |
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||
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Cpt.1 |
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Cpt.0 |
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||||||
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falling |
rising |
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falling |
rising |
falling |
rising |
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0xE000402C |
T0CR0 |
T0 Capture |
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32 bit data |
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RO |
0 |
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Register 0 |
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0xE0004030 |
T0CR1 |
T0 Capture |
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32 bit data |
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RO |
0 |
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Register 1 |
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0xE0004034 |
T0CR2 |
T0 Capture |
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32 bit data |
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RO |
0 |
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Register 2 |
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|
Introduction |
21 |
May 03, 2004 |
Philips Semiconductors |
|
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|
|
Preliminary User Manual |
|
|||
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ARM-based Microcontroller |
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LPC2114/2124/2212/2214 |
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||||||
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Table 2: LPC2114/2124/2212/2214 Registers |
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Address |
Name |
Description |
MSB |
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LSB |
Access |
Reset |
|
Offset |
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Value |
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T0 External |
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4 reserved (-) bits |
|
External Match |
External Match |
|
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||||
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Control 3 |
Control 2 |
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|||||
0xE000403C |
T0EMR |
Match |
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R/W |
0 |
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External Match |
External Match |
Ext. |
Ext. |
Ext. |
Ext. |
|
||||||||
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Register |
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|||||||||
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Control 1 |
Control 0 |
Mtch3. |
Mtch2. |
Mtch.1 |
Mtch.0 |
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TIMER1 |
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0xE0008000 |
T1IR |
T1 Interrupt |
CR3 |
CR2 |
CR1 |
|
CR0 |
MR3 |
MR2 |
MR1 |
MR0 |
R/W |
0 |
|
Register |
Int. |
Int. |
Int. |
|
Int. |
Int. |
Int. |
Int. |
Int. |
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||||
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0xE0008004 |
T1TCR |
T1 Control |
- |
- |
- |
|
- |
- |
- |
CTR |
CTR |
R/W |
0 |
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Register |
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Reset |
Enable |
|
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0xE0008008 |
T1TC |
T1 Counter |
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32 bit data |
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RW |
0 |
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0xE000800C |
T1PR |
T1 Prescale |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
|
Register |
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||||||
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|
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0xE0008010 |
T1PC |
T1 Prescale |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
|
Counter |
|
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||||||
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Stop |
Reset |
Int. on |
Stop |
|
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|
|
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4 reserved (-) bits |
|
on |
on |
on |
|
|
|
|||
|
|
T1 Match |
|
|
MR3 |
|
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|
||||||
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|
MR3 |
MR3 |
MR2 |
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||
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|
||||
0xE0008014 |
T1MCR |
Control |
|
|
|
|
|
|
|
|
|
R/W |
0 |
|
Reset |
|
Stop |
|
Reset |
|
Stop |
Reset |
|
|
|||||
|
|
Register |
Int. on |
|
Int. on |
Int. on |
|
|
|
|||||
|
|
|
on |
on |
|
on |
on |
on |
|
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|
|||
|
|
|
MR2 |
|
MR1 |
MR0 |
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|||||
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MR2 |
MR1 |
|
MR1 |
MR0 |
MR0 |
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|||
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|||||
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0xE0008018 |
T1MR0 |
T1 Match |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
|
Register 0 |
|
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||||||
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|
0xE000801C |
T1MR1 |
T1 Match |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
|
Register 1 |
|
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|
||||||
|
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|
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0xE0008020 |
T1MR2 |
T1 Match |
|
|
|
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32 bit data |
|
|
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R/W |
0 |
|
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Register 2 |
|
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||||||
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0xE0008024 |
T1MR3 |
T1 Match |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
|
Register 3 |
|
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|
|
|
|
|
|
||||||
|
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Int. on |
Int. on |
Int. on |
Int. on |
|
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|
4 reserved (-) bits |
|
Cpt.3 |
Cpt.3 |
|
|
|
||||
|
|
T1 Capture |
|
|
Cpt.3 |
Cpt.2 |
|
|
|
|||||
|
|
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|
|
falling |
rising |
|
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|
|||
|
|
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|
|
R/W |
0 |
|
|||
0xE0008028 |
T1CCR |
Control |
|
|
|
|
|
|
|
|
|
|
||
|
|
Register |
Int. on |
Int. on |
Int. on |
|
Int. on |
Int. on |
Int. on |
Int. on |
Int. on |
|
|
|
|
|
|
Cpt.2 |
Cpt.2 |
|
Cpt.1 |
Cpt.1 |
Cpt.0 |
Cpt.0 |
|
|
|
||
|
|
|
Cpt.1 |
|
Cpt.0 |
|
|
|
||||||
|
|
|
falling |
rising |
|
falling |
rising |
falling |
rising |
|
|
|
||
|
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|
||||||
|
|
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|
|
|
0xE000802C |
T1CR0 |
T1 Capture |
|
|
|
|
32 bit data |
|
|
|
RO |
0 |
|
|
Register 0 |
|
|
|
|
|
|
|
|
||||||
|
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|
|
0xE0008030 |
T1CR1 |
T1 Capture |
|
|
|
|
32 bit data |
|
|
|
RO |
0 |
|
|
Register 1 |
|
|
|
|
|
|
|
|
||||||
|
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|
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|
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|
|
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|
|
|
|
|
|
|
|
|
|
0xE0008034 |
T1CR2 |
T1 Capture |
|
|
|
|
32 bit data |
|
|
|
RO |
0 |
|
|
Register 2 |
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Introduction |
22 |
May 03, 2004 |
Philips Semiconductors |
|
|
|
|
|
|
|
|
|
Preliminary User Manual |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ARM-based Microcontroller |
|
|
|
|
|
|
LPC2114/2124/2212/2214 |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 2: LPC2114/2124/2212/2214 Registers |
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address |
Name |
Description |
MSB |
|
|
|
|
|
|
|
LSB |
Access |
Reset |
|
Offset |
|
|
|
|
|
|
|
Value |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0008038 |
T1CR3 |
T1 Capture |
|
|
|
|
32 bit data |
|
|
|
RO |
0 |
|
|
Register 3 |
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
T1 External |
|
4 reserved (-) bits |
|
External Match |
External Match |
|
|
|
||||
|
|
|
|
Control 3 |
Control 2 |
|
|
|
||||||
|
|
|
|
|
|
|
R/W |
0 |
|
|||||
0xE000803C |
T1EMR |
Match |
|
|
|
|
|
|
|
|
|
|
||
|
|
Register |
External Match |
External Match |
Ext. |
Ext. |
Ext. |
Ext. |
|
|
|
|||
|
|
|
Control 1 |
Control 0 |
Mtch.3 |
Mtch2. |
Mtch.1 |
Mtch.0 |
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
UART0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0RBR |
U0 Receiver |
|
|
|
|
|
|
|
|
|
|
un- |
|
|
Buffer |
|
|
|
|
8 bit data |
|
|
|
RO |
||||
|
(DLAB=0) |
Register |
|
|
|
|
|
|
|
|
|
|
defined |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE000C000 |
U0THR |
U0 Transmit |
|
|
|
|
|
|
|
|
|
|
|
|
Holding |
|
|
|
|
8 bit data |
|
|
|
WO |
NA |
||||
|
(DLAB=0) |
Register |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0DLL |
U0 Divisor |
|
|
|
|
8 bit data |
|
|
|
R/W |
0x01 |
||
|
(DLAB=1) |
Latch LSB |
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0IER |
U0 Interrupt |
|
|
|
|
|
|
En. Rx |
Enable |
En. Rx |
|
|
|
|
Enable |
0 |
0 |
0 |
|
0 |
0 |
Line |
THRE |
Data |
R/W |
0 |
|
|
|
(DLAB=0) |
|
Status |
|
||||||||||
0xE000C004 |
Register |
|
|
|
|
|
|
Int. |
Av.Int. |
|
|
|
||
|
|
|
|
|
|
|
|
Int. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0DLM |
U0 Divisor |
|
|
|
|
8 bit data |
|
|
|
R/W |
0 |
|
|
|
(DLAB=1) |
Latch MSB |
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0IIR |
U0 Interrupt |
FIFOs Enabled |
0 |
|
0 |
IIR3 |
IIR2 |
IIR1 |
IIR0 |
RO |
0x01 |
||
|
ID Register |
|
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE000C008 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0 FIFO |
|
|
|
|
|
|
U0 Tx |
U0 Rx |
U0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
U0FCR |
Control |
Rx Trigger |
- |
|
- |
- |
FIFO |
FIFO |
FIFO |
WO |
0 |
|
|
|
|
Register |
|
|
|
|
|
|
Reset |
Reset |
Enable |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0 Line |
|
Set |
Stick |
|
Even |
Parity |
Nm. of |
Word Length |
|
|
|
|
0xE000C00C |
U0LCR |
Control |
DLAB |
|
Parity |
Stop |
R/W |
0 |
|
|||||
Break |
Parity |
|
Enable |
Select |
|
|||||||||
|
|
Register |
|
|
Select |
Bits |
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U0 Line |
Rx |
|
|
|
|
|
|
|
|
|
|
|
0xE000C014 |
U0LSR |
Status |
FIFO |
TEMT |
THRE |
|
BI |
FE |
PE |
OE |
DR |
RO |
0x60 |
|
|
|
Register |
Error |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE000C01C |
U0SCR |
U0 Scratch |
|
|
|
|
8 bit data |
|
|
|
R/W |
0 |
|
|
Pad Register |
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
UART1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Introduction |
23 |
May 03, 2004 |
Philips Semiconductors |
|
|
|
|
|
|
|
|
Preliminary User Manual |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ARM-based Microcontroller |
|
|
|
|
|
LPC2114/2124/2212/2214 |
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 2: LPC2114/2124/2212/2214 Registers |
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address |
Name |
Description |
MSB |
|
|
|
|
|
|
LSB |
Access |
Reset |
|
Offset |
|
|
|
|
|
|
|
|
|
|
|
Value |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1RBR |
U1 Receiver |
|
|
|
|
|
|
|
|
|
un- |
|
|
Buffer |
|
|
|
8 bit data |
|
|
|
RO |
||||
|
(DLAB=0) |
Register |
|
|
|
|
|
|
|
|
|
defined |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0010000 |
U1THR |
U1 Transmit |
|
|
|
|
|
|
|
|
|
|
|
Holding |
|
|
|
8 bit data |
|
|
|
WO |
NA |
||||
|
|
|
|
|
|
|
|||||||
|
(DLAB=0) |
Register |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1DLL |
U1 Divisor |
|
|
|
8 bit data |
|
|
|
R/W |
0x01 |
||
|
(DLAB=1) |
Latch LSB |
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1IER |
U1 Interrupt |
|
|
|
|
En. |
En. Rx |
Enable |
En. Rx |
|
|
|
|
Enable |
0 |
0 |
0 |
0 |
Mdem |
Line |
THRE |
Data |
R/W |
0 |
|
|
|
(DLAB=0) |
Satus |
Status |
|
|||||||||
0xE0010004 |
Register |
|
|
|
|
Int. |
Av.Int. |
|
|
|
|||
|
|
|
|
|
|
Int. |
Int. |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1DLM |
U1 Divisor |
|
|
|
8 bit data |
|
|
|
R/W |
0 |
|
|
|
(DLAB=1) |
Latch MSB |
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1IIR |
U1 Interrupt |
FIFOs Enabled |
0 |
0 |
IIR3 |
IIR2 |
IIR1 |
IIR0 |
RO |
0x01 |
||
|
ID Register |
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0010008 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1 FIFO |
|
|
|
|
|
U0 Tx |
U0 Rx |
U0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
U1FCR |
Control |
Rx Trigger |
- |
- |
- |
FIFO |
FIFO |
FIFO |
WO |
0 |
|
|
|
|
Register |
|
|
|
|
|
Reset |
Reset |
Enable |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1 Line |
|
Set |
Stick |
Even |
Parity |
Nm. of |
Word Length |
|
|
|
|
0xE001000C |
U1LCR |
Control |
DLAB |
Parity |
Stop |
R/W |
0 |
|
|||||
Break |
Parity |
Enable |
Select |
|
|||||||||
|
|
Register |
|
Select |
Bits |
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
U1 |
U1 Modem |
|
|
|
Loop |
|
|
|
|
|
|
|
0xE0010010 |
Control |
0 |
0 |
0 |
0 |
0 |
RTS |
DTR |
R/W |
0 |
|
||
MCR |
Back |
|
|||||||||||
|
Register |
|
|
|
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||
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|
|
U1 Line |
Rx |
|
|
|
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|
|
|
|
|
|
0xE0010014 |
U1LSR |
Status |
FIFO |
TEMT |
THRE |
BI |
FE |
PE |
OE |
DR |
RO |
0x60 |
|
|
|
Register |
Error |
|
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|
|
|
|
0xE001001C |
U1SCR |
U1 Scratch |
|
|
|
8 bit data |
|
|
|
R/W |
0 |
|
|
Pad Register |
|
|
|
|
|
|
|
||||||
|
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|
|
U1 |
U1 Modem |
|
|
|
|
Delta |
Trailing |
Delta |
Delta |
|
|
|
0xE0010018 |
Status |
DCD |
RI |
DSR |
CTS |
Edge |
RO |
0 |
|
||||
MSR |
DCD |
DSR |
CTS |
|
|||||||||
|
Register |
|
|
|
|
RI |
|
|
|
||||
|
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|
||
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|
|
|
|
|
PWM |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PWM |
- |
- |
- |
- |
- |
MR6 |
MR5 |
MR4 |
|
|
|
|
PWM |
Int. |
Int. |
Int. |
|
|
|
||||||
0xE0014000 |
|
|
|
|
|
R/W |
0 |
|
|||||
Interrupt |
|
|
|
|
|
|
|
|
|
||||
IR |
|
|
|
|
MR3 |
MR2 |
MR1 |
MR0 |
|
||||
|
Register |
- |
- |
- |
- |
|
|
|
|||||
|
|
|
|
|
|||||||||
|
|
|
Int. |
Int. |
Int. |
Int. |
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PWM |
PWM Timer |
|
|
|
|
PWM |
|
CTR |
CTR |
|
|
|
0xE0014004 |
Control |
- |
- |
- |
- |
- |
R/W |
0 |
|
||||
TCR |
Enable |
Reset |
Enable |
|
|||||||||
|
Register |
|
|
|
|
|
|
|
|
||||
|
|
|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014008 |
PWM |
PWM Timer |
|
|
|
32 bit data |
|
|
|
RW |
0 |
|
|
TC |
Counter |
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Introduction |
24 |
May 03, 2004 |
Philips Semiconductors |
|
|
|
|
|
|
|
|
|
Preliminary User Manual |
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ARM-based Microcontroller |
|
|
|
|
|
|
LPC2114/2124/2212/2214 |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 2: LPC2114/2124/2212/2214 Registers |
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address |
Name |
Description |
MSB |
|
|
|
|
|
|
|
LSB |
Access |
Reset |
|
Offset |
|
|
|
|
|
|
|
Value |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PWM |
PWM |
|
|
|
|
|
|
|
|
|
|
|
|
0xE001400C |
Prescale |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
||
PR |
|
|
|
|
|
|
|
|
||||||
|
Register |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PWM |
PWM |
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014010 |
Prescale |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
||
PC |
|
|
|
|
|
|
|
|
||||||
|
Counter |
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
Stop |
Reset |
Int. on |
Stop |
Reset |
|
|
|
|
|
|
11 reserved (-) bits |
on |
on |
on |
on |
|
|
|
||||
|
|
|
MR6 |
|
|
|
||||||||
|
|
|
|
|
|
|
MR6 |
MR6 |
MR5 |
MR5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
PWM Match |
|
|
|
|
|
|
|
|
|
|
|
|
|
PWM |
Int. on |
Stop |
|
Reset |
Int. on |
Stop |
Reset |
Int. on |
Stop |
|
|
|
|
0xE0014014 |
Control |
on |
|
on |
on |
on |
on |
R/W |
0 |
|
||||
MCR |
MR5 |
|
MR4 |
MR3 |
|
|||||||||
|
Register |
MR4 |
|
MR4 |
MR3 |
MR3 |
MR2 |
|
|
|
||||
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Reset |
Int. on |
Stop |
Reset |
Int. on |
Stop |
Reset |
Int. on |
|
|
|
|
|
|
|
on |
on |
on |
on |
on |
|
|
|
||||
|
|
|
MR2 |
|
MR1 |
MR0 |
|
|
|
|||||
|
|
|
MR2 |
|
MR1 |
MR1 |
MR0 |
MR0 |
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014018 |
PWM |
PWM Match |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
|
MR0 |
Register 0 |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE001401C |
PWM |
PWM Match |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
|
MR1 |
Register 1 |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014020 |
PWM |
PWM Match |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
|
MR2 |
Register 2 |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014024 |
PWM |
PWM Match |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
|
MR3 |
Register 3 |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014040 |
PWM |
PWM Match |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
|
MR4 |
Register 4 |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014044 |
PWM |
PWM Match |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
|
MR5 |
Register 5 |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0014048 |
PWM |
PWM Match |
|
|
|
|
32 bit data |
|
|
|
R/W |
0 |
|
|
MR6 |
Register 6 |
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE001404C |
PWM |
PWM Control |
- |
ENA6 |
|
ENA5 |
ENA4 |
ENA3 |
ENA2 |
ENA1 |
- |
R/W |
0 |
|
|
|
|
|
|
|
|
|
|
|
|||||
PCR |
Register |
- |
SEL6 |
|
SEL5 |
SEL4 |
SEL3 |
SEL2 |
SEL1 |
- |
|
|||
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
PWM Latch |
|
Ena. |
Ena. |
Ena. |
Ena. |
Ena. |
Ena. |
Ena. |
|
|
|
|
|
PWM |
|
PWM |
|
PWM |
PWM |
PWM |
PWM |
PWM |
PWM |
|
|
|
|
0xE0014050 |
Enable |
- |
|
R/W |
0 |
|
||||||||
LER |
M6 |
|
M5 |
M4 |
M3 |
M2 |
M1 |
M0 |
|
|||||
|
Register |
|
|
|
|
|
||||||||
|
|
|
Latch |
|
Latch |
Latch |
Latch |
Latch |
Latch |
Latch |
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
I2C |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE001C000 |
I2CONS |
I2C Control |
- |
I2EN |
|
STA |
STO |
SI |
AA |
- |
- |
R/W |
0 |
|
|
ET |
Set Register |
|
|
|
|
|
|
|
|
|
|
|
|
0xE001C004 |
I2STAT |
I2C Status |
|
|
5 bit Status |
|
0 |
0 |
0 |
RO |
0xF8 |
|
||
Register |
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE001C008 |
I2DAT |
I2C Data |
|
|
|
|
8 bit data |
|
|
|
R/W |
0 |
|
|
Register |
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Introduction |
25 |
May 03, 2004 |
Philips Semiconductors |
|
|
|
|
|
|
|
|
|
Preliminary User Manual |
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ARM-based Microcontroller |
|
|
|
|
|
|
LPC2114/2124/2212/2214 |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 2: LPC2114/2124/2212/2214 Registers |
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address |
Name |
Description |
MSB |
|
|
|
|
|
|
|
LSB |
Access |
Reset |
|
Offset |
|
|
|
|
|
|
|
Value |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
I2 |
I2C Slave |
|
|
|
|
|
|
|
|
|
|
|
|
0xE001C00C |
Address |
|
|
|
7 bit data |
|
|
|
GC |
R/W |
0 |
|
||
ADR |
|
|
|
|
|
|
|
|||||||
|
Register |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SCL Duty |
|
|
|
|
|
|
|
|
|
|
|
|
0xE001C010 |
I2 |
Cycle |
|
|
|
16 bit data |
|
|
|
R/W |
0x04 |
|
||
SCLH |
Register High |
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
Half Word |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SCL Duty |
|
|
|
|
|
|
|
|
|
|
|
|
0xE001C014 |
I2 |
Cycle |
|
|
|
16 bit data |
|
|
|
R/W |
0x04 |
|
||
SCLL |
Register Low |
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
Half Word |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
I2CONC |
I2C Control |
|
|
|
|
|
|
|
|
|
|
|
|
0xE001C018 |
Clear |
- |
I2ENC |
STAC |
- |
|
SIC |
AAC |
- |
- |
WO |
NA |
|
|
|
LR |
Register |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SPI0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0020000 |
S0 |
SPI0 Control |
SPIE |
LSBF |
MSTR |
CPOL |
|
CPHA |
- |
- |
- |
R/W |
0 |
|
SPCR |
Register |
|
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0020004 |
S0 |
SPI0 Status |
SPIF |
WCOL |
ROVR |
MODF |
|
ABRT |
- |
- |
- |
RO |
0 |
|
SPSR |
Register |
|
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0020008 |
S0 |
SPI0 Data |
|
|
|
8 bit data |
|
|
|
R/W |
0 |
|
||
SPDR |
Register |
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
S0 |
SPI0 Clock |
|
|
|
|
|
|
|
|
|
|
|
|
0xE002000C |
Counter |
|
|
|
8 bit data |
|
|
|
R/W |
0 |
|
|||
SPCCR |
|
|
|
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|
|||||||
|
|
Register |
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|
|
|
0xE002001C |
S0 |
SPI0 |
- |
- |
- |
- |
|
- |
- |
- |
SPI |
R/W |
0 |
|
SPINT |
Interrupt Flag |
|
Int. |
|
||||||||||
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|||
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SPI1 |
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|
|
0xE0030000 |
S1 |
SPI1 Control |
SPIE |
LSBF |
MSTR |
CPOL |
|
CPHA |
- |
- |
- |
R/W |
0 |
|
SPCR |
Register |
|
|
|||||||||||
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||
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|
|
|
0xE0030004 |
S1 |
SPI1 Status |
SPIF |
WCOL |
ROVR |
MODF |
|
ABRT |
- |
- |
- |
RO |
0 |
|
SPSR |
Register |
|
|
|||||||||||
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||
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|
|
|
|
0xE0030008 |
S1 |
SPI1 Data |
|
|
|
8 bit data |
|
|
|
R/W |
0 |
|
||
SPDR |
Register |
|
|
|
|
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|
|
||||||
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||
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|
|
S1 |
SPI1 Clock |
|
|
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|
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|
|
|
|
|
0xE003000C |
Counter |
|
|
|
8 bit data |
|
|
|
R/W |
0 |
|
|||
SPCCR |
|
|
|
|
|
|
|
|||||||
|
Register |
|
|
|
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|
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|
|
|
|
|
|
|
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|
|
|
|
|
|
0xE003001C |
S1 |
SPI1 |
- |
- |
- |
- |
|
- |
- |
- |
SPI |
R/W |
0 |
|
SPINT |
Interrupt Flag |
|
Int. |
|
||||||||||
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|
|||
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|
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RTC |
|
|
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|
|
|
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|
|
|
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|
|
|
|
|
|
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|
|
|
|
|
|
Introduction |
26 |
May 03, 2004 |
Philips Semiconductors |
|
|
|
|
|
|
|
|
|
|
|
|
|
Preliminary User Manual |
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
ARM-based Microcontroller |
|
|
|
|
|
|
|
|
LPC2114/2124/2212/2214 |
|
||||||||
|
|
|
|
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|
|
|
|
|
|
Table 2: LPC2114/2124/2212/2214 Registers |
|
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|||
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|
|
|
Address |
Name |
Description |
MSB |
|
|
|
|
|
|
|
|
|
|
|
LSB |
Access |
Reset |
|
Offset |
|
|
|
|
|
|
|
|
|
|
|
Value |
|
|||||
|
|
|
|
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|
|
|
|
|
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|
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|
|
|
|
|
|
|
Interrupt |
|
|
|
|
|
|
|
|
|
|
RTC |
|
RTC |
|
|
|
0xE0024000 |
ILR |
Location |
- |
- |
- |
|
- |
|
- |
|
- |
|
|
R/W |
* |
|
||
|
|
|
|
ALF |
|
CIF |
|
|||||||||||
|
|
Register |
|
|
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|
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|
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||
|
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|
|
|
|
|
|
0xE0024004 |
CTC |
Clock Tick |
|
|
15 bit data |
|
|
|
|
|
|
- |
RO |
* |
|
|||
Counter |
|
|
|
|
|
|
|
|
|
|||||||||
|
|
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|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
0xE0024008 |
CCR |
Clock Control |
- |
- |
- |
|
- |
|
CTTEST |
|
CTC |
|
CLK |
R/W |
* |
|
||
Register |
|
|
|
RST |
|
EN |
|
|||||||||||
|
|
|
|
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|
|||
|
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|
|
|
|
Counter |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE002400C |
CIIR |
Increment |
IM |
IM |
IM |
|
IM |
|
IM |
|
IM |
|
IM |
|
IM |
R/W |
* |
|
Interrupt |
YEAR |
MON |
DOY |
|
DOW |
|
DOM |
|
HOUR |
|
MIN |
|
SEC |
|
||||
|
|
|
|
|
|
|
|
|
|
|||||||||
|
|
Register |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024010 |
AMR |
Alarm Mask |
AMR |
AMR |
AMR |
|
AMR |
|
AMR |
|
AMR |
|
AMR |
|
AMR |
R/W |
* |
|
Register |
YEAR |
MON |
DOY |
|
DOW |
|
DOM |
|
HOUR |
|
MIN |
|
SEC |
|
||||
|
|
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
- |
- |
- |
|
- |
|
- |
|
3 bit Day of Week |
|
|
|
||||
|
|
Consolidated |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
- |
- |
- |
|
|
|
|
5 bit Hours |
|
|
|
RO |
* |
|
|||
0xE0024014 |
CTIME0 |
Time |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
- |
- |
|
|
|
|
6 bit Minutes |
|
|
|
|
||||||||
|
|
Register 0 |
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
- |
- |
|
|
|
|
6 bit Seconds |
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
- |
- |
- |
|
- |
|
|
|
|
|
|
|
|
|
|
|
|
|
Consolidated |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024018 |
|
|
|
|
|
12 bit Year |
|
|
|
|
|
|
RO |
* |
|
|||
CTIME1 |
Time |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
- |
- |
- |
|
- |
|
|
|
4 bit Month |
|
|
||||||||
|
|
Register 1 |
|
|
|
|
|
|
|
|
||||||||
|
|
|
- |
- |
- |
|
|
|
5 bit Day of Month |
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Consolidated |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE002401C |
CTIME2 |
Time |
|
reserved (-) 20 bits |
|
|
|
12 bit Day of Year |
|
RO |
* |
|
||||||
|
|
Register 2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024020 |
SEC |
Seconds |
- |
- |
|
|
|
|
6 bit data |
|
|
|
R/W |
* |
|
|||
Register |
|
|
|
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024024 |
MIN |
Minutes |
- |
- |
|
|
|
|
6 bit data |
|
|
|
R/W |
* |
|
|||
Register |
|
|
|
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024028 |
HOUR |
Hours |
- |
- |
- |
|
|
|
|
|
5 bit data |
|
|
|
R/W |
* |
|
|
Register |
|
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE002402C |
DOM |
Day of Month |
- |
- |
- |
|
|
|
|
|
5 bit data |
|
|
|
R/W |
* |
|
|
Register |
|
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024030 |
DOW |
Day of Week |
- |
- |
- |
|
- |
|
- |
|
|
3 bit data |
|
R/W |
* |
|
||
Register |
|
|
|
|
|
|
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024034 |
DOY |
Day of Year |
|
reserved (-) 7 bits |
|
|
|
|
9 bit data |
|
R/W |
* |
|
|||||
Register |
|
|
|
|
|
|
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024038 |
MONTH |
Months |
- |
- |
- |
|
- |
|
|
|
4 bit data |
|
R/W |
* |
|
|||
Register |
|
|
|
|
|
|
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE002403C |
YEAR |
Year Register |
reserved (-) 4 bits |
|
|
|
|
12 bit data |
|
|
|
R/W |
* |
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Introduction |
27 |
May 03, 2004 |
Philips Semiconductors |
|
|
|
|
|
|
|
|
|
Preliminary User Manual |
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ARM-based Microcontroller |
|
|
|
|
|
|
LPC2114/2124/2212/2214 |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Table 2: LPC2114/2124/2212/2214 Registers |
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Address |
Name |
Description |
MSB |
|
|
|
|
|
|
|
LSB |
Access |
Reset |
|
Offset |
|
|
|
|
|
|
|
Value |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024060 |
AL |
Alarm value |
- |
- |
|
|
|
6 bit data |
R/W |
* |
|
|||
SEC |
for Seconds |
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024064 |
AL |
Alarm value |
- |
- |
|
|
|
6 bit data |
R/W |
* |
|
|||
MIN |
for Minutes |
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024068 |
AL |
Alarm value |
- |
- |
- |
|
|
|
5 bit data |
R/W |
* |
|
||
HOUR |
for Hours |
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AL |
Alarm value |
|
|
|
|
|
|
|
|
|
|
|
|
0xE002406C |
for Day of |
- |
- |
- |
|
|
|
5 bit data |
R/W |
* |
|
|||
DOM |
|
|
|
|
||||||||||
|
Month |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AL |
Alarm value |
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024070 |
for Day of |
- |
- |
- |
- |
|
- |
|
3 bit data |
R/W |
* |
|
||
DOW |
|
|
|
|||||||||||
|
Week |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AL |
Alarm value |
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024074 |
for Day of |
reserved (-) 7 bits |
|
|
|
9 bit data |
R/W |
* |
|
|||||
DOY |
|
|
|
|
||||||||||
|
Year |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE0024078 |
AL |
Alarm value |
- |
- |
- |
- |
|
|
4 bit data |
R/W |
* |
|
||
MON |
for Months |
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
0xE002407C |
AL |
Alarm value |
reserved |
|
|
|
12 bit data |
R/W |
* |
|
||||
YEAR |
for Year |
(-) 4 bits |
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PRE |
Prescale |
reserved |
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0xE0024080 |
value, integer |
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13 bit data |
R/W |
0 |
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INT |
(-) 3 bits |
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portion |
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Prescale |
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0xE0024084 |
PRE |
value, |
- |
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15 bit data |
R/W |
0 |
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FRAC |
fractional |
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portion |
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GPIO PORT0 |
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0xE0028000 |
IO0PIN |
GPIO 0 Pin |
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32 bit data |
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RO |
NA |
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Value reg. |
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0xE0028004 |
IO0SET |
GPIO 0 Out. |
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32 bit data |
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R/W |
0 |
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Set register |
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0xE0028008 |
IO0DIR |
GPIO 0 Dir. |
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32 bit data |
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R/W |
0 |
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control reg. |
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0xE002800C |
IO0CLR |
GPIO 0 Out. |
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32 bit data |
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WO |
0 |
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Clear register |
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GPIO PORT1 |
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0xE0028010 |
IO1PIN |
GPIO 1 Pin |
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32 bit data |
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RO |
NA |
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Value reg. |
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0xE0028014 |
IO1SET |
GPIO 1 Out. |
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32 bit data |
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R/W |
0 |
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Set register |
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|||||||
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|
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|
Introduction |
28 |
May 03, 2004 |
Philips Semiconductors |
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Preliminary User Manual |
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ARM-based Microcontroller |
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LPC2114/2124/2212/2214 |
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Table 2: LPC2114/2124/2212/2214 Registers |
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Address |
Name |
Description |
MSB |
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LSB |
Access |
Reset |
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Offset |
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Value |
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0xE0028018 |
IO1DIR |
GPIO 1 Dir. |
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32 bit data |
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R/W |
0 |
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control reg. |
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0xE002801C |
IO1CLR |
GPIO 1 Out. |
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32 bit data |
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WO |
0 |
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Clear register |
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GPIO PORT2 |
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0xE0028020 |
IO2PIN |
GPIO 2 Pin |
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32 bit data |
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RO |
NA |
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Value reg. |
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0xE0028024 |
IO2SET |
GPIO 2 Out. |
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32 bit data |
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R/W |
0 |
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Set register |
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0xE0028028 |
IO2DIR |
GPIO 2 Dir. |
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32 bit data |
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R/W |
0 |
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control reg. |
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0xE002802C |
IO2CLR |
GPIO 2 Out. |
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32 bit data |
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WO |
0 |
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Clear register |
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GPIO PORT3 |
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0xE0028030 |
IO3PIN |
GPIO 3 Pin |
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32 bit data |
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RO |
NA |
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|||
Value reg. |
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0xE0028034 |
IO3SET |
GPIO 3 Out. |
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32 bit data |
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R/W |
0 |
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Set register |
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0xE0028038 |
IO3DIR |
GPIO 3 Dir. |
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32 bit data |
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R/W |
0 |
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|||
control reg. |
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0xE002803C |
IO3CLR |
GPIO 3 Out. |
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32 bit data |
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WO |
0 |
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Clear register |
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Pin Connet Block |
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PIN |
Pin function |
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0xE002C000 |
select |
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32 bit data |
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R/W |
0 |
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SEL0 |
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register 0 |
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PIN |
Pin function |
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0xE002C004 |
select |
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32 bit data |
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R/W |
0 |
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SEL1 |
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register 1 |
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- |
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PIN |
Pin function |
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24-bit pin configuration data (144 package case) |
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0xE002C014 |
select |
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R/W |
0 |
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Reserved bits (64 package case) |
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|||||||||
SEL2 |
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|||||||||
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register 2 |
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configuration |
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- |
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data |
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ADC |
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|
|
|
Introduction |
29 |
May 03, 2004 |
Philips Semiconductors |
|
|
|
|
|
|
|
|
|
Preliminary User Manual |
|
|||
|
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|
|
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|
|
|
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|
|
|
ARM-based Microcontroller |
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LPC2114/2124/2212/2214 |
|
|||||||
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|
|
Table 2: LPC2114/2124/2212/2214 Registers |
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Address |
Name |
Description |
MSB |
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LSB |
Access |
Reset |
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Offset |
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Value |
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- |
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EDGE |
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START |
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0xE0034000 |
ADCR |
ADC Control |
TEST1:0 |
PDN |
- |
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CLKS |
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BURST |
RW |
01 |
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|||||
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register |
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8 bit data |
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8 bit data |
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DONE |
OVER |
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- |
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CHN |
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RUN |
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0xE0034004 |
ADDR |
ADC Data |
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- |
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RW |
x |
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register |
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10 bit data |
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- |
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System Control Block |
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0xE01FC000 |
MAM |
MAM control |
- |
- |
- |
- |
- |
- |
2 bit data |
R/W |
0 |
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CR |
register |
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||||||||||||
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0xE01FC004 |
MAM |
MAM timing |
- |
- |
- |
- |
- |
|
3 bit data |
|
R/W |
0x07 |
|
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TIM |
control |
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MEM |
Memory |
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0xE01FC040 |
mapping |
- |
- |
- |
- |
- |
- |
2 bit data |
R/W |
0 |
|
|||
MAP |
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|||||||||||||
|
control |
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0xE01FC080 |
PLL |
PLL control |
- |
- |
- |
- |
- |
- |
PLLC |
|
PLLE |
R/W |
0 |
|
CON |
register |
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|||||||||||
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PLL |
PLL |
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0xE01FC084 |
configuration |
- |
2bit data PSEL |
|
5 bit data MSEL |
|
R/W |
0 |
|
|||||
CFG |
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|||||||||||
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register |
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0xE01FC088 |
PLL |
PLL status |
- |
- |
- |
- |
- |
PLOCK |
PLLC |
|
PLLE |
RO |
0 |
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|||||
STAT |
register |
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|||
- |
2bit data PSEL |
|
5 bit data MSEL |
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|||||||||
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|||||||||
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0xE01FC08C |
PLL |
PLL feed |
|
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|
8 bit data |
|
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WO |
NA |
|
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FEED |
register |
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|||||
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0xE01FC0C0 |
PCON |
Power control |
- |
- |
- |
- |
- |
- |
PD |
|
IDL |
R/W |
0 |
|
register |
|
|
||||||||||||
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|
Power control |
reserved (-) 19 bits |
PCAD |
- |
PC |
PC |
|
PC |
|
|
|
||
|
|
SPI1 |
RTC |
|
SPI0 |
|
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0xE01FC0C4 |
PCONP |
for |
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R/W |
0x3BE |
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PC |
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PC |
PC |
PC |
PC |
PC |
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peripherals |
- |
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- |
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I2C |
PWM0 |
URT1 |
URT0 |
TIM1 |
TIM0 |
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VPB |
VPB divider |
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0xE01FC100 |
- |
- |
- |
- |
- |
- |
2 bit data |
R/W |
0 |
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DIV |
control |
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EXT |
External |
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0xE01FC140 |
interrupt flag |
- |
- |
- |
- |
EINT3 |
EINT2 |
EINT1 |
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EINT0 |
R/W |
0 |
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INT |
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register |
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Introduction |
30 |
May 03, 2004 |
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