June 1999
LM2524D/LM3524D
Regulating Pulse Width Modulator
General Description
The LM3524D family is an improved version of the industry standard LM3524. It has improved specifications and additional features yet is pin for pin compatible with existing 3524 families. New features reduce the need for additional external circuitry often required in the original version.
The LM3524D has a ±1% precision 5V reference. The current carrying capability of the output drive transistors has
been raised to 200 mA while reducing VCEsat and increasing VCE breakdown to 60V. The common mode voltage range of
the error-amp has been raised to 5.5V to eliminate the need for a resistive divider from the 5V reference.
In the LM3524D the circuit bias line has been isolated from the shut-down pin. This prevents the oscillator pulse amplitude and frequency from being disturbed by shut-down. Also at high frequencies ( 300 kHz) the max. duty cycle per output has been improved to 44% compared to 35% max. duty cycle in other 3524s.
In addition, the LM3524D can now be synchronized externally, through pin 3. Also a latch has been added to insure
one pulse per period even in noisy environments. The LM3524D includes double pulse suppression logic that insures when a shut-down condition is removed the state of the T-flip-flop will change only after the first clock pulse has arrived. This feature prevents the same output from being pulsed twice in a row, thus reducing the possibility of core saturation in push-pull designs.
Features
nFully interchangeable with standard LM3524 family
n±1% precision 5V reference with thermal shut-down
nOutput current to 200 mA DC
n60V output capability
nWide common mode input range for error-amp
nOne pulse per period (noise suppression)
nImproved max. duty cycle at high frequencies
nDouble pulse suppression
nSynchronize through pin 3
Block Diagram
DS008650-1
Modulator Width Pulse Regulating LM2524D/LM3524D
© 1999 National Semiconductor Corporation |
DS008650 |
www.national.com |
Absolute Maximum Ratings (Note 5)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.
Supply Voltage |
40V |
Collector Supply Voltage |
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(LM2524D) |
55V |
(LM3524D) |
40V |
Output Current DC (each) |
200 mA |
Oscillator Charging Current (Pin 7) |
5 mA |
Internal Power Dissipation |
1W |
Operating Junction Temperature |
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Range (Note 2) |
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LM2524D |
−40ÊC to +125ÊC |
LM3524D |
0ÊC to +125ÊC |
Maximum Junction Temperature |
150Ê |
Storage Temperature Range |
−65ÊC to +150ÊC |
Lead Temperature (Soldering 4 sec.) |
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M, N Pkg. |
260ÊC |
Electrical Characteristics
(Note 1)
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LM2524D |
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LM3524D |
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Symbol |
Parameter |
Conditions |
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Tested |
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Design |
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Tested |
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Design |
Units |
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Typ |
Limit |
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Limit |
Typ |
Limit |
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Limit |
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(Note 3) |
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(Note 4) |
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(Note 3) |
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(Note 4) |
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REFERENCE SECTION |
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VREF |
Output Voltage |
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5 |
4.85 |
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4.80 |
5 |
4.75 |
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VMin |
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5.15 |
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5.20 |
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5.25 |
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VMax |
VRLine |
Line Regulation |
VIN = 8V to 40V |
10 |
15 |
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30 |
10 |
25 |
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50 |
mVMax |
VRLoad |
Load Regulation |
IL = 0 mA to 20 mA |
10 |
15 |
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25 |
10 |
25 |
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50 |
mVMax |
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Ripple Rejection |
f = 120 Hz |
66 |
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66 |
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dB |
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IOS |
Short Circuit |
VREF = 0 |
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25 |
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25 |
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mA Min |
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Current |
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50 |
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50 |
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180 |
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200 |
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mA Max |
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NO |
Output Noise |
10 Hz ≤ f ≤ 10 kHz |
40 |
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100 |
40 |
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100 |
µVrms Max |
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Long Term |
TA = 125ÊC |
20 |
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20 |
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mV/kHr |
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Stability |
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OSCILLATOR SECTION |
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fOSC |
Max. Freq. |
RT = 1k, CT = 0.001 µF |
550 |
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500 |
350 |
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kHzMin |
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(Note 7) |
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fOSC |
Initial |
RT = 5.6k, CT = 0.01 µF |
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17.5 |
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17.5 |
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kHzMin |
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Accuracy |
(Note 7) |
20 |
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20 |
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22.5 |
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22.5 |
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kHzMax |
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RT = 2.7k, CT = 0.01 µF |
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34 |
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30 |
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kHzMin |
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(Note 7) |
38 |
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38 |
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42 |
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46 |
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kHzMax |
fOSC |
Freq. Change |
VIN = 8 to 40V |
0.5 |
1 |
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0.5 |
1.0 |
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%Max |
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with VIN |
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fOSC |
Freq. Change |
TA = −55ÊC to +125ÊC |
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with Temp. |
at 20 kHz RT = 5.6k, |
5 |
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5 |
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% |
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CT = 0.01 µF |
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VOSC |
Output Amplitude |
RT = 5.6k, CT = 0.01 µF |
3 |
2.4 |
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3 |
2.4 |
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VMin |
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(Pin 3) (Note 8) |
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tPW |
Output Pulse |
RT = 5.6k, CT = 0.01 µF |
0.5 |
1.5 |
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0.5 |
1.5 |
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µs Max |
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Width (Pin 3) |
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Sawtooth Peak |
RT = 5.6k, CT = 0.01 µF |
3.4 |
3.6 |
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3.8 |
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3.8 |
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VMax |
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Voltage |
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Sawtooth Valley |
RT = 5.6k, CT = 0.01 µF |
1.1 |
0.8 |
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0.6 |
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0.6 |
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VMin |
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Voltage |
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ERROR-AMP SECTION |
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VIO |
Input Offset |
VCM = 2.5V |
2 |
8 |
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10 |
2 |
10 |
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mVMax |
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Voltage |
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IIB |
Input Bias |
VCM = 2.5V |
1 |
8 |
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10 |
1 |
10 |
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µAMax |
www.national.com |
2 |
Electrical Characteristics (Continued)
(Note 1)
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LM2524D |
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LM3524D |
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Symbol |
Parameter |
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Conditions |
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Tested |
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Design |
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Tested |
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Design |
Units |
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Typ |
Limit |
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Limit |
Typ |
Limit |
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Limit |
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(Note 3) |
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(Note 4) |
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(Note 3) |
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(Note 4) |
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ERROR-AMP SECTION |
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Current |
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IIO |
Input Offset |
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VCM = 2.5V |
0.5 |
1.0 |
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1 |
0.5 |
1 |
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µAMax |
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Current |
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ICOSI |
Compensation |
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VIN(I) − V IN(NI) = 150 mV |
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65 |
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65 |
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µAMin |
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Current (Sink) |
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95 |
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95 |
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125 |
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125 |
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µAMax |
ICOSO |
Compensation |
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VIN(NI) − V IN(I) = 150 mV |
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−125 |
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−125 |
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µA Min |
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Current (Source) |
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−95 |
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−95 |
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−65 |
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−65 |
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µA Max |
AVOL |
Open Loop Gain |
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RL = ∞, VCM = 2.5 V |
80 |
74 |
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60 |
80 |
70 |
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60 |
dBMin |
VCMR |
Common Mode |
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1.5 |
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1.4 |
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1.5 |
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VMin |
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Input Voltage Range |
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5.5 |
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5.4 |
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5.5 |
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VMax |
CMRR |
Common Mode |
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90 |
80 |
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90 |
80 |
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dBMin |
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Rejection Ratio |
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GBW |
Unity Gain |
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AVOL = 0 dB, VCM = 2.5V |
3 |
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2 |
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MHz |
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Bandwidth |
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VO |
Output Voltage |
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RL = ∞ |
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0.5 |
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0.5 |
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VMin |
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Swing |
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5.5 |
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5.5 |
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VMax |
PSRR |
Power Supply |
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VIN = 8 to 40V |
80 |
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70 |
80 |
65 |
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dbMin |
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Rejection Ratio |
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COMPARATOR SECTION |
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Minimum Duty |
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Pin 9 = 0.8V, |
0 |
0 |
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0 |
0 |
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%Max |
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Cycle |
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[RT = 5.6k, CT = 0.01 µF] |
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Maximum Duty |
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Pin 9 = 3.9V, |
49 |
45 |
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49 |
45 |
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%Min |
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Cycle |
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[RT = 5.6k, CT = 0.01 µF] |
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Maximum Duty |
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Pin 9 = 3.9V, |
44 |
35 |
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44 |
35 |
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%Min |
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Cycle |
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[RT = 1k, CT = 0.001 µF] |
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VCOMPZ |
Input Threshold |
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Zero Duty Cycle |
1 |
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1 |
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V |
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(Pin 9) |
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VCOMPM |
Input Threshold |
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Maximum Duty Cycle |
3.5 |
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3.5 |
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V |
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(Pin 9) |
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IIB |
Input Bias |
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−1 |
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−1 |
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µA |
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Current |
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CURRENT LIMIT SECTION |
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VSEN |
Sense Voltage |
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V(Pin 2) − V (Pin 1) ³ |
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180 |
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180 |
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mVMin |
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150 mV |
200 |
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200 |
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220 |
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220 |
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mVMax |
TC-Vsense |
Sense Voltage T.C. |
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0.2 |
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0.2 |
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mV/ÊC |
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Common Mode |
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−0.7 |
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−0.7 |
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V Min |
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Voltage Range |
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V5 − V 4 = 300 mV |
1 |
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1 |
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VMax |
SHUT DOWN SECTION |
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VSD |
High Input |
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V(Pin 2) − V (Pin 1) ³ |
1 |
0.5 |
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1 |
0.5 |
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VMin |
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Voltage |
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150 mV |
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1.5 |
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1.5 |
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VMax |
ISD |
High Input |
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I(pin 10) |
1 |
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1 |
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mA |
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Current |
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OUTPUT SECTION (EACH OUTPUT) |
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VCES |
Collector Emitter |
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IC £ 100 µA |
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55 |
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40 |
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VMin |
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Voltage Breakdown |
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3 |
www.national.com |
Electrical Characteristics (Continued)
(Note 1)
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LM2524D |
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LM3524D |
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Symbol |
Parameter |
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Conditions |
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Tested |
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Design |
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Tested |
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Design |
Units |
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Typ |
Limit |
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Limit |
Typ |
Limit |
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Limit |
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(Note 3) |
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(Note 4) |
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(Note 3) |
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(Note 4) |
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OUTPUT SECTION (EACH OUTPUT) |
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ICES |
Collector Leakage |
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VCE = 60V |
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Current |
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VCE = 55V |
0.1 |
50 |
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µAMax |
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VCE = 40V |
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0.1 |
50 |
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VCESAT |
Saturation |
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IE = 20 mA |
0.2 |
0.5 |
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0.2 |
0.7 |
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VMax |
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Voltage |
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IE = 200 mA |
1.5 |
2.2 |
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1.5 |
2.5 |
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VEO |
Emitter Output |
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IE = 50 mA |
18 |
17 |
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18 |
17 |
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VMin |
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Voltage |
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tR |
Rise Time |
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VIN = 20V, |
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IE = −250 µA |
200 |
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200 |
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ns |
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RC = 2k |
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tF |
Fall Time |
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RC = 2k |
100 |
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100 |
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ns |
SUPPLY CHARACTERISTICS SECTION |
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VIN |
Input Voltage |
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After Turn-on |
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8 |
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8 |
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VMin |
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Range |
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40 |
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40 |
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VMax |
T |
Thermal Shutdown |
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(Note 2) |
160 |
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160 |
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ÊC |
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Temp. |
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IIN |
Stand By Current |
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VIN = 40V (Note 6) |
5 |
10 |
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5 |
10 |
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mA |
Note 1: Unless otherwise stated, these specifications apply for TA = TJ = 25ÊC. Boldface numbers apply over the rated temperature range: LM2524D is −40Ê to 85ÊC and LM3524D is 0ÊC to 70ÊC. VIN = 20V and fOSC = 20 kHz.
Note 2: For operation at elevated temperatures, devices in the N package must be derated based on a thermal resistance of 86ÊC/W, junction to ambient. Devices in the M package must be derated at 125ÊC/W, junction to ambient.
Note 3: Tested limits are guaranteed and 100% tested in production.
Note 4: Design limits are guaranteed (but not 100% production tested) over the indicated temperature and supply voltage range. These limits are not used to calculate outgoing quality level.
Note 5: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its rated operating conditions.
Note 6: Pins 1, 4, 7, 8, 11, and 14 are grounded; Pin 2 = 2V. All other inputs and outputs open.
Note 7: The value of a Ct capacitor can vary with frequency. Careful selection of this capacitor must be made for high frequency operation. Polystyrene was used in this test. NPO ceramic or polypropylene can also be used.
Note 8: OSC amplitude is measured open circuit. Available current is limited to 1 mA so care must be exercised to limit capacitive loading of fast pulses.
Typical Performance Characteristics
Switching Transistor |
Maximum Average Power |
Maximum & Minimum |
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Peak Output Current |
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Dissipation (N, M Packages) |
Duty Cycle Threshold |
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vs Temperature |
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Voltage |
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DS008650-29
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DS008650-30
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Typical Performance Characteristics (Continued)
Output Transistor |
Output Transistor Emitter |
Saturation Voltage |
Voltage |
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Standby Current |
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Standby Current |
vs Voltage |
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vs Temperature |
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Test Circuit
Reference Transistor
Peak Output Current
DS008650-33
Current Limit Sense Voltage
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DS008650-4
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Functional Description
INTERNAL VOLTAGE REGULATOR
The LM3524D has an on-chip 5V, 50 mA, short circuit protected voltage regulator. This voltage regulator provides a supply for all internal circuitry of the device and can be used as an external reference.
For input voltages of less than 8V the 5V output should be shorted to pin 15, VIN, which disables the 5V regulator. With these pins shorted the input voltage must be limited to a maximum of 6V. If input voltages of 6V±8V are to be used, a pre-regulator, as shown in Figure 1, must be added.
DS008650-10
*Minimum CO of 10 µF required for stability.
FIGURE 1.
OSCILLATOR
The LM3524D provides a stable on-board oscillator. Its frequency is set by an external resistor, RT and capacitor, CT. A graph of RT, CT vs oscillator frequency is shown is Figure 2. The oscillator's output provides the signals for triggering an internal flip-flop, which directs the PWM information to the outputs, and a blanking pulse to turn off both outputs during transitions to ensure that cross conduction does not occur. The width of the blanking pulse, or dead time, is controlled by the value of CT, as shown in Figure 3. The recommended values of RT are 1.8 kΩ to 100 kΩ, and for CT, 0.001 µF to 0.1 µF.
If two or more LM3524D's must be synchronized together, the easiest method is to interconnect all pin 3 terminals, tie all pin 7's (together) to a single CT, and leave all pin 6's open except one which is connected to a single RT. This method works well unless the LM3524D's are more than 6" apart.
A second synchronization method is appropriate for any circuit layout. One LM3524D, designated as master, must have its RTCT set for the correct period. The other slave LM3524D(s) should each have an RTCT set for a 10% longer period. All pin 3's must then be interconnected to allow the master to properly reset the slave units.
The oscillator may be synchronized to an external clock source by setting the internal free-running oscillator frequency 10% slower than the external clock and driving pin 3 with a pulse train (approx. 3V) from the clock. Pulse width should be greater than 50 ns to insure full synchronization.
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FIGURE 2.
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FIGURE 3.
ERROR AMPLIFIER
The error amplifier is a differential input, transconductance amplifier. Its gain, nominally 86 dB, is set by either feedback or output loading. This output loading can be done with either purely resistive or a combination of resistive and reactive components. A graph of the amplifier's gain vs output load resistance is shown in Figure 4.
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FIGURE 4.
The output of the amplifier, or input to the pulse width modulator, can be overridden easily as its output impedance is very high (ZO 5 MΩ). For this reason a DC voltage can be
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