MOTOROLA MC74VHCT125AD, MC74VHCT125ADT, MC74VHCT125ADTR2 Datasheet
Semiconductor Components Industries, LLC, 2000
April, 2000 – Rev. 1
1 Publication Order Number:
MC74VHCT125A/D
MC74VHCT125A
Quad Bus Buffer
with 3–State Control Inputs
The MC74VHCT125A is a high speed CMOS quad bus buffer
fabricated with silicon gate CMOS technology . It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The MC74VHCT125A requires the 3–state control input (OE
) to be
set High to place the output into the high impedance state.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3V to 5.0V, because it has
full 5V CMOS level output swings.
The VHCT125A input structures provide protection when voltages
between 0V and 5.5V are applied, regardless of the supply voltage.
The output structures also provide protection when VCC = 0V. These
input and output structures help prevent device destruction caused by
supply voltage – input/output voltage mismatch, battery backup, hot
insertion, etc.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
• High Speed: t
PD
= 3.8ns (Typ) at VCC = 5V
• Low Power Dissipation: I
CC
= 4µA (Max) at TA = 25°C
• TTL–Compatible Inputs: V
IL
= 0.8V; VIH = 2.0V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
OLP
= 0.8V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V ; Machine Model > 200V
• Chip Complexity: 72 FETs or 18 Equivalent Gates
LOGIC DIAGRAM
Active–Low Output Enables
Y1
Y2
Y4
3
6
8
11
13
12
10
9
4
5
1
2
A1
OE1
A2
OE2
A3
OE3
A4
OE4
Y3
FUNCTION TABLE
VHCT125A
Inputs Output
AOE
Y
HL H
LL L
XH Z
14–LEAD SOIC
D SUFFIX
CASE 751A
http://onsemi.com
14–LEAD TSSOP
DT SUFFIX
CASE 948G
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
Device Package Shipping
ORDERING INFORMATION
MC74VHCT125AD SOIC 55 Units/Rail
MC74VHCT125ADT TSSOP
96 Units/Rail
14–LEAD SOIC EIAJ
M SUFFIX
CASE 965
MC74VHCT125AM SOIC EIAJ
50 Units/Rail
For detailed package marking information, see the Marking
Diagram section on page 4 of this data sheet.
11
12
13
14
8
9
105
4
3
2
1
7
6
OE3
Y4
A4
OE4
V
CC
Y3
A3
OE2
Y1
A1
OE1
GND
Y2
A2
MC74VHCT125A
http://onsemi.com
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage
– 0.5 to + 7.0
V
V
in
DC Input Voltage
– 0.5 to + 7.0
V
V
out
DC Output Voltage
– 0.5 to VCC + 0.5
V
I
IK
Input Diode Current
– 20
mA
I
OK
Output Diode Current
± 20
mA
I
out
DC Output Current, per Pin
± 25
mA
I
CC
DC Supply Current, VCC and GND Pins
± 50
mA
ÎÎ
Î
P
D
ОООООООООООО
Î
Power Dissipation in Still Air, SOIC Packages†
TSSOP Package†
ÎÎÎ
Î
500
450
Î
Î
mW
T
stg
Storage Temperature
– 65 to + 150
_
C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not
implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
ÎÎ
Max
Unit
V
CC
DC Supply Voltage
4.5
ÎÎ
5.5
V
V
in
DC Input Voltage
0
ÎÎ
5.5
V
V
out
DC Output Voltage
0
ÎÎ
V
CC
V
T
A
Operating Temperature, All Package Types
– 40
ÎÎ
+ 85
_
C
tr, t
f
Input Rise and Fall Time VCC =5.0V ±0.5V
0
ÎÎ
20
ns/V
DC ELECTRICAL CHARACTERISTICS
V
TA = 25°C
TA ≤ 85°C
TA ≤ 125°C
Symbol
Parameter
Test Conditions
V
CC
(V)
Min
Typ
Max
Min
Max
Min
Max
Unit
ÎÎ
Î
V
IH
ОООООО
Î
Minimum High–Level Input
Voltage
ÎÎÎÎÎÎ
Î
3.0
4.5
5.5
Î
Î
1.2
2.0
2.0
ÎÎÎÎÎ
Î
1.2
2.0
2.0
ÎÎÎ
Î
1.2
2.0
2.0
Î
Î
V
ÎÎ
Î
ÎÎ
Î
V
IL
ОООООО
Î
ОООООО
Î
Maximum Low–Level Input
Voltage
ÎÎÎÎ
Î
ÎÎÎÎ
Î
Î
Î
Î
Î
3.0
4.5
5.5
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
0.53
0.8
0.8
Î
Î
Î
Î
Î
Î
Î
Î
0.53
0.8
0.8
Î
Î
Î
Î
Î
Î
Î
Î
0.53
0.8
0.8
V
V
OH
Minimum High–Level
Output Voltage
VIN = VIH or V
IL
IOH = – 50µA
3.0
4.5
2.9
4.4
3.0
4.5
2.9
4.4
2.9
4.4
V
ÎÎÎОООООО
Î
VIN = VIH or V
IL
ÎÎÎÎ
Î
VIN = VIH or V
IL
IOH = – 4mA
IOH = – 8mA
Î
Î
3.0
4.5
Î
Î
2.58
3.94
ÎÎÎÎÎ
Î
2.48
3.80
ÎÎÎ
Î
2.34
3.66
Î
Î
ÎÎ
Î
V
OL
ОООООО
Î
Maximum Low–Level
Output Voltage
ÎÎÎÎ
Î
VIN = VIH or V
IL
IOL = 50µA
Î
Î
3.0
4.5
ÎÎÎ
Î
0.0
0.0
Î
Î
0.1
0.1
ÎÎÎ
Î
0.1
0.1
ÎÎÎ
Î
0.1
0.1
V
ÎÎÎОООООО
Î
VIN = VIH or V
IL
ÎÎÎÎ
Î
VIN = VIH or V
IL
IOL = 4mA
IOL = 8mA
Î
Î
3.0
4.5
ÎÎÎÎÎ
Î
0.36
0.36
ÎÎÎ
Î
0.44
0.44
ÎÎÎ
Î
0.52
0.52
I
IN
Maximum Input Leakage
Current
VIN = 5.5 V or
GND
0 to 5.5
± 0.1
± 1.0
± 1.0
µA
ÎÎ
Î
I
CC
ОООООО
Î
Maximum Quiescent Supply
Current
ÎÎÎÎ
Î
VIN = VCC or GND
Î
Î
5.5
ÎÎÎÎÎ
Î
2.0
ÎÎÎ
Î
20
ÎÎÎ
Î
40
µA
I
CCT
Quiescent Supply Current
Input: VIN = 3.4V
5.5
1.35
1.50
1.65
mA
I
OPD
Output Leakage Current
V
OUT
= 5.5V
0.0
0.5
5.0
10
µA
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
out
should be constrained to the
range GND v (Vin or V
out
) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74VHCT125A
http://onsemi.com
3
AC ELECTRICAL CHARACTERISTICS (Input t
r
= tf = 3.0ns)
TA = 25°C
TA = ≤ 85°C
TA ≤ 125°C
Symbol
Parameter
Test Conditions
Min
Typ
Max
Min
Max
Min
Max
Unit
ÎÎ
Î
t
PLH
,
t
PHL
ОООООО
Î
Maximum Propagation
Delay, A to Y
ОООООО
Î
VCC = 3.3 ± 0.3V CL = 15pF
CL = 50pF
ÎÎÎ
Î
5.6
8.1
Î
Î
8.0
11.5
Î
Î
1.0
1.0
Î
Î
9.5
13.0
ÎÎÎ
Î
12.0
16.0
ns
VCC = 5.0 ± 0.5V CL = 15pF
CL = 50pF
3.8
5.3
5.5
7.5
1.0
1.0
6.5
8.5
8.5
10.5
ÎÎ
Î
t
PZL
,
t
PZH
ОООООО
Î
Maximum Output Enable
TIme,OE
to Y
ОООООО
Î
VCC = 3.3 ± 0.3V CL = 15pF
RL = 1kΩ CL = 50pF
ÎÎÎ
Î
5.4
7.9
Î
Î
8.0
11.5
Î
Î
1.0
1.0
Î
Î
9.5
13.0
ÎÎÎ
Î
11.5
15.0
ns
ÎÎÎООООООÎОООООО
Î
VCC = 5.0 ± 0.5V CL = 15pF
RL = 1kΩ CL = 50pF
ÎÎÎ
Î
3.6
5.1
Î
Î
5.1
7.1
Î
Î
1.0
1.0
Î
Î
6.0
8.0
ÎÎÎ
Î
7.5
9.5
t
PLZ
,
t
PHZ
Maximum Output Disable
Time,OE
to Y
VCC = 3.3 ± 0.3V CL = 50pF
RL = 1kΩ
9.5
13.2
1.0
15.0
18.0
ns
ÎÎÎООООООÎОООООО
Î
VCC = 5.0 ± 0.5V CL = 50pF
RL = 1kΩ
ÎÎÎ
Î
6.1
Î
Î
8.8
Î
Î
1.0
Î
Î
10.0
ÎÎÎ
Î
12.0
ÎÎ
Î
t
OSLH
,
t
OSHL
ОООООО
Î
Output–to–Output Skew
ОООООО
Î
VCC = 3.3 ± 0.3V CL = 50pF
(Note 1.)
ÎÎÎÎÎ
Î
1.5
ÎÎÎ
Î
1.5
ÎÎÎ
Î
2.0
ns
VCC = 5.0 ± 0.5V CL = 50pF
(Note 1.)
1.0
1.0
1.5
ÎÎ
Î
C
in
ОООООО
Î
Maximum Input
Capacitance
ООООООÎÎÎÎ
Î
4
Î
Î
10
ÎÎÎ
Î
10
ÎÎÎ
Î
10
pF
ÎÎ
Î
C
out
ОООООО
Î
Maximum Three–State
Output Capacitance (Output
in High Impedance State)
ООООООÎÎÎÎ
Î
6
ÎÎÎÎÎÎÎÎÎ
Î
pF
Typical @ 25°C, VCC = 5.0V
C
PD
Power Dissipation Capacitance (Note 2.)
14
pF
1. Parameter guaranteed by design. t
OSLH
= |t
PLHm
– t
PLHn
|, t
OSHL
= |t
PHLm
– t
PHLn
|.
2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= CPD VCC fin + ICC/4 (per buffer). CPD is used to determine the
no–load dynamic power consumption; PD = CPD V
CC
2
fin + ICC VCC.
NOISE CHARACTERISTICS (Input t
r
= tf = 3.0ns, CL = 50pF, VCC = 5.0V)
TA = 25°C
Symbol Characteristic
Typ Max
Unit
V
OLP
Quiet Output Maximum Dynamic V
OL
0.3 0.8 V
V
OLV
Quiet Output Minimum Dynamic V
OL
– 0.3 – 0.8 V
V
IHD
Minimum High Level Dynamic Input Voltage 3.5 V
V
ILD
Maximum Low Level Dynamic Input Voltage 1.5 V
Loading...