MOTOROLA MC74VHCT08ADTR2, MC74VHCT08AD, MC74VHCT08ADR2 Datasheet
SEMICONDUCTOR TECHNICAL DATA
The MC74VHCT08A is an advanced high speed CMOS 2–input AND gate
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V , because it has full 5V CMOS
level output swings.
The VHCT08A input structures provide protection when voltages between
0V and 5.5V are applied, regardless of the supply voltage. The output
structures also provide protection when VCC = 0V. These input and output
structures help prevent device destruction caused by supply voltage –
input/output voltage mismatch, battery backup, hot insertion, etc.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
• High Speed: tPD = 4.3ns (Typ) at VCC = 5V
• Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C
• TTL–Compatible Inputs: VIL = 0.8V; VIH = 2.0V
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
• Low Noise: V
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 24 FETs or 6 Equivalent Gates
= 0.8V (Max)
OLP
1
A1
2
B1
4
A2
5
B2
9
A3
10
B3
12
A4
13
B4
LOGIC DIAGRAM
3
Y1
6
Y2
Y = AB
8
Y3
11
Y4
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
14–LEAD TSSOP PACKAGE
14–LEAD SOIC EIAJ PACKAGE
MC74VHCTXXAD
MC74VHCTXXADT
MC74VHCTXXAM
DT SUFFIX
CASE 948G–01
M SUFFIX
CASE 965–01
ORDERING INFORMATION
SOIC
TSSOP
SOIC EIAJ
FUNCTION TABLE
Inputs Output
AB
L
L
H
H
L
H
L
H
Y
L
L
L
H
4/99
Motorola, Inc. 1999
Pinout: 14–Lead Packages (Top View)
VCCB4 A4 Y4 B3 A3 Y3
1314 12 11 10 9 8
21 34567
A1 B1 Y1 A2 B2 Y2 GND
1
REV 0
MC74VHCT08A
Î
Î
Î
Î
V
CC
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
Î
MAXIMUM RATINGS*
Symbol
V
V
I
I
I
Î
T
DC Supply Voltage
CC
V
DC Input Voltage
in
DC Output Voltage
out
I
Input Diode Current
IK
Output Diode Current
OK
DC Output Current, per Pin
out
DC Supply Current, VCC and GND Pins
CC
P
Power Dissipation in Still Air, SOIC Packages†
D
ОООООООООООО
Storage Temperature
stg
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
V
V
T
tr, t
DC Supply Voltage
CC
DC Input Voltage
in
DC Output Voltage
out
Operating Temperature
A
Input Rise and Fall Time VCC = 5.0V ±0.5V
f
Parameter
Parameter
TSSOP Package†
Value
– 0.5 to + 7.0
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
– 20
± 20
± 25
± 50
500
450
ÎÎÎÎ
– 65 to + 150
Min
Max
4.5
5.5
0
5.5
0
V
CC
– 40
+ 85
0
20
Unit
V
V
V
mA
mA
mA
mA
mW
Î
_
C
Unit
V
V
V
_
C
ns/V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
V
should be constrained to the
out
range GND v (Vin or V
Unused inputs must always be
) v VCC.
out
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
DC ELECTRICAL CHARACTERISTICS
Symbol
V
Minimum High–Level Input
IH
Î
Î
Î
V
Î
Voltage
ОООООО
V
Maximum Low–Level Input
IL
ОООООО
Voltage
ОООООО
Minimum High–Level
OH
ОООООО
Output Voltage
VIN = VIH or V
ÎÎОООООО
V
Î
ÎÎОООООО
I
Î
I
CCT
I
OPD
Maximum Low–Level
OL
Output Voltage
ОООООО
VIN = VIH or V
I
Maximum Input Leakage
IN
Current
Maximum Quiescent Supply
CC
Current
ОООООО
Quiescent Supply Current
Output Leakage Current
Parameter
IL
IL
ОООООÎÎ
ООООО
ООООО
VIN = VIH or V
ООООО
IOH = – 50µA
VIN = VIH or V
IOH = – 4mA
ООООО
IOH = – 8mA
VIN = VIH or V
IOL = 50µA
ООООО
VIN = VIH or V
IOL = 4mA
IOL = 8mA
ООООО
VIN = 5.5 V or GND
VIN = VCC or GND
ООООО
Input: VIN = 3.4V
V
Test Conditions
IL
IL
IL
IL
= 5.5V
OUT
V
(V)
3.0
4.5
5.5
3.0
Î
4.5
5.5
Î
3.0
Î
4.5
3.0
Î
4.5
3.0
4.5
Î
3.0
4.5
Î
0 to 5.5
5.5
Î
5.5
0.0
TA = 25°C
Min
Typ
Max
1.2
2.0
Î
ÎÎÎÎÎ
2.0
0.53
Î
Î
Î
Î
ÎÎÎ
Î
Î
2.9
3.0
Î
4.4
4.5
2.58
ÎÎÎÎÎ
3.94
0.0
0.0
Î
0.8
0.8
Î
ÎÎÎ
0.1
0.1
Î
0.36
ÎÎÎÎÎ
0.36
± 0.1
2.0
ÎÎÎÎÎ
1.35
0.5
TA ≤ 85°C
Min
Max
1.2
2.0
ÎÎÎ
2.0
0.53
Î
Î
2.48
3.80
2.9
4.4
Î
0.8
0.8
Î
ÎÎÎ
ÎÎÎ
0.1
ÎÎÎ
0.1
0.44
0.44
ÎÎÎ
± 1.0
20
ÎÎÎ
1.50
5.0
TA ≤ 125°C
Min
Max
1.2
2.0
ÎÎÎ
2.0
0.53
Î
Î
2.9
4.4
2.34
3.66
Î
0.8
0.8
Î
ÎÎÎ
ÎÎÎ
0.1
ÎÎÎ
0.1
0.52
0.52
ÎÎÎ
± 1.0
40εA
ÎÎÎ
1.65
10
Unit
V
V
Î
Î
V
V
Î
Î
µA
mA
µA
MOTOROLA VHC Data – Advanced CMOS Logic
2
DL203 — Rev 1
MC74VHCT08A
ОООООООО
ОООООООО
Î
Î
ОООООООО
Î
Î
Î
Î
Î
Î
ОООООООО
Î
Î
Î
Î
Î
Î
Î
ОООООООО
Î
Î
Î
Î
AC ELECTRICAL CHARACTERISTICS (Input t
Symbol
t
,
PLH
t
Î
ÎÎООООООО
Î
Maximum Propagation
Delay,
ООООООО
PHL
Input A or B to Y
C
Maximum Input Capacitance
in
ООООООО
Parameter
VCC = 3.0 ± 0.3V CL = 15pF
ООООООО
VCC = 5.0 ± 0.5V CL = 15pF
ООООООО
ОООООООÎÎÎÎ
= tf = 3.0ns)
r
Test Conditions
CL = 50pF
CL = 50pF
TA = 25°C
Min
Typ
6.2
ÎÎÎ
8.7
4.3
ÎÎÎ
5.8
4
Max
8.8
12.3
Î
5.9
7.9
Î
10
Î
TA ≤ 85°C
Min
Max
10.5
14.0
ÎÎÎ
7.0
ÎÎÎ
ÎÎÎ
9.0
10
TA ≤ 125°C
Max
Max
14.0
17.5
ÎÎÎ
9.0
11.0
ÎÎÎ
ÎÎÎ
10ÎpF
Unit
ns
Î
Î
Typical @ 25°C, VCC = 5.0V
C
Power Dissipation Capacitance (Note 1.)
PD
20
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
dynamic power consumption; PD = CPD V
NOISE CHARACTERISTICS (Input t
= tf = 3.0 ns, CL = 50pF, VCC = 5.0 V)
r
2
fin + ICC VCC.
CC
CC(OPR
= CPD VCC fin + ICC/4 (per gate). CPD is used to determine the no–load
)
TA = 25°C
Symbol Characteristic
V
V
V
V
OLP
OLV
IHD
ILD
Quiet Output Maximum Dynamic V
Quiet Output Minimum Dynamic V
OL
OL
Minimum High Level Dynamic Input Voltage 3.5 V
Maximum Low Level Dynamic Input Voltage 1.5 V
Typ Max
0.3 0.8 V
– 0.3 – 0.8 V
Unit
A or B
Y
1.5V
t
PLH
1.5V
Figure 1. Switching Waveforms
t
PHL
3.0V
GND
V
OH
V
OL
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
Figure 2. T est Circuit
VHC Data – Advanced CMOS Logic
DL203 — Rev 1
3 MOTOROLA
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