The 38C3 group uses the standard 740 family instruction set. Refer
to the table of 740 family addressing modes and machine instruc-
tions or the 740 Family Software Manual for details on the instruction
set.
Machine-resident 740 family instructions are as follows:
The FST and SLW instruction cannot be used.
The STP, WIT, MUL, and DIV instruction can be used.
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and the
internal system clock selection bit.
The CPU mode register is allocated at address 003B
16.
Fig. 5 Structure of CPU mode register
8
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
192
256
384
512
640
768
896
1024
00FF
16
013F
16
01BF
16
023F
16
02BF
16
033F
16
03BF
16
043F
16
RAM area
RAM size
(bytes)
Address
XXXX
16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
F000
16
E000
16
D000
16
C000
16
B000
16
A000
16
9000
16
8000
16
7000
16
6000
16
5000
16
4000
16
F080
16
E080
16
D080
16
C080
16
B080
16
A080
16
9080
16
8080
16
7080
16
6080
16
5080
16
4080
16
ROM area
ROM size
(bytes)
Address
YYYY
16
Address
ZZZZ
16
0058
16
0000
16
0040
16
0440
16
FF00
16
FFDC
16
FFFE
16
FFFF
16
XXXX
16
YYYY
16
ZZZZ
16
RAM
ROM
0050
16
Reserved area
SFR area 1
Not used
Interrupt vector area
Reserved ROM area
(128 bytes)
Zero page
Special page
LCD display RAM area
Reserved ROM area
ROM corrective RAM area
0100
16
(Note 1)
SFR area 2 (Note 1)
0F00
16
0FFF
16
Note 1 : This is valid only in mask ROM version.
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control
registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
Access to this area with only 2 bytes is possible in the special page
addressing mode.
Fig. 6 Memory map diagram
9
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
Fig. 7 Memory map of special function register (SFR)
ROM correct high-order address register 1 (Note)
ROM correct high-order address register 2 (Note)
ROM correct high-order address register 3 (Note)
ROM correct high-order address register 4 (Note)
Port P8 output selection register (P8SEL)
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Serial I/O control register 1 (SIOCON1)
Serial I/O control register 2 (SIOCON2)
Serial I/O register (SIO)
Interrupt control register 2 (ICON2)
Timer 6 PWM register (T6PWM)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Timer 1 (T1)
Timer 3 (T3)
Timer 5 (T5)
Timer 6 (T6)
Timer 2 (T2)
Timer 4 (T4)
PULL register A (PULLA)
PULL register B (PULLB)
Timer 12 mode register (T12M)
Timer 34 mode register (T34M)
Timer 56 mode register (T56M)
Segment output enable register (SEG)
LCD mode register (LM)
A-D control register (ADCON)
A-D conversion register (low) (ADL)
Port P8 (P8)
Port P8 direction register (P8D)
φ output control register (CKOUT)
Timer A register (low) (TAL)
Timer A register (high) (TAH)
Compare register (low) (CONAL)
Compare register (high) (CONAH)
Timer A mode register (TAM)
Timer A control register (TACON)
A-D conversion register (high) (ADH)
0F0A
16
0F0B
16
0F0C
16
0F0D
16
0F0E
16
0F0F
16
0F10
16
0F11
16
ROM correct enable register 1 (Note)
ROM correct low-order address register 1 (Note)
ROM correct high-order address register 5 (Note)
ROM correct low-order address register 5 (Note)
ROM correct high-order address register 6 (Note)
ROM correct low-order address register 6 (Note)
ROM correct high-order address register 7 (Note)
ROM correct low-order address register 7 (Note)
ROM correct high-order address register 8 (Note)
ROM correct low-order address register 8 (Note)
0F01
16
0F02
16
0F03
16
0F07
16
0F08
16
0F09
16
0F04
16
0F05
16
0F06
16
ROM correct low-order address register 2 (Note)
ROM correct low-order address register 3 (Note)
ROM correct low-order address register 4 (Note)
Note: This register is valid only in mask ROM version.
10
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
I/O PORTS
[Direction Registers (ports P2, P4, P5
0, P52–P57,
and P6–P8)]
The I/O ports P2, P4, P50, P52–P57, and P6–P8 have direction reg-
isters which determine the input/output direction of each individual
pin. Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin becomes
an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are float-
ing. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
[Direction Registers (ports P0 and P1)]
Ports P0 and P1 have direction registers which determine the input/
output direction of each individual port.
Each port in a direction register corresponds to one port, each port
can be set to be input or output.
When “0” is written to the bit 0 of a direction register, that port be-
comes an input port. When “1” is written to that port, that port be-
comes an output port. Bits 1 to 7 of ports P0 and P1 direction regis-
ters are not used.
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL register
B (address 0017
16), ports except for ports P3 and P51 can control
either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with a
program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
Port P8 Output Selection
Ports P80 to P87 can be switched to N-channel open-drain output by
setting “1” to the port P8 output selection register.
Fig. 8 Structure of PULL register A and PULL register B
Pin
P00/SEG8 –
P07/SEG15
P10/SEG16 –
P17/SEG23
P20/SEG0 –
P27/SEG7
P30/SEG24 –
P37/SEG31
Name
Port P0
Port P1
Port P2
Port P3
Input/Output
Input/Output,
port unit
Input/Output,
port unit
Input/Output,
individual bits
Output,
individual bits
I/O format
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
CMOS 3-state output
CMOS 3-state output
Non-port function
LCD segment output
LCD segment output
LCD segment output
LCD segment output
Related SFRs
PULL register A
Segment output enable reg-
ister
PULL register A
Segment output enable reg-
ister
PULL register A
Segment output enable reg-
ister
Segment output enable reg-
ister
Ref. No.
(1)
(2)
Table 4 List of I/O port function (1)
Fig. 9 Structure of port P8 output selection register
P0
0
–P0
7
pull-down
P1
0
–P1
7
pull-down
P2
0
–P2
7
pull-down
Not used
P7
0
, P7
1
pull-up
P8
0
–P8
7
pull-up
PULL register A
(PULLA : address 0016
16
)
b7b0
P4
0
–P4
3
pull-up
P4
4
–P4
7
pull-up
P5
0
, P5
2
, P5
3
pull-up
P5
4
–P5
7
pull-up
P6
0
, P6
3
pull-up
P6
4
–P6
7
pull-up
Not used (return “0” when read)
0 : Disable
1 : Enable
PULL register B
(PULLB : address 0017
16
)
b7b0
Note :The contents of PULL register A and PULL register B
do not affect ports programmed as the output ports.
Not used (return “0” when read)
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
Port P8 output selection register
(P8SEL : address 0018
16)
b7b0
11
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
Pin
P40/SCLK2
P41/T1OUT
P42/T3OUT
P43/φ
P44/SIN
P45/SOUT
P46/SCLK1
P47/SRDY
P50/TAOUT
P51
P52/PWM1
P53/CNTR0
P54/CNTR1
P55/INT0
P56/INT1
P57/INT2
P60/AN0
–
P67/AN7
P70/XCIN
P71/XCOUT
P80 – P87
COM
0
– COM
3
Name
Port P4
Port P5
Port P6
Port P7
Port P8
Common
Input/Output
Input/Output,
individual bits
Input/Output,
individual bits
Input
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Output
I/O format
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
LCD common output
Non-port function
Serial I/O function I/O
Timer output
Timer output
φ clock output
Serial I/O function I/O
Timer A output
PWM output
External count I/O
External interrupt in-
put
A-D converter input
Sub-clock generating
circuit I/O
Key input (key-on
wake-up) interrupt in-
put
Related SFRs
Serial I/O control registers
1, 2
PULL register B
Timer 12 mode register
PULL register B
Timer 34 mode register
PULL register B
φ output control register
PULL register B
Serial I/O control registers
1, 2
PULL register B
Timer A mode register
Timer A control reigster
PULL register B
Timer 56 mode register
PULL register B
Interrupt edge selection reg-
ister
PULL register B
Interrupt edge selection reg-
ister
PULL register B
A-D control register
PULL register B
CPU mode register
PULL register A
Interrupt control register 2
PULL register A
LCD mode register
Ref. No.
(3)
(4)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(4)
(12)
(12)
(13)
(14)
(15)
(17)
(16)
Table 5 List of I/O port function (2)
Notes 1: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from V
CC to VSS through the input-stage gate.
2:For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double function ports as function I/O ports, refer to the
applicable sections.
12
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
Fig. 10 Port block diagram (1)
(6)Port P4
4
Serial I/O input
(1)Ports P0, P1, P2
Segment output enable bit
Pull-down control
Segment output enable bit
Direction register
Data bus
Port latch
V
L2
/V
L3
V
L1
/V
SS
(5)Port P4
3
φ
φ output control bit
(2)Port P3
Segment output enable bit
Pull-down control
Segment output enable bit
Data busPort latch
V
L2
/V
L3
V
L1
/V
SS
(4)Ports P4
1
, P4
2
, P5
2
Timer 1 output selection bit
Timer 3 output selection bit
Timer 6 output selection bit
Direction register
Pull-up control
Timer 1 output
Timer 3 output
Timer 6 output
(3)Port P4
0
Data bus
Serial I/O clock output
Serial I/O mode selection bit
Port latch
Direction register
Pull-up control
P-channel output disable bit
(Note)
Note : Port P0, P1 direction registers are only bit 0.
Data bus
Port latch
Port latch
Direction register
Data bus
Pull-up control
Data bus
Port latch
Direction register
Pull-up control
13
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
Fig. 11 Port block diagram (2)
(7)Port P4
5
Data bus
Serial I/O port selection bit
Serial I/O output
P-channel output disable bit
Port latch
Direction register
Pull-up control
(9)Port P4
7
Data bus
Serial I/O ready output
Port latch
S
RDY
output enable bit
Direction register
Pull-up control
(8)Port P4
6
Serial I/O clock output
Serial I/O clock input
Serial I/O mode selection bit
Port latch
Direction register
Pull-up control
P-channel output disable bit
(10)Port P5
0
Data bus
Port latch
Direction register
Pull-up control
Timer A output enable bit
Timer A output
(12)Ports P5
3
–P5
7
INT
0
–INT
2
interrupt input
Data bus
Direction register
Port latch
Pull-up control
(11)Port P5
1
Data bus
(Note)
Note: The initihal value of M version becomes “1” (output).
Data bus
CNTR
0
,CNTR
1
interrupt input
14
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
Fig. 12 Port block diagram (3)
(14)Port P7
0
Direction register
Data bus
Port latch
Port selection • pull-up control
Oscillator
Port P7
0
(15)Port P7
1
Direction register
Data bus
Port Xc switch bit
Port latch
Port selection • pull-up control
Sub-clock generating circuit input
(16)COM
0
–COM
3
V
L3
V
L2
V
L1
The gate input signal of each
transistor is controlled by the
LCD duty ratio and the bias
value.
(13)Port P6
Analog input pin selection bit
A-D conversion input
Data bus
Port latch
Direction register
Pull-up control
(17)Port P8
Key input (key-on wake-up) interrupt input
Data bus
Direction register
Port latch
Pull-up control
P-channel output disable bit
Port Xc switch bit
Port Xc switch bit
15
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
INTERRUPTS
Interrupts occur by sixteen sources: six external, nine internal, and
one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an in-
terrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding inter-
rupt request and enable bits are “1” and the interrupt disable flag is
“0”.
Interrupt enable bits can be set or cleared by software. Interrupt re-
quest bits can be cleared by software, but cannot be set by software.
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I flag disables all interrupts except the BRK instruction
interrupt and reset. If several interrupts requests occurs at the same
time the interrupt with highest priority is accepted first.
Interrupt Operation
By acceptance of an interrupt, the following operations are automati-
cally performed:
1.The processing being executed is stopped.
2.The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3.The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4.The interrupt jump destination address is read from the vector
table into the program counter.
■Notes on Interrupts
When the active edge of an external interrupt (INT
0 – INT2, CNTR0
or CNTR1) is set or an vector interrupt source where several interrupt
source is assigned to the same vector address is switched, the cor-
responding interrupt request bit may also be set. Therefore, take fol-
lowing sequence:
(1)Disable the interrupt.
(2)Change the active edge in interrupt edge selection register.
(3)Clear the set interrupt request bit to “0.”
(4)Enable the interrupt.
16
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
38C3 Group
Interrupt Source
Reset (Note 2)
INT0
INT1
INT2
Serial I/O
Timer A
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
CNTR0
CNTR1
Key input (Key-
on wake-up)
A-D conversion
BRK instruction
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Vector Addresses (Note 1)
High
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Interrupt Request
Generating Conditions
At reset
At detection of either rising or falling edge of
INT
0 intput
At detection of either rising or falling edge of
INT1 input
At detection of either rising or falling edge of
INT2 input
At completion of serial I/O data transmit/re-
ceive
At timer A underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
At detection of either rising or falling edge of
CNTR0 input
At detection of either rising or falling edge of
CNTR1 input
At falling of port P8 (at input) input logical level