Fairchild Semiconductor NM27C256Q100, NM27C256N200, NM27C256VE150, NM27C256V100, NM27C256QE250 Datasheet

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July 1998

NM27C256

262,144-Bit (32K x 8) High Performance CMOS EPROM

General Description

The NM27C256 is a 256K Electrically Programmable Read Only Memory. It is manufactured in Fairchild’s latest CMOS split gate EPROM technology which enables it to operate at speeds as fast as 90 ns access time over the full operating range.

The NM27C256 provides microprocessor-based systems extensive storage capacity for large portions of operating system and application software. Its 90 ns access time provides high speed operation with high-performance CPUs. The NM27C256 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed from EPROM storage, greatly enhancing system utility.

The NM27C256 is configured in the standard EPROM pinout which provides an easy upgrade path for systems which are currently using standard EPROMs.

The NM27C256 is one member of a high density EPROM Family which range in densities up to 4 Mb.

Features

■High performance CMOS

—90 ns access time

■JEDEC standard pin configuration

—28-pin PDIP package

—32-pin chip carrier

—28-pin CERDIP package

■Drop-in replacement for 27C256 or 27256

■Manufacturer’s identification code

Block Diagram

Data Outputs O0 - O7

VCC

GND

VPP

Output Enable

and Chip Enable Logic Output

CE/PGM

Buffers

Y Decoder	.
	.

Y Gating

A0 - A14
Address
Address
Inputs		.
Inputs		.
	X Decoder	. . . . .


		.
		.

DS010833-1

EPROM CMOS Performance High 8) x (32K Bit-262,144 NM27C256

www.fairchildsemi.com

Connection Diagrams

27C080

27C040

27C020

27C010 27C512

DlP

27C512

27C010

27C020

27C040

27C080

A19

XX/VPP

VCC

NM27C256

A16

VCC

XX/PGM

A18

A15

VPP

VCC

A17

A12

A14

A13

A11

OE/VPP

A10

CE/PGM

GND

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C256 pins.

DS010833-2

Commercial Temp. Range (0°C to +70°C) VCC = 5V ±10%

Parameter/Order Number	Access Time (ns)

NM27C256 Q, N, V 90	90

NM27C256 Q, N, V 100	100

NM27C256 Q, N, V 120	120

NM27C256 Q, N, V 150	150

NM27C256 Q, N, V 200	200

Extended Temp. Range (-40°C to +85°C) VCC = 5V ±10%

Parameter/Order Number	Access Time (ns)

NM27C256 QE, NE, VE 120	120

NM27C256 QE, NE, VE 150	150

NM27C256 QE, NE, VE 200	200

Note: Surface mount PLCC package available for commercial and extended temperature ranges only.

Package Types: NM27C256 Q, N, V XXX

Q = Quartz-Windowed Ceramic DIP

N = Plastic OTP DIP

V = Surface-Mount PLCC

•All Packages conform to the JEDEC standard.

•All versions are guaranteed to function for slower speeds.

			Pin Names

Symbol			Description

A0–A14			Addresses

CE/PGM			Chip Enable/Program

		OE	Output Enable

O0–O7			Outputs

	XX		Don’t Care (during Read)

PLCC

	7		12	PP	XX	CC	14	13
		A A V			XX	V A A


	4		3	2	1	32 31 30
A6		5						29	A8
A6		5						29	A8
A5		6						28	A9
A5		6						28	A9
A4		7						27	A11
A4		7						27	A11
A3		8						26	XX
A3		8						26	XX
A2		9						25	OE
A2		9						25	OE
A1		10						24	A10
A1		10						24	A10
		11						23
A0									CE/PGM
A0									CE/PGM
XX		12						22	O7
XX		12						22	O7
O0		13			17	18		21	O6
O0		13						21	O6
	14 15 16						19 20


		O	O	GND	XX	O	O	O
	1		2			3	4	5	DS010833-3
									DS010833-3

Top

EPROM CMOS Performance High 8) x (32K Bit-262,144 NM27C256

2	www.fairchildsemi.com

Absolute Maximum Ratings (Note 1)

Storage Temperature	-65°C to +150°C
All Input Voltages except A9 with
Respect to Ground	-0.6V to +7V
VPP and A9 with Respect
to Ground	-0.7V to +14V
VCC Supply Voltage with
Respect to Ground	-0.6V to +7V

ESD Protection			> 2000V
All Output Voltages with
Respect to Ground		VCC + 1.0V to GND -0.6V
Operating Range

Range	Temperature		VCC
Comm’l		0°C to +70°C	+5V ±10%

Industrial		-40°C to +85°C	+5V ±10%

Read Operation

DC Electrical Characteristics Over Operating Range with VPP = VCC

Symbol	Parameter					Test Conditions		Min	Max	Units

VIL	Input Low Level							-0.5	0.8	V
VIH	Input High Level							2.0	VCC +1	V
VOL	Output Low Voltage	IOL = 2.1 mA							0.4	V
VOH	Output High Voltage	IOH = -2.5 mA						3.5		V
ISB1	VCC Standby Current		CE		= VCC ±0.3V				100	μA
(Note 11)	(CMOS)

ISB2	VCC Standby Current (TTL)	CE = VIH							1	mA
ICC1	VCC Active Current						= VIL,f=5 MHz		35	mA
ICC1	VCC Active Current			CE	=	OE	= VIL,f=5 MHz		35	mA
	TTL Inputs	Inputs = VIH or VIL, I/O = 0 mA

IPP	VPP Supply Current	VPP = VCC							10	μA
VPP	VPP Read Voltage							VCC - 0.7	VCC	V
ILI	Input Load Current	VIN = 5.5V or GND						-1	1	μA
ILO	Output Leakage Current	VOUT = 5.5V or GND						-10	10	μA

AC Electrical Characteristics Over Operating Range with VPP = VCC

Symbol		Parameter				90					100				120		150		200		Units

						Min	Max			Min		Max			Min	Max	Min	Max	Min	Max

tACC	Address to Output Delay							90				100				120		150		200	ns
tCE								90				100				120		150		200
tCE	CE to Output Delay							90				100				120		150		200
tOE								35				50				50		50		50
tOE	OE to Output Delay							35				50				50		50		50
tDF	Output Disable to							30				30				35		45		45
(Note 2)	Output Float

tOH	Output Hold from					0					0				0		0		0
(Note 2)	Addresses,
	CE or		OE,	Whichever
	Occurred First

Capacitance (Note 2) TA = +25˚C, f = 1 MHz

Symbol	Parameter				Conditions				Typ		Max		Units

CIN	Input Capacitance				VIN = 0V				6		12			pF
COUT	Output Capacitance				VOUT = 0V				9		12			pF

EPROM CMOS Performance High 8) x (32K Bit-262,144 NM27C256

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AC Test Conditions

Output Load	1 TTL Gate and CL = 100 pF (Note 8)
Input Rise and Fall Times		≤ 5 ns
Input Pulse Levels		0.45 to 2.4V
Timing Measurement Reference Level (Note 10)
Inputs		0.8V and 2.0V
Outputs		0.8V and 2.0V

AC Waveforms (Note 6) (Note 7) (Note 9)

ADDRESSES	2.0V		ADDRESSES VALID
	0.8V
CE 2.0V
	0.8V
			tCE
OE 2.0V
	0.8V
			tOE
			(Note 3)
OUTPUT	2.0V	Hi-Z	VALID OUTPUT
	0.8V		VALID OUTPUT
	0.8V
			tACC
			(Note 3)

tCE

(Notes 4, 5)

tDF

(Notes 4, 5)

Hi-Z

tOH

DS010833-4

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note 2: This parameter is only sampled and is not 100% tested.

Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC.

Note 4: The tDF and tCF compare level is determined as follows:

High to TRI-STATE®, the measured VOH1 (DC) - 0.10V;

Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.

Note 5: TRI-STATE may be attained using OE or CE.

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 μF ceramic capacitor be used on every device between VCC and GND.

Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.

Note 8: TTL Gate: IOL = 1.6 mA, IOH = -400 μA. CL = 100 pF includes fixture capacitance.

Note 9: VPP may be connected to VCC except during programming.

Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

Note 11: CMOS inputs: VIL = GND ±0.3V, VIH = VCC ±0.3V.

Programming Characteristics (Note 12) (Note 13) (Note 14) (Note 15)

Symbol	Parameter	Conditions	Min	Typ	Max	Units

EPROM CMOS Performance High 8) x (32K Bit-262,144 NM27C256

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