March 1999
NM25C160
16K-Bit Serial CMOS EEPROM
(Serial Peripheral Interface (SPI) Synchronous Bus)
General Description
The NM25C160 is a 16,384-bit CMOS EEPROM with an SPI compatible serial interface. The NM25C160 is designed for data storage in applications requiring both non-volatile memory and insystem data updates. This EEPROM is well suited for applications using the 68HC11 series of microcontrollers that support the SPI interface for high speed communication with peripheral devices via a serial bus to reduce pin count. The NM25C160 is implemented in Fairchild Semiconductor’s floating gate CMOS process that provides superior endurance and data retention.
The serial data transmission of this device requires four signal lines to control the device operation: Chip Select (CS), Clock (SCK), Data In (SI), and Serial Data Out (SO). All programming cycles are completely self-timed and do not require an erase before WRITE.
BLOCK WRITE protection is provided by programming the STATUS REGISTER with one of four levels of write protection. Additionally, separate WRITE enable and WRITE disable instructions are provided for data protection.
Hardware data protection is provided by the WP pin to protect against inadvertent programming. The HOLD pin allows the serial communication to be suspended without resetting the serial sequence.
Features
■2.1 MHz clock rate @ 2.7V to 5.5V
■16,384 bits organized as 2,048 x 8
■Multiple chips on the same 3-wire bus with separate chip select lines
■Self-timed programming cycle
■Simultaneous programming of 1 to 16 bytes at a time
■Status register can be polled during programming to monitor READY/BUSY
■Write Protect (WP) pin and write disable instruction for both hardware and software write protection
■Block write protect feature to protect against accidental writes
■Endurance: 1,000,000 data changes
■Data retention greater than 40 years
■Packages available: 8-pin DIP, 8-pin SO, or 8-pin TSSOP
Block Diagram
CS |
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Instruction |
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VCC |
HOLD |
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VSS |
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Decoder |
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SCK |
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Control Logic |
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WP |
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SI |
Instruction |
and Clock |
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Register |
Generators |
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Address |
Program |
High Voltage |
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Enable |
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Counter/ |
Generator |
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Register |
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and |
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VPP |
Program |
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Timer |
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Decoder |
EEPROM Array |
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16,384 Bits |
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1 of 2048 |
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(2048 x 8) |
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Read/Write Amps |
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Data In/Out Register |
Data Out |
SO |
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8 Bits |
Buffer |
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Non-Volatile |
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Status Register |
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DS012402-1 |
(SPI) Interface Periphrial (Serial |
CMOS Serial Bit-16K NM25C160 |
Synchronous |
EEPROM |
Bus) |
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© 1999 Fairchild Semiconductor Corporation |
1 |
www.fairchildsemi.com |
NM25C160 Rev. D.1
Connection Diagram
Dual-In-Line Package (N), SO Package (M8),
and TSSOP Package (MT8)
CS |
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1 |
8 |
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VCC |
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SO |
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7 |
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HOLD |
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NM25C160 |
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WP |
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3 |
6 |
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SCK |
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VSS |
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4 |
5 |
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SI |
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DS012402-2
Top View
See Package Number N08E (N), M08A (M8), and MTC08 (MT8)
Pin Names
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CS |
Chip Select Input |
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SO |
Serial Data Output |
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WP |
Write Protect |
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VSS |
Ground |
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SI |
Serial Data Input |
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SCK |
Serial Clock Input |
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HOLD |
Suspends Serial Data |
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VCC |
Power Supply |
Ordering Information |
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NM 25 |
C |
XX LZ E XX |
Letter |
Description |
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Package |
N |
8-pin DIP |
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M8 |
8-pin SO |
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MT8 |
8-pin TSSOP |
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Temp. Range |
None |
0 to 70°C |
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V |
-40 to +125°C |
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E |
-40 to +85°C |
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Voltage Operating Range |
Blank |
4.5V to 5.5V |
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L |
2.7V to 4.5V |
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LZ |
2.7V to 4.5V and |
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<1μA Standby Current |
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Density/Mode |
160 |
16K, mode 0 |
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C |
CMOS technology |
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Interface |
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25 |
SPI |
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NM |
Fairchild Nonvolatile |
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Memory Prefix |
(SPI) Interface Periphrial (Serial |
CMOS Serial Bit-16K NM25C160 |
Synchronous |
EEPROM |
Bus) |
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2 |
www.fairchildsemi.com |
NM25C160 Rev. D.1
Standard Voltage 4.5 ≤ VCC ≤ 5.5V Specifications
Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature |
-65°C to +150°C |
All Input or Output Voltage with |
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Respect to Ground |
+6.5V to -0.3V |
Lead Temp. (Soldering, 10 sec.) |
+300°C |
ESD Rating |
2000V |
Operating Conditions
Ambient Operating Temperature |
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NM25C160 |
0°C to +70°C |
NM25C160E |
-40°C to +85°C |
NM25C160V |
-40°C to +125°C |
Power Supply (VCC) |
4.5V to 5.5V |
DC and AC Electrical Characteristics 4.5V ≤ VCC ≤ 5.5V (unless otherwise specified)
Symbol |
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Parameter |
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Conditions |
Min |
Max |
Units |
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ICC |
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Operating Current |
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= VIL |
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3 |
mA |
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CS |
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μA |
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ICCSB |
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Standby Current |
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CS = VCC |
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50 |
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IIL |
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Input Leakage |
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VIN = 0 to VCC |
-1 |
+1 |
μA |
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IOL |
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Output Leakage |
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VOUT = GND to VCC |
-1 |
+1 |
μA |
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VIL |
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CMOS Input Low Voltage |
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-0.3 |
VCC * 0.3 |
V |
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VIH |
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CMOS Input High Voltage |
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0.7 * VCC |
VCC + 0.3 |
V |
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VOL |
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Output Low Voltage |
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IOL = 1.6 mA |
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0.4 |
V |
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VOH |
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Output High Voltage |
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IOH = -0.8 mA |
VCC - 0.8 |
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V |
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fOP |
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SCK Frequency |
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2.1 |
MHz |
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tRI |
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Input Rise Time |
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2.0 |
μs |
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tFI |
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Input Fall Time |
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2.0 |
μs |
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tCLH |
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Clock High Time |
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(Note 2) |
190 |
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tCLL |
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Clock Low Time |
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(Note 2) |
190 |
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tCSH |
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Min CS High Time |
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(Note 3) |
240 |
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ns |
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tCSS |
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CS Setup Time |
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240 |
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tDIS |
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Data Setup Time |
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100 |
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ns |
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tHDS |
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HOLD Setup Time |
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90 |
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ns |
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tCSN |
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CS Hold Time |
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240 |
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tDIN |
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Data Hold Time |
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100 |
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ns |
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tHDN |
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HOLD Hold Time |
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90 |
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tPD |
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Output Delay |
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CL = 200 pF |
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240 |
ns |
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tDH |
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Output Hold Time |
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0 |
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tLZ |
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to Output Low Z |
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100 |
ns |
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HOLD |
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tDF |
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Output Disable Time |
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CL = 200 pF |
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240 |
ns |
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tHZ |
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to Output High Z |
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100 |
ns |
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HOLD |
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tWP |
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Write Cycle Time |
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1–16 Bytes |
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10 |
ms |
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Capacitance TA = 25°C, f = 2.1/1 MHz (Note 4) |
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AC Test Conditions |
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Output Load |
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CL = 200 pF |
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Symbol |
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Test |
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Typ |
Max |
Units |
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Input Pulse Levels |
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0.1 * VCC – 0.9 * VCC |
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COUT |
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Output Capacitance |
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3 |
8 |
pF |
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Timing Measurement Reference Level |
0.3 * VCC - 0.7 * VCC |
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CIN |
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Input Capacitance |
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2 |
6 |
pF |
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2: The fOP frequency specification specifies a minimum clock period of 1/fOP. Therefore, for every fOP clock cycle, tCLH + tCLL must be equal to or greater than 1/fOP. For example, if the 2.1MHz period = 476ns and tCLH = 190ns, tCLL must be 286ns.
Note 3: CS must be brought high for a minimum of tCSH between consecutive instruction cycles.
Note 4: This parameter is periodically sampled and not 100% tested.
(SPI) Interface Periphrial (Serial |
CMOS Serial Bit-16K NM25C160 |
Synchronous |
EEPROM |
Bus) |
|
3 |
www.fairchildsemi.com |
NM25C160 Rev. D.1