February 2000
NM93CS56
(MICROWIRE™ Bus Interface) 2048-Bit Serial EEPROM with Data Protect and Sequential Read
General Description
NM93CS56 is a 2048-bit CMOS non-volatile EEPROM organized as 128 x 16-bit array. This device features MICROWIRE interface which is a 4-wire serial bus with chipselect (CS), clock (SK), data input (DI) and data output (DO) signals. This interface is compatible to many of standard Microcontrollers and Microprocessors. NM93CS56 offers programmable write protection to the memory array using a special register called Protect Register. Selected memory locations can be protected against write by programming this Protect Register with the address of the first memory location to be protected (all locations greater than or equal to this first address are then protected from further change). Additionally, this address can be “permanently locked” into the device, making all future attempts to change data impossible. In addition this device features “sequential read”, by which, entire memory can be read in one cycle instead of multiple single byte read cycles. There are 10 instructions implemented on the NM93CS56, 5 of which are for memory operations and the remaining 5 are for Protect Register operations. This device is fabricated using Fairchild Semiconductor floating-gate CMOS process for high reliability, high endurance and low power consumption.
“LZ” and “L” versions of NM93CS56 offer very low standby current making them suitable for low power applications. This device is offered in both SO and TSSOP packages for small space considerations.
Features
■Wide VCC 2.7V - 5.5V
■Programmable write protection
■Sequential register read
■Typical active current of 200 A 10 A standby current typical 1 A standby current typical (L)
0.1 A standby current typical (LZ)
■No Erase instruction required before Write instruction
■Self timed write cycle
■Device status during programming cycles
■40 year data retention
■Endurance: 1,000,000 data changes
■Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP
Functional Diagram
CS |
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INSTRUCTION |
VCC |
SK |
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PRE |
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DECODER |
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CONTROL LOGIC |
PE |
DI |
INSTRUCTION |
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AND CLOCK |
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GENERATORS |
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REGISTER |
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COMPARATOR |
HIGH VOLTAGE |
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AND |
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ADDRESS |
PROTECT |
GENERATOR |
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WRITE ENABLE |
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REGISTER |
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AND |
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REGISTER |
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PROGRAM |
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TIMER |
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DECODER |
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EEPROM ARRAY |
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16 |
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READ/WRITE AMPS |
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16 |
VSS |
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DATA IN/OUT REGISTER |
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16 BITS |
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DO |
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DATA OUT BUFFER |
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EEPROM Serial Bit-2048 Interface) Bus (MICROWIRE NM93CS56 Read Sequential and Protect Data with
© 1999 Fairchild Semiconductor Corporation |
1 |
www.fairchildsemi.com |
NM93CS56 Rev. F.2
Connection Diagram
Dual-In-Line Package (N)
8–Pin SO (M8) and 8–Pin TSSOP (MT8)
CS |
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8 |
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VCC |
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SK |
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7 |
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PRE |
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DI |
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6 |
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PE |
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DO |
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4 |
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GND |
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Top View |
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Package Number |
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N08E, M08A and MTC08 |
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Pin Names |
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CS |
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Chip Select |
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SK |
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Serial Data Clock |
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DI |
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Serial Data Input |
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DO |
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Serial Data Output |
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GND |
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Ground |
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PE |
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Program Enable |
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PRE |
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Protect Register Enable |
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VCC |
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Power Supply |
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Ordering Information |
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NM 93 |
CS XX LZ E |
XXX |
Letter |
Description |
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Package |
N |
8-pin DIP |
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M8 |
8-pin SO |
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MT8 |
8-pin TSSOP |
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Temp. Range |
None |
0 to 70°C |
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V |
-40 to +125°C |
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E |
-40 to +85°C |
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Voltage Operating Range |
Blank |
4.5V to 5.5V |
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L |
2.7V to 5.5V |
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LZ |
2.7V to 5.5V and |
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<1 A Standby Current |
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Density |
56 |
2048 bits |
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C |
CMOS |
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CS |
Data protect and sequential |
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read |
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Interface |
93 |
MICROWIRE |
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Fairchild Memory Prefix |
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EEPROM Serial Bit-2048 Interface) Bus (MICROWIRE NM93CS56 Read Sequential and Protect Data with
2 |
www.fairchildsemi.com |
NM93CS56 Rev. F.2
Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature |
-65°C to +150°C |
All Input or Output Voltages |
+6.5V to -0.3V |
with Respect to Ground |
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Lead Temperature |
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(Soldering, 10 sec.) |
+300°C |
ESD rating |
2000V |
Operating Conditions
Ambient Operating Temperature |
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NM93CS56 |
0°C to +70°C |
NM93CS56E |
-40°C to +85°C |
NM93CS56V |
-40°C to +125°C |
Power Supply (VCC) |
4.5V to 5.5V |
DC and AC Electrical Characteristics VCC = 4.5V to 5.5V unless otherwise specified
Symbol |
Parameter |
Conditions |
Min |
Max |
Units |
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ICCA |
Operating Current |
CS = VIH, SK=1.0 MHz |
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1 |
mA |
ICCS |
Standby Current |
CS = VIL |
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50 |
A |
IIL |
Input Leakage |
VIN = 0V to VCC |
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±-1 |
A |
IOL |
Output Leakage |
(Note 2) |
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VIL |
Input Low Voltage |
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-0.1 |
0.8 |
V |
VIH |
Input High Voltage |
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2 |
VCC +1 |
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VOL1 |
Output Low Voltage |
IOL = 2.1 mA |
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0.4 |
V |
VOH1 |
Output High Voltage |
IOH = -400 A |
2.4 |
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VOL2 |
Output Low Voltage |
IOL = 10 A |
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0.2 |
V |
VOH2 |
Output High Voltage |
IOH = -10 A |
VCC - 0.2 |
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fSK |
SK Clock Frequency |
(Note 3) |
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1 |
MHz |
tSKH |
SK High Time |
0°C to +70°C |
250 |
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ns |
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-40°C to +125°C |
300 |
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tSKL |
SK Low Time |
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250 |
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ns |
tSKS |
SK Setup Time |
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50 |
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ns |
tCS |
Minimum CS Low Time |
(Note 4) |
250 |
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ns |
tCSS |
CS Setup Time |
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100 |
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ns |
tPRES |
PRE Setup Time |
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50 |
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ns |
tDH |
DO Hold Time |
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70 |
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ns |
tPES |
PE Setup Time |
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50 |
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ns |
tDIS |
DI Setup Time |
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100 |
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ns |
tCSH |
CS Hold Time |
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0 |
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ns |
tPEH |
PE Hold Time |
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250 |
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ns |
tPREH |
PRE Hold Time |
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50 |
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ns |
tDIH |
DI Hold Time |
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20 |
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tPD |
Output Delay |
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500 |
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tSV |
CS to Status Valid |
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500 |
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tDF |
CS to DO in Hi-Z |
CS = VIL |
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100 |
ns |
tWP |
Write Cycle Time |
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10 |
ms |
EEPROM Serial Bit-2048 Interface) Bus (MICROWIRE NM93CS56 Read Sequential and Protect Data with
3 |
www.fairchildsemi.com |
NM93CS56 Rev. F.2
Absolute Maximum Ratings (Note 1)
Ambient Storage Temperature |
-65°C to +150°C |
All Input or Output Voltages |
+6.5V to -0.3V |
with Respect to Ground |
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Lead Temperature |
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(Soldering, 10 sec.) |
+300°C |
ESD rating |
2000V |
Operating Conditions
Ambient Operating Temperature |
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NM93CS56L/LZ |
0°C to +70°C |
NM93CS56LE/LZE |
-40°C to +85°C |
NM93CS56LV/LZV |
-40°C to +125°C |
Power Supply (VCC) |
2.7V to 5.5V |
DC and AC Electrical Characteristics VCC = 2.7V to 5.5V unless otherwise specified
Symbol |
Parameter |
Conditions |
Min |
Max |
Units |
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ICCA |
Operating Current |
CS = VIH, SK=1.0 MHz |
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1 |
mA |
ICCS |
Standby Current |
CS = VIL |
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A |
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L |
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10 |
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LZ (2.7V to 4.5V) |
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1 |
A |
IIL |
Input Leakage |
VIN = 0V to VCC |
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±1 |
A |
IOL |
Output Leakage |
(Note 2) |
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VIL |
Input Low Voltage |
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-0.1 |
0.15VCC |
V |
VIH |
Input High Voltage |
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0.8VCC |
VCC +1 |
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VOL |
Output Low Voltage |
IOL = 10 A |
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0.1VCC |
V |
VOH |
Output High Voltage |
IOH = -10 A |
0.9VCC |
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fSK |
SK Clock Frequency |
(Note 3) |
0 |
250 |
KHz |
tSKH |
SK High Time |
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1 |
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s |
tSKL |
SK Low Time |
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1 |
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tSKS |
SK Setup Time |
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0.2 |
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s |
tCS |
Minimum CS Low Time |
(Note 4) |
1 |
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tCSS |
CS Setup Time |
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0.2 |
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s |
tPRES |
PRE Setup Time |
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50 |
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tDH |
DO Hold Time |
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70 |
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ns |
tPES |
PE Setup Time |
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50 |
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ns |
tDIS |
DI Setup Time |
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0.4 |
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s |
tCSH |
CS Hold Time |
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0 |
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ns |
tPEH |
PE Hold Time |
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250 |
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ns |
tPREH |
PRE Hold Time |
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50 |
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ns |
tDIH |
DI Hold Time |
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0.4 |
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s |
tPD |
Output Delay |
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2 |
s |
tSV |
CS to Status Valid |
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1 |
s |
tDF |
CS to DO in Hi-Z |
CS = VIL |
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0.4 |
s |
tWP |
Write Cycle Time |
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15 |
ms |
Capacitance TA = 25°C, f = 1 MHz (Note 5)
Symbol |
Test |
Typ |
Max |
Units |
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COUT |
Output Capacitance |
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5 |
pF |
CIN |
Input Capacitance |
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5 |
pF |
AC Test Conditions
Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note 2: Typical leakage values are in the 20nA range.
Note 3: The shortest allowable SK clock period = 1/fSK (as shown under the fSK parameter). Maximum SK clock speed (minimum SK period) is determined by the interaction of several AC parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not allowable to set 1/fSK = tSKHminimum + tSKLminimum for shorter SK cycle time operation.
Note 4: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal device registers (device reset) prior to beginning another opcode cycle. (This is shown in the opcode diagram on the following page.)
Note 5: This parameter is periodically sampled and not 100% tested.
VCC Range |
VIL/VIH |
VIL/VIH |
VOL/VOH |
IOL/IOH |
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Input Levels |
Timing Level |
Timing Level |
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2.7V ≤ VCC ≤ 5.5V |
0.3V/1.8V |
1.0V |
0.8V/1.5V |
±10 A |
(Extended Voltage Levels) |
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4.5V ≤ VCC ≤ 5.5V |
0.4V/2.4V |
1.0V/2.0V |
0.4V/2.4V |
2.1mA/-0.4mA |
(TTL Levels) |
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Output Load: 1 TTL Gate (CL = 100 pF) |
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EEPROM Serial Bit-2048 Interface) Bus (MICROWIRE NM93CS56 Read Sequential and Protect Data with
4 |
www.fairchildsemi.com |
NM93CS56 Rev. F.2
Pin Description
Chip Select (CS)
This is an active high input pin to NM93CS56 EEPROM (the device) and is generated by a master that is controlling the device. A high level on this pin selects the device and a low level deselects the device. All serial communications with the device is enabled only when this pin is held high. However this pin cannot be permanently tied high, as a rising edge on this signal is required to reset the internal state-machine to accept a new cycle and a falling edge to initiate an internal programming after a write cycle. All activity on the SK, DI and DO pins are ignored while CS is held low.
Serial Clock (SK)
This is an input pin to the device and is generated by the master that is controlling the device. This is a clock signal that synchronizes the communication between a master and the device. All input information (DI) to the device is latched on the rising edge of this clock input, while output data (DO) from the device is driven from the rising edge of this clock input. This pin is gated by CS signal.
Program Enable (PE)
This is an active high input pin to the device and is used to enable operations, that are write in nature, to the memory array and to the Protect register. When this pin is held high, operations that are “write” in nature are enabled. When this pin is held low, operations that are “write” in nature are disabled. This pin operates in conjunction with PRE pin. Refer Table1 for functional matrix of this pin for various operations.
Microwire Interface
A typical communication on the Microwire bus is made through the CS, SK, DI and DO signals. To facilitate various operations on the Memory array and on the Protect Register, a set of 10 instructions are implemented on NM93CS56. The format of each instruction is listed in Table 1.
Instruction
Each of the above 10 instructions is explained under individual instruction descriptions.
Serial Input (DI)
This is an input pin to the device and is generated by the master that is controlling the device. The master transfers Input information (Start bit, Opcode bits, Array addresses and Data) serially via this pin into the device. This Input information is latched on the rising edge of the SCK. This pin is gated by CS signal.
Serial Output (DO)
This is an output pin from the device and is used to transfer Output data via this pin to the controlling master. Output data is serially shifted out on this pin from the rising edge of the SCK. This pin is active only when the device is selected.
Protect Register Enable (PRE)
This is an active high input pin to the device and is used to distinguish operations to memory array and operations to Protect Register. When this pin is held low, operations to the memory array are enabled. When this pin is held high, operations to the Protect Register are enabled. This pin operates in conjunction with PE pin. Refer Table1 for functional matrix of this pin for various operations.
TABLE 1. Instruction set
Start Bit
This is a 1-bit field and is the first bit that is clocked into the device when a Microwire cycle starts. This bit has to be “1” for a valid cycle to begin. Any number of preceding “0” can be clocked into the device before clocking a “1”.
Opcode
This is a 2-bit field and should immediately follow the start bit. These two bits (along with PRE, PE signals and 2 MSB of address field) select a particular instruction to be executed.
Address Field
This is a 8-bit field and should immediately follow the Opcode bits. In NM93CS56, only the LSB 7 bits are used for address decoding during READ, WRITE and PRWRITE instructions. During these three instructions (READ, WRITE and PRWRITE), the MSB is “don’t care” (can be 0 or 1). During all other instructions (with the exception of PRREAD), the MSB 2 bits are used to decode instruction (along with Opcode bits, PRE and PE signals).
Data Field
This is a 16-bit field and should immediately follow the Address bits. Only the WRITE and WRALL instructions require this field. D15 (MSB) is clocked first and D0 (LSB) is clocked last (both during writes as well as reads).
Instruction |
Start Bit |
Opcode Field |
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Address Field |
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Data Field |
PRE Pin |
PE Pin |
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READ |
1 |
10 |
X |
A6 |
A5 |
A4 |
A3 |
A2 |
A1 |
A0 |
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0 |
X |
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WEN |
1 |
00 |
1 |
1 |
X |
X |
X |
X |
X |
X |
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0 |
1 |
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WRITE |
1 |
01 |
X |
A6 |
A5 |
A4 |
A3 |
A2 |
A1 |
A0 |
D15-D0 |
0 |
1 |
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WRALL |
1 |
00 |
0 |
1 |
X |
X |
X |
X |
X |
X |
D15-D0 |
0 |
1 |
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WDS |
1 |
00 |
0 |
0 |
X |
X |
X |
X |
X |
X |
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0 |
X |
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PRREAD |
1 |
10 |
X |
X |
X |
X |
X |
X |
X |
X |
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1 |
X |
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PREN |
1 |
00 |
1 |
1 |
X |
X |
X |
X |
X |
X |
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1 |
1 |
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PRCLEAR |
1 |
11 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
1 |
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1 |
1 |
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PRWRITE |
1 |
01 |
X |
A6 |
A5 |
A4 |
A3 |
A2 |
A1 |
A0 |
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1 |
1 |
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PRDS |
1 |
00 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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1 |
1 |
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EEPROM Serial Bit-2048 Interface) Bus (MICROWIRE NM93CS56 Read Sequential and Protect Data with
5 |
www.fairchildsemi.com |
NM93CS56 Rev. F.2