Fairchild Semiconductor NM24C65LEM8X, NM24C65LEN, NM24C65N, NM24C65XLZEM8, NM24C65XLZM8X Datasheet

PRELIMINARY

March 1999

NM24C65

64K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect

General Description:

The NM24C65 devices are 65,536 bits of CMOS nonvolatile electrically erasable memory. These devices offer the designer different low voltage and low power options, and they conform to all in the Extended IIC 2-wire protocol. Furthermore, they are designed to minimize device pin count and simplify PC board layout requirements.

Features:

■Extended operating voltage 2.7V – 5.5V

■400 KHz clock frequency (F) at 2.7V - 5.5V

■200μA active current typical

10μA standby current typical

1μA standby typical (L)

0.1μA standby typical (LZ)

The upper half of the memory can be disabled (Write Protection) by connecting the WP pin to VCC. This section of memory then becomes ROM.

This communication protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s).

Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability, and low power consumption.

■IIC compatible interface

–Provides bidirectional data transfer protocol

■32 byte page write mode

–Minimizes total write time per byte

■Self timed write cycle

Typical write cycle time of 6ms

■Hardware write protect for upper block

■Endurance: 1,000,000 data changes

■Data retention greater than 40 years

■Packages available: 8-pin SO, 8-pin DIP

■Low VCC programming lockout (3.8V - on Standard VCC devices only).

Block Diagram

VCC		WRITE
		LOCKOUT
WP			START CYCLE	H.V. GENERATION
				TIMING &CONTROL
SDA		START
		STOP
		LOGIC
		CONTROL
		LOGIC
		SLAVE ADDRESS		E2PROM
		REGISTER &		ARRAY
SCL		COMPARATOR	XDEC
		LOAD	INC
	A2	WORD
	A1
		ADDRESS
	A0
		COUNTER
		R/W		YDEC
			CK		DOUT
		DIN		DATA REGISTER

DS500042-1

Interface Bus Wire-2 Extended Bit-64K NM24C65

Protect Write with EEPROM Serial

© 1999 Fairchild Semiconductor Corporation

1

www.fairchildsemi.com

NM24C65 Rev. C.3

Connection Diagram

Dual-In-Line Package (N)

and 8-Pin SO Package (M8)

A0				1	8		VCC
A1				2	7		WP
					NM24C65
A2				3	6		SCL
VSS				4	5		SDA

DS500042-2

Top View

See Package Number N08E and M08A

Pin Names

A0, A1, A2	Device Address Input
VSS	Ground
SDA	Data I/O
SCL	Clock Input
WP	Write Protect
VCC	Power Supply

Ordering Information

NM 24

C

XX F LZ E

XX

Letter

Description

Package

N

8-pin DIP

M8

8-pin SO8

Temp. Range

None

0 to 70°C

V

-40 to +125°C

E

-40 to +85°C

Voltage Operating Range

Blank

4.5V to 5.5V

L

2.7V to 4.5V

LZ

2.7V to 4.5V and

<1μA Standby Current

SCL Clock Frequency

Blank

100KHz

Density

F

400KHz

65

64K with Write Protect

C

CMOS

Interface

24

IIC

NM

Fairchild Non-Volatile

Memory

Interface Bus Wire-2 Extended Bit-64K NM24C65

Protect Write with EEPROM Serial

2	www.fairchildsemi.com

NM24C65 Rev. C.3

Product Specifications

Absolute Maximum Ratings

Ambient Storage Temperature	–65°C to +150°C
All Input or Output Voltages
with Respect to Ground	6.5V to –0.3V
Lead Temperature
(Soldering, 10 seconds)	+300°C
ESD Rating	2000V min.

Operating Conditions

Ambient Operating Temperature
NM24C65	0°C to +70°C
NM24C65E	-40°C to +85°C
NM24C65V	-40°C to +125°C
Positive Power Supply
NM24C65	4.5V to 5.5V
NM24C65L	2.7V to 4.5V
NM24C65LZ	2.7V to 4.5V

Standard VCC (4.5V to 5.5V) DC Electrical Characteristics

Symbol	Parameter	Test Conditions		Limits		Units
			Min	Typ (Note 1)	Max
ICCA	Active Power Supply Current	fSCL = 100 KHz		0.2	1.0	mA
ISB	Standby Current	VIN = GND or VCC		10	50	μA
ILI	Input Leakage Current	VIN = GND to VCC		0.1	1	μA
ILO	Output Leakage Current	VOUT = GND to VCC		0.1	1	μA
VIL	Input Low Voltage		–0.3		VCC x 0.3	V
VIH	Input High Voltage		VCC x 0.7		VCC + 0.5	V
VOL	Output Low Voltage	IOL = 3 mA			0.4	V

Low VCC (2.7V to 4.5V) DC Electrical Characteristics

Symbol	Parameter	Test Conditions				Limits			Units
				Min		Typ (Note 1)		Max
ICCA	Active Power Supply Current	fSCL = 100 kHz				0.2		1.0	mA
ISB	Standby Current for L	VIN = GND or VCC				1		10	μA
(Note 1)	Standby Current for LZ	VIN = GND or VCC				0.1		1	μA
ILI	Input Leakage Current	VIN = GND to VCC				0.1		1	μA
ILO	Output Leakage Current	VOUT = GND to VCC				0.1		1	μA
VIL	Input Low Voltage			–0.3				VCC x 0.3	V
VIH	Input High Voltage			VCC x 0.7				VCC + 0.5	V
VOL	Output Low Voltage	IOL = 3 mA						0.4	V
Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2)
Symbol	Test		Conditions	Max	Units
CI/O	Input/Output Capacitance (SDA)		VI/O = 0V	8	pF
CIN	Input Capacitance (A0, A1, A2, SCL)		VIN = 0V	6	pF

Note 1: Typical values are for TA = 25°C and nominal supply voltage (5V).

Note 2: This parameter is periodically sampled and not 100% tested.

Interface Bus Wire-2 Extended Bit-64K NM24C65

Protect Write with EEPROM Serial

3	www.fairchildsemi.com

NM24C65 Rev. C.3

AC Conditions of Test

Input Pulse Levels	VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times	10 ns
Input & Output Timing Levels	VCC x 0.5
Output Load	1 TTL Gate and CL = 100 pF

Read and Write Cycle Limits (Standard and Low VCC Range - 2.7V-5.5V)

Symbol		Parameter	100 KHz		400 KHz		Units
			Min	Max	Min	Max
fSCL		SCL Clock Frequency		100		400	KHz
TI		Noise Suppression Time Constant at
		SCL, SDA Inputs (Minimum VIN		100		50	ns
		Pulse width)
tAA		SCL Low to SDA Data Out Valid	0.3	3.5	0.1	0.9	μs
tBUF		Time the Bus Must Be Free before	4.7		1.3		μs
		a New Transmission Can Start
tHD:STA		Start Condition Hold Time	4.0		0.6		μs
tLOW		Clock Low Period	4.7		1.5		μs
tHIGH		Clock High Period	4.0		0.6		μs
tSU:STA		Start Condition Setup Time	4.7		0.6		μs
		(for a Repeated Start Condition)
tHD:DAT		Data in Hold Time	0		0		ns
tSU:DAT		Data in Setup Time	250		100		ns
tR		SDA and SCL Rise Time		1		0.3	μs
tF		SDA and SCL Fall Time		300		300	ns
tSU:STO		Stop Condition Setup Time	4.7		0.6		μs
tDH		Data Out Hold Time	300		50		ns
tWR		Write Cycle Time - NM24C65		10		10	ms
(Note 3)		- NM24C65L, NM24C65LZ		15		15

Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the NM24C65 bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address

Interface Bus Wire-2 Extended Bit-64K NM24C65

Protect Write with EEPROM Serial

4	www.fairchildsemi.com

NM24C65 Rev. C.3