Fairchild Semiconductor NM24W04EM8X, NM24W04LEM8, NM24W04LEM8X, NM24W04LMT8, NM24W04N Datasheet

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Fairchild Semiconductor NM24W04EM8X, NM24W04LEM8, NM24W04LEM8X, NM24W04LMT8, NM24W04N Datasheet

PRELIMINARY

March 1999

NM24Wxx

2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect

General Description

The NM24Wxx devices are 2048/4096/8192/16,384 bits, respectively, of CMOS non-volatile electrically erasable memory. These devices conform to all specifications in the IIC 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements.

The entire ememory can be disabled (Write Protected) by connecting the WP pin to VCC. The memory then becomes unalterable unless WP is switched to VSS.

This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s). The Standard IIC protocol allows for a maximum of 16K of EEPROM memory which is supported by Fairchild's family in 2K, 4K, 8K, and 16K devices, allowing the user to configure the memory as the application requires with any combination of EEPROMs.

Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability and low power consumption.

Features

■Hardware Write Protect for entire memory

■Low Power CMOS

200μA active current typical

10μA standby current typical

1μA standby typical (L)

0.1μA standby typical (LZ)

■IIC Compatible interface

—Provides bidirectional data transfer protocol

■Sixteen byte page write mode

—Minimizes total write time per byte

■Self timed write cycle

—Typical write cycle time of 6ms

■Endurance: 1,000,000 data changes

■Data retention greater than 40 years

■Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP

■Available in three temperature ranges

-Commercial: 0° to +70°C

-Extended (E): -40° to +85C

-Automotive (V): -40° to +125°C

Block Diagram

VCC
VSS
WP						H.V. GENERATION
				START CYCLE		H.V. GENERATION
				START CYCLE		TIMING &CONTROL
						TIMING &CONTROL
SDA		START
		STOP
		LOGIC
		CONTROL
		LOGIC
		SLAVE ADDRESS			16/	E2PROM
		REGISTER &			32/	E2PROM
SCL		COMPARATOR		XDEC	64/	ARRAY
SCL		COMPARATOR		XDEC	64/
		LOAD	INC		128/
		LOAD	INC
	A2	WORD
	A1	WORD
	A1	ADDRESS
	A0	ADDRESS
	A0	COUNTER			0/1/2/3	16
		COUNTER		4	0/1/2/3


					4
		R/W				YDEC
						YDEC
		Device Address Bits				8
				CK			DOUT
		DIN				DATA REGISTER	DOUT
		DIN

DS500074-1

Full with EEPROM Serial	2K/4K/8K/16K NM24Wxx
Protect Write Array	Wire-2 Standard Bit-
	Interface Bus

www.fairchildsemi.com

NM24Wxx Rev. C.2

Connection Diagrams

Dual-In-Line Package (N), SO Package (M8), and TSSOP Package (MT8)

A0	1	8	VCC	NC	1	8	VCC	NC	1	8	VCC	NC	1	8	VCC

A1	2	7	WP	A1	2	7	WP	NC	2	7	WP	NC	2	7	WP
		NM24W02				NM24W04			NM24W08				NM24W16
A2	3	6	SCL	A2	3	6	SCL	A2	3	6	SCL	NC	3	6	SCL

VSS	4	5	SDA	VSS	4	5	SDA	VSS	4	5	SDA	VSS	4	5	SDA

		DS500074-2				DS500074-3				DS500074-4				DS500074-18

Top View

See Package Number N08E (N), M08A (M8), and MTC08 (MT8)

	Pin Names

A0,A1,A2	Device Address Inputs

VSS	Ground
SDA	Data I/O

SCL	Clock Input

WP	Write Protect

VCC	Power Supply
NC	No Connect

Ordering Information

NM 24

W XX LZ E XX

Letter

Description

Package

8-Pin DIP

8-Pin SO8

MT8

8-Pin TSSOP

Temp. Range

None

0 to 70°C

-40 to +85°C

-40°C to +125°C

Voltage Operating Range

Blank

4.5V to 5.5V

2.7V to 4.5V

2.7V to 4.5V and

<1μA Standby Current

Density

16K

Total Array Write Protect

Interface

IIC

Fairchild Non-Volatile

Memory

Full with EEPROM Serial	2K/4K/8K/16K NM24Wxx
Protect Write Array	Wire-2 Standard Bit-
	Interface Bus

2	www.fairchildsemi.com

NM24Wxx Rev. C.2

Product Specifications

Absolute Maximum Ratings

Ambient Storage Temperature	–65°C to +150°C
All Input or Output Voltages
with Respect to Ground	6.5V to –0.3V
Lead Temperature
(Soldering, 10 seconds)	+300°C
ESD Rating	2000V min.

Operating Conditions

Ambient Operating Temperature
NM24Wxx	0°C to +70°C
NM24WxxE	-40°C to +85°C
NM24WxxV	-40°C to +125°C
Positive Power Supply
NM24Wxx	4.5V to 5.5V
NM24WxxL	2.7V to 4.5V
NM24WxxLZ	2.7V to 4.5V

Standard VCC (4.5V to 5.5V) DC Electrical Characteristics

Symbol	Parameter	Test Conditions		Limits		Units
			Min	Typ	Max
				(Note 1)

ICCA	Active Power Supply Current	fSCL = 100 kHz		0.2	1.0	mA
ISB	Standby Current	VIN = GND or VCC		10	50	μA
ILI	Input Leakage Current	VIN = GND to VCC		0.1	1	μA
ILO	Output Leakage Current	VOUT = GND to VCC		0.1	1	μA
VIL	Input Low Voltage		–0.3		VCC x 0.3	V
VIH	Input High Voltage		VCC x 0.7		VCC + 0.5	V
VOL	Output Low Voltage	IOL = 3 mA			0.4	V

Low VCC (2.7V to 5.5V) DC Electrical Characteristics

Symbol	Parameter	Test Conditions				Limits			Units
				Min			Typ	Max
						(Note 1)

ICCA	Active Power Supply Current	fSCL = 100 kHz				0.2		1.0	mA
ISB	Standby Current for L	VIN = GND or VCC				1		10	μA
	Standby Current for LZ	VIN = GND or VCC				0.1		1	μA

ILI	Input Leakage Current	VIN = GND to VCC				0.1		1	μA
ILO	Output Leakage Current	VOUT = GND to VCC				0.1		1	μA
VIL	Input Low Voltage			–0.3				VCC x 0.3	V
VIH	Input High Voltage			VCC x 0.7				VCC + 0.5	V
VOL	Output Low Voltage	IOL = 3 mA						0.4	V
Capacitance TA = +25°C, f = 100/400 KHz, VCC = 5V (Note 2)

Symbol	Test		Conditions	Max	Units

CI/O	Input/Output Capacitance (SDA)		VI/O = 0V	8	pF
CIN	Input Capacitance (A0, A1, A2, SCL)		VIN = 0V	6	pF

Note 1: Typical values are TA = 25°C and nominal supply voltage (5V).

Note 2: This parameter is periodically sampled and not 100% tested.

Full with EEPROM Serial	2K/4K/8K/16K NM24Wxx
Protect Write Array	Wire-2 Standard Bit-
	Interface Bus

3	www.fairchildsemi.com

NM24Wxx Rev. C.2

AC Conditions of Test

Input Pulse Levels	VCC x 0.1 to VCC x 0.9

Input Rise and Fall Times	10 ns

Input & Output Timing Levels	VCC x 0.5

Output Load	1 TTL Gate and CL = 100 pF

Read and Write Cycle Limits (Standard and Low VCC Range 2.7V - 4.5V)

Symbol	Parameter	100 KHz		400 KHz		Units
		Min	Max	Min	Max

fSCL	SCL Clock Frequency		100		400	KHz
TI	Noise Suppression Time Constant at
	SCL, SDA Inputs (Minimum VIN		100		50	ns
	Pulse width)

tAA	SCL Low to SDA Data Out Valid	0.3	3.5	0.1	0.9	μs
tBUF	Time the Bus Must Be Free before	4.7		1.3		μs
	a New Transmission Can Start

tHD:STA	Start Condition Hold Time	4.0		0.6		μs
tLOW	Clock Low Period	4.7		1.5		μs
tHIGH	Clock High Period	4.0		0.6		μs
tSU:STA	Start Condition Setup Time	4.7		0.6		μs
	(for a Repeated Start Condition)

tHD:DAT	Data in Hold Time	0		0		ns
tSU:DAT	Data in Setup Time	250		100		ns
tR	SDA and SCL Rise Time		1		0.3	μs
tF	SDA and SCL Fall Time		300		300	ns

tSU:STO	Stop Condition Setup Time	4.7		0.6		μs
tDH	Data Out Hold Time	300		50		ns
tWR	Write Cycle Time - NM24Wxx		10		10	ms
(Note 3)	- NM24WxxL, NM24WxxLZ		15		15

Note 3: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the NM24Wxx bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.

Full with EEPROM Serial	2K/4K/8K/16K NM24Wxx
Protect Write Array	Wire-2 Standard Bit-
	Interface Bus

4	www.fairchildsemi.com

NM24Wxx Rev. C.2

Bus Timing

t	F		tR
		tHIGH
	tLOW		tLOW
SCL
tSU:STA		tHD:DAT	tSU:STO
tSU:STA		tHD:DAT	tSU:DAT
tHD:STA
SDA
IN			tBUF
			tBUF
	tAA		tDH
SDA
OUT

DS500074-5

Background Information (IIC Bus)

As mentioned, the IIC bus allows synchronous bidirectional communication between Transmitter/Receiver using the SCL (clock) and SDA (Data I/O) lines. All communication must be started with a valid START condition, concluded with a STOP condition and acknowledged by the Receiver with an ACKNOWLEDGE condition.

In addition, since the IIC bus is designed to support other devices such as RAM, EPROMs, etc., a devce type identifier string must follow the START condition. For EEPROMs, this 4-bit string is 1010 and is the first 4 bits in the slave address.

As shown below, the EEPROMs on the IIC bus may be configured in any manner required, and for the Standard IIC protocol, the total memory addressed can not exceed 16K (16,384 bits). EEPROM memory address programming is controlled by 2 methods:

•Hardware configuring the A0, A1, and A2 pins (Device Address pins) with pull-up or pull-down to resistors. All unused pins must be grounded (tied to VSS).

•Software addressing the required PAGE BLOCK within the device memory array (as sent in the Slave Address string).

Addressing an EEPROM memory location involves sending a command string with the following information:

[DEVICE TYPE]—[DEVICE ADDRESS]—[PAGE BLOCK ADDRESS]—[BYTE ADDRESS]

	DEFINITIONS

WORD	8 bits of data

PAGE	16 sequential addresses (one byte
	each) that may be programmed
	during a 'Page Write' programming
	cycle

PAGE BLOCK	2,048 (2K) bits organized into 16
	pages of addressable memory. (8
	bits) x (16 bytes) x (16 pages) = 2,048
	bits

MASTER	Any IIC device CONTROLLING the
	transfer of data (such as a micropro-
	cessor)

SLAVE	Device being controlled (EEPROMs
	are always considered Slaves)

TRANSMITTER	Device currently SENDING data on
	the bus (may be either a Master or
	Slave).

RECEIVER	Device currently receiving data on the
	bus (Master or Slave)

Example of 16K of Memory on 2-Wire Bus

VCC VCC

SDA

SCL

VCC

NM24W02

NM24W04

NM24W08

A0 A1 A2 VSS

DS500074-6

To VCC or VSS

Note: The SDA pull-up resistor is required due to the open-drain/open collector output of IIC bus devices.

The SCL pull-up resistor is recommended because of the normal SCL line inactive 'high' state.

It is recommended that the total line capacitance be less than 400pF.

Specific timing and addressing considerations are described in greater detail in the following sections.

5	www.fairchildsemi.com

NM24Wxx Rev. C.2

Full with EEPROM Serial	2K/4K/8K/16K NM24Wxx
Protect Write Array	Wire-2 Standard Bit-
	Interface Bus

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