Fairchild Semiconductor NM27C128N150, NM27C128NE120, NM27C128NE200, NM27C128Q150, NM27C128Q200 Datasheet

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July 1998

NM27C128

131,072-Bit (16K x 8) High Performance CMOS EPROM

General Description

The NM27C128 is a high performance 128K UV Erasable Electrically Programmable Read Only Memory. It is manufactured with Fairchild’s latest CMOS split gate EPROM technology which enables it to operate at speeds as fast as 90 ns access time over the full operating range.

The NM27C128 provides microprocessor-based systems extensive storage capacity for large portions of operating system and application software. Its 90 ns access time provides high speed operation with high-performance CPUs. The NM27C128 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed from EPROM storage, greatly enhancing system utility.

The NM27C128 is configured in the standard EPROM pinout which provides an easy upgrade path for systems which are currently using standard EPROMs.

The NM27C128 is one member of a high density EPROM Family which range in densities up to 4 Mb.

Features

High performance CMOS

90 ns access time

Fast turn-off for microprocessor compatibility

JEDEC standard pin configuration

28-pin PDIP package

32-pin chip carrier

28-pin CERDIP package

Drop-in replacement for 27C128 or 27128

40% faster programming time with Fairchild’s turbo algorithm

Block Diagram

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

 

 

 

 

 

 

Data Outputs O0 - O7

 

 

 

 

 

 

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

VPP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OE

 

 

 

Output Enable,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PGM

 

 

and Chip

 

 

 

 

 

 

Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Enable Logic

 

 

 

 

 

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Buffers

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

. .

Y Decoder

 

Y Gating

 

A0 - A14

Address

Inputs

X Decoder

.

131,072-Bit

. .

Cell Matrix

 

 

. . . .

 

DS011329-1

EPROM CMOS Performance High 8) x (16K Bit-131,072 NM27C128

© 1998 Fairchild Semiconductor Corporation

1

www.fairchildsemi.com

Connection Diagrams

27C080 27C040

27C020

27C010 27C512 27C256

 

 

 

DlP

 

 

 

 

 

27C256

 

27C512 27C010

27C020

27C040

 

27C080

A19

VPP

VPP

VPP

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC

 

 

VCC

 

VCC

 

 

VCC

 

 

 

 

NM27C128

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A16

A16

A16

A16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PGM

PGM

A18

 

 

A18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VPP

 

 

28

 

 

 

 

 

VCC

 

VCC

 

 

A15

A15

A15

A15

A15

VPP

 

1

 

VCC

 

XX

 

XX

A17

 

 

A17

 

 

A12

A12

A12

A12

A12

A12

A12

 

2

27

 

 

 

 

 

A14

 

A14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PGM

 

A14

 

A14

A14

 

 

A14

 

 

 

 

A7

A7

A7

A7

A7

A7

A7

 

3

26

 

A13

A13

 

A13 A13

 

A13

A13

 

 

A13

 

 

A6

A6

A6

A6

A6

A6

A6

 

4

25

 

A8

 

A8

 

 

A8

A8

 

A8

 

 

A8

 

 

 

A8

 

 

 

24

 

A5

A5

A5

A5

A5

A5

A5

 

5

 

A9

 

A9

 

 

A9

A9

 

A9

 

 

A9

 

 

 

A9

 

 

 

 

A4

A4

A4

A4

A4

A4

A4

 

6

23

 

A11

A11

 

A11 A11

 

A11

A11

 

 

A11

 

 

 

 

 

 

 

 

 

 

 

22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A3

A3

A3

A3

A3

A3

A3

 

7

 

OE

 

 

OE

 

OE/VPP

 

 

 

 

 

 

 

 

 

 

 

 

 

OE/VPP

 

 

OE

OE

OE

A2

A2

A2

A2

A2

A2

A2

 

8

21

 

A10

A10

 

A10 A10

 

A10

A10

 

 

A10

 

 

A1

A1

A1

A1

A1

A1

A1

 

9

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

 

CE

 

CE/PGM

 

 

 

 

 

 

 

CE/PGM CE/PGM

 

 

CE

CE

A0

A0

A0

A0

A0

A0

A0

 

10

19

 

O7

 

O7

 

O7

O7

 

O7

O7

 

 

O7

 

 

 

18

 

O0

O0

O0

O0

O0

O0

O0

 

11

 

O6

 

O6

 

O6

O6

 

O6

O6

 

 

O6

 

 

O1

O1

O1

O1

O1

O1

O1

 

12

17

 

O5

 

O5

 

O5

O5

 

O5

O5

 

 

O5

 

 

O2

O2

O2

O2

O2

O2

O2

 

13

16

 

O4

 

O4

 

O4

O4

 

O4

O4

 

 

O4

 

 

GND

GND

GND

GND

GND

GND

GND

 

14

15

 

O3

 

O3

 

O3

O3

 

O3

O3

 

 

O3

 

 

 

 

 

DS011329-8

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C128 pins.

Commercial Temp. Range (0°C to +70°C) VCC = 5V ±10%

Parameter/Order Number

Access Time (ns)

 

 

NM27C128 Q, N, V 90

90

 

 

NM27C128 Q, N, V 120

120

 

 

NM27C128 Q, N, V 150

150

 

 

NM27C128 Q, N, V 200

200

 

 

Pin Names

Symbol

Description

 

 

 

 

 

 

 

 

A0–A13

Addresses

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Chip Enable

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Enable

OE

 

 

 

 

 

 

 

 

O0–O7

Outputs

 

 

 

 

 

 

 

 

 

Program

 

PGM

 

 

 

 

 

 

 

 

 

 

NC

No Connect

 

 

 

 

 

 

 

 

Extended Temp. Range

(-40°C to +85°C) VCC = 5V ±10%

Parameter/Order Number

Access Time (ns)

 

 

NM27C128 QE, NE, VE 120

120

 

 

NM27C128 QE, NE, VE 150

150

 

 

NM27C128 QE, NE, VE 200

200

 

 

Note: Surface mount PLCC package available for commercial and extended temperature ranges only.

Package Types: NM27C128 Q, N, V XXX

Q = Quartz-Windowed Ceramic DIP

N = Plastic OTP DIP

V = Surface-Mount PLCC

All packages conform to the JEDEC standard.

All versions are guaranteed to function for slower speeds.

 

 

 

 

PLCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Top

 

PGM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A7

A12

VPP

NC

VCC

 

A13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

3

2

1

32 31 30

 

 

 

 

 

 

A6

 

5

 

 

 

 

 

 

 

 

 

 

 

 

29

 

 

A8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A5

 

6

 

 

 

 

 

 

 

 

 

 

 

 

28

 

 

A9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A4

 

7

 

 

 

 

 

 

 

 

 

 

 

 

27

 

 

A11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A3

 

8

 

 

 

 

 

 

 

 

 

 

 

 

26

 

 

NC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A2

 

9

 

 

 

 

 

 

 

 

 

 

 

 

25

 

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A1

 

10

 

 

 

 

 

 

 

 

 

 

 

 

24

 

 

A10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A0

 

11

 

 

 

 

 

 

 

 

 

 

 

 

23

 

 

CE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NC

 

12

 

 

 

 

 

 

 

 

 

 

 

 

22

 

 

O7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O0

 

13

 

 

 

 

 

 

 

 

 

 

 

 

21

 

 

O6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

15

16

17

18

19

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

O1

O2

GND

NC

O3

 

O4

O5

 

 

 

 

 

DS011329-3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EPROM CMOS Performance High 8) x (16K Bit-131,072 NM27C128

2

www.fairchildsemi.com

Absolute Maximum Ratings (Note 1)

Storage Temperature

-65°C to +150°C

All Input Voltages except A9 with

 

Respect to Ground

-0.6V to +7V

VPP and A9 with Respect

 

to Ground

-0.7V to +14V

VCC Supply Voltage with

 

Respect to Ground

-0.6V to +7V

ESD Protection

> 2000V

Read Operation

All Output Voltages with

 

 

 

Respect to Ground

VCC + 1.0V to GND -0.6V

Operating Range

 

 

 

 

 

 

 

Range

Temperature

VCC

Comm’l

0°C to +70°C

 

+5V ±10%

 

 

 

 

 

Industrial

-40°C to +85°C

+5V ±10%

 

 

 

 

 

DC Electrical Characteristics Over Operating Range with VPP = VCC

Symbol

Parameter

 

 

 

 

Test Conditions

Min

Max

Units

 

 

 

 

 

 

 

 

 

 

 

 

VIL

Input Low Level

 

 

 

 

 

 

-0.5

0.8

V

 

VIH

Input High Level

 

 

 

 

 

 

2.0

VCC +1

V

 

VOL

Output Low Voltage

 

IOL = 2.1 mA

 

0.4

V

 

VOH

Output High Voltage

IOH = -2.5 mA

3.5

 

V

ISB1

VCC Standby Current

 

CE

= VCC ±0.3V

 

100

μA

 

 

(CMOS)

 

VIL = GND ± 0.3V, VIH = VCC ±0.3V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I

V Standby Current (T2L)

CE = V

 

1

mA

SB2

CC

 

 

 

 

IH

 

 

 

 

I

V Active Current, T2L Inputs

CE =

OE

= V , f = 5 MHz

 

35

mA

CC1

CC

 

 

 

 

 

IL

 

 

 

 

 

 

I/O = 0 mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IPP

VPP Supply Current

VPP = VCC

 

10

μA

 

VPP

VPP Read Voltage

 

 

 

 

 

 

GND

VCC

V

ILI

Input Load Current

VIN = 5.5V or GND

-1

1

μA

 

ILO

Output Leakage Current

VOUT = 5.5V or GND

-10

10

μA

AC Electrical Characteristics Over Operating Range with VPP = VCC

Symbol

 

 

 

 

 

 

 

Parameter

90

120

150

200

Units

 

 

 

 

 

 

 

 

 

Min

Max

Min

Max

Min

Max

Min

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tACC

 

Address to Output Delay

 

90

 

120

 

150

 

200

ns

tCE

 

 

 

 

 

to Output Delay

 

90

 

120

 

150

 

200

ns

CE

 

 

 

 

tOE

 

 

 

to Output Delay

 

50

 

50

 

50

 

50

ns

OE

 

 

 

 

tCF

 

CE High to Output Float

 

30

 

30

 

45

 

55

ns

(Note 2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDF

 

 

 

 

 

35

 

35

 

45

 

55

ns

 

 

OE

High to Output Float

 

 

 

 

(Note 2)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tOH

 

Output Hold from Addresses,

 

 

 

 

 

 

 

 

 

(Note 2)

 

 

or

 

 

0

 

0

 

0

 

0

 

ns

 

CE

OE,

 

 

 

 

 

 

Whichever Occurred First

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EPROM CMOS Performance High 8) x (16K Bit-131,072 NM27C128

3

www.fairchildsemi.com

Fairchild Semiconductor NM27C128N150, NM27C128NE120, NM27C128NE200, NM27C128Q150, NM27C128Q200 Datasheet

Capacitance TA = +25°C, f = 1 MHz (Note 2)

Symbol

Parameter

Conditions

Typ

Max

Units

 

 

 

 

 

 

CIN

Input Capacitance

VIN = 0V

6

12

pF

COUT

Output Capacitance

VOUT = 0V

9

12

pF

AC Test Conditions

Output Load

1 TTL Gate and CL = 100 pF (Note 8)

 

Input Rise and Fall Times

5 ns

 

Input Pulse Levels

 

0.45 to 2.4V

 

Timing Measurement Reference Level (Note 10)

 

Inputs

 

0.8V and 2.0V

 

Outputs

 

0.8V and 2.0V

 

AC Waveforms (Notes 6, 7, 9)

 

ADDRESSES

2V

Addresses Valid

 

 

0.8V

 

 

CE

2V

 

tCF

 

0.8V

 

 

 

tCE

(Notes 4, 5)

 

2V

 

OE

 

 

0.8V

tOE

tDF

 

 

 

 

(Note 3)

(Notes 4, 5)

OUTPUT

2V

Hi-Z

Hi-Z

0.8V

 

Valid Output

 

 

 

 

 

tACC

tOH

 

 

(Note 3)

 

 

DS011329-4

 

 

 

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Note 2: This parameter is only sampled and is not 100% tested.

Note 3: OE may be delayed up to tACC - tOE after the falling edge of CE without impacting tACC.

Note 4: The tDF and tCF compare level is determined as follows:

High to TRI-STATE®, the measured VOH1 (DC) - 0.10V;

Low to TRI-STATE, the measured VOL1 (DC) + 0.10V.

Note 5: TRI-STATE may be attained using OE or CE .

Note 6: The power switching characteristics of EPROMs require careful device decoupling. It is recommended that at least a 0.1 μF ceramic capacitor be used on every device between V CC and GND.

Note 7: The outputs must be restricted to VCC + 1.0V to avoid latch-up and device damage.

Note 8: TTL Gate: IOL = 1.6 mA, IOH = -400 μA.

CL = 100 pF includes fixture capacitance.

Note 9: VPP may be connected to VCC except during programming.

Note 10: Inputs and outputs can undershoot to -2.0V for 20 ns Max.

EPROM CMOS Performance High 8) x (16K Bit-131,072 NM27C128

4

www.fairchildsemi.com

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