Fairchild Semiconductor NM27C210VE150, NM27C210V150, NM27C210V120, NM27C210Q120, NM27C210VE120 Datasheet

July 1998

NM27C210

1,048,576-Bit (64K x 16) High Performance CMOS EPROM

General Description

The NM27C210 is a high performance Electrically Programmable UV erasable ROM (EPROM). It contains 1,048,576 bits configured as 64K x 16 bit. It is offered in both erasable versions for prototyping and early production applications as well as nonerasable, plastic packaged versions that are ideal for high volume and automated assembly applications.

The NM27C210 operates from a single 5 volt ±10% supply in the read mode.

The NM27C210 is offered in both DIP and surface mount packages. The DIP package is a 40-pin dual-in-line ceramic with a quartz window to allow erasing. The surface mount package is a 44-pin PLCC that is offered in OTP.

This EPROM is manufactured using Fairchild’s proprietary AMG™ EPROM technology for an excellent combination of speed and economy while providing excellent reliability.

Features

■High performance CMOS

—90 ns access time

■Fast turn-off for microprocessor compatibility

■Simplified upgrade path

—VPP and PGM are “Don’t Care” during normal read operation

■Compatible with 27210 and 27C210 EPROMs

■Manufacturer’s identification code

■Fast programming

■JEDEC standard pin configuration

—40-pin CDIP package

—40-pin PDIP package

—44-pin PLCC package

Block Diagram

Vcc

Data Outputs O0 - O15

GND

Vpp
OE	Output Enable
PGM	Chip Enable, and	Output
CE	Program Logic	Buffers
	Y
	Decoder
A0 - A15		4,194,304-Bit
		Cell Matrix
Address	X
Inputs
	Decoder

DS011093-1

AMG™ is a trademark of WSI, Inc.

EPROM CMOS Performance High 16) x (64K Bit-1,048,576 NM27C210

© 1998 Fairchild Semiconductor Corporation

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Connection Diagrams

DIP PIN CONFIGURATIONS

27C280

27C240

27C220

DIP

NM27C210

A18

XXVPP

XXVPP

XX/VPP

VCC

1

40

CE

2

39

CE/PGM

CE/PGM

CE

XX/PGM

O15

O15

O15

O15

3

38

NC

O14

O14

O14

O14

4

37

A15

O13

O13

O13

O13

5

36

A14

O12

O12

O12

O12

6

35

A13

7

O11

O11

O11

O11

34

A12

O10

O10

O10

O10

8

33

A11

O9

O9

O9

O9

9

32

A10

O8

O8

O8

O8

10

31

A9

GND

GND

GND

GND

11

30

GND

O7

O7

O7

O7

12

29

A8

O6

O6

O6

O6

13

28

A7

O5

O5

O5

O5

14

27

A6

O4

O4

O4

O4

15

26

A5

O3

O3

O3

O3

16

25

A4

17

O2

O2

O2

O2

24

A3

O1

O1

O1

O1

18

23

A2

O0

O0

O0

O0

19

22

A1

20

OE/VPP

OE

OE

OE

21

A0

Note: Compatible EPROM pin configurations are shown in the blocks adjacent to the NM27C210 pins.

27C220			27C240	27C280
VCC			VCC	VCC
	PGM		A17	A17
A16			A16	A16
A15			A15	A15
A14			A14	A14
A13			A13	A13
A12			A12	A12
A11			A11	A11
A10			A10	A10
	A9		A9	A9
GND			GND	GND
	A8		A8	A8
	A7		A7	A7
	A6		A6	A6
	A5		A5	A5
	A4		A4	A4
	A3		A3	A3
	A2		A2	A2
	A1		A1	A1
	A0		A0	A0

DS011093-7

Commercial Temperature Range (0°C to +70°C) VCC = 5V ±10%

Parameter/Order Number	Access Time (ns)
NM27C210 Q, V, N 90	90
NM27C210 Q, V, N 120	120
NM27C210 Q, V, N 150	150

Industrial Temperature Range (-40°C to +85°C) VCC = 5V ±10%

Parameter/Order Number	Access Time (ns)
NM27C210 QE, VE, NE 120	120
NM27C210 QE, VE, NE 150	150

Package Types: NM27C210 Q, V, N XXX

Q = Quartz-Windowed Ceramic DIP package

N = Plastic DIP package

V = PLCC package

•All packages conform to JEDEC standard.

•All versions are guaranteed to function in slower applications.

Pin Names

A0–A15				Addresses
	CE			Chip Enable
				Output Enable
		OE
O0–O15				Outputs
PGM				Program
		XX		Don’t Care (During Read)
	NC			No Connect

PLCC Pin Configuration

		O	O O		CE XX/V NC V				XX/PGM NC A A
							PP
	7	13	14 15					CC	15 14	39
O12		6	5	4	3	2		4443424140
								1		A13
O11		8							38	A12
O10		9							37	A11
O9		10							36	A10
O8		11							35	A9
GND		12							34	GND
NC		13							33	NC
O7		14							32	A8
O6		15							31	A7
O5		16							30	A6
O4	17	1819202122232425262728								A5
										29
		3	2 1 0				OE	1 2 2 3 4
		O O O O						NC A A A A A		DS011093-3

Top View

EPROM CMOS Performance High 16) x (64K Bit-1,048,576 NM27C210

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Absolute Maximum Ratings (Note 1)

Storage Temperature	-65°C to +150°C
All Input Voltages except A9 with
Respect to Ground (Note 10)	-0.6V to +7V
VPP and A9 with Respect to Ground	-0.6V to +14V
VCC Supply Voltage with
Respect to Ground	-0.6V to +7V
ESD Protection	>2000V

All Output Voltages with
Respect to Ground (Note 10)		VCC + 1.0V to GND - 0.6V
Operating Range
Range	Temperature	VCC	Tolerance
Commercial	0°C to +70°C	+5V	±10%
Industrial	-40°C to +85°C	+5V	±10%

DC Read Characteristics Over Operating Range with VPP = VCC

Symbol

Parameter

Test Conditions

Min

Max

Units

VIL

Input Low Level

-0.5

0.8

V

VIH

Input High Level

2.0

VCC +1

V

VOL

Output Low Voltage

IOL = 2.1 mA

0.4

V

VOH

Output High Voltage

IOH = -2.5 mA

3.5

V

ISB1

VCC Standby Current

CE

= VCC ± 0.3V

100

μA

(CMOS)

ISB2

VCC Standby Current

CE = VIH

1

mA

ICC

VCC Active Current

CE

= OE = VIL

f = 5 MHz

40

mA

I/O = 0 mA

IPP

VPP Supply Current

VPP = VCC

10

μA

ILI

Input Load Current

VIN = 5.5 or GND

-1

1

μA

ILO

Output Leakage Current

VOUT = 5.5V or GND

-10

10

μA

AC Read Characteristics Over Operating Range with VPP = VCC

Symbol

Parameter

90

120

150

Units

Min

Max

Min

Max

Min

Max

tACC

Address to Output Delay

90

120

150

tCE

CE to Output Delay

90

120

150

tOE

OE to Output Delay

50

50

50

tDF

Output Disable to Output Float

30

35

45

ns

(Note 2)

tOH

Output

Hold from Addresses,

(Note 2)

CE or OE , Whichever

0

0

0

Occurred First

Capacitance (Note 2) TA = +25°C, f = 1 MHz

Symbol

Parameter

Conditions

Typ

Max

Units

CIN

Input Capacitance

VIN = 0V

12

20

pF

COUT

Output Capacitance

VOUT = 0V

13

20

pF

EPROM CMOS Performance High 16) x (64K Bit-1,048,576 NM27C210

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