Fairchild Semiconductor NM25C640EM8X, NM25C640EM8, NM25C640LVM8, NM25C640UM8, NM25C640ULZVN Datasheet

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NM25C640 Rev. D.2

NM25C640 64K-Bit Serial CMOS EEPROM

(Serial Periphrial Interface (SPI) Synchronous Bus)

PRELIMINARY

March 1999

NM25C640

64K-Bit Serial CMOS EEPROM

(Serial Peripheral Interface (SPI) Synchronous Bus)

General Description

The NM25C640 is a 65,536-bit CMOS EEPROM with an SPI

compatible serial interface. The NM25C640 is designed for data

storage in applications requiring both non-volatile memory and in-

system data updates. This EEPROM is well suited for applications

using the 68HC11 series of microcontrollers that support the SPI

interface for high speed communication with peripheral devices

via a serial bus to reduce pin count. The NM25C640 is imple-

mented in Fairchild Semiconductor’s floating gate CMOS process

that provides superior endurance and data retention.

The serial data transmission of this device requires four signal

lines to control the device operation: Chip Select (CS), Clock

(SCK), Data In (SI), and Serial Data Out (SO). All programming

cycles are completely self-timed and do not require an erase

before WRITE.

BLOCK WRITE protection is provided by programming the STA-

TUS REGISTER with one of four levels of write protection.

Additionally, separate WRITE enable and WRITE disable instruc-

tions are provided for data protection.

Hardware data protection is provided by the WP pin to protect

against inadvertent programming. The HOLD pin allows the serial

communication to be suspended without resetting the serial

sequence.

Block Diagram

Features

■ 2.75 MHz clock rate @ 4.5V to 5.5V

2.1 MHz @ 2.7V to 4.5V

■ 65,536 bits organized as 8,192 x 8

■ Multiple chips on the same 3-wire bus with separate chip

select lines

■ Self-timed programming cycle

■ Simultaneous programming of 1 to 32 bytes at a time

■ Status register can be polled during programming to monitor

READY/BUSY

■ Write Protect (WP) pin and write disable instruction for both

hardware and software write protection

■ Block write protect feature to protect against accidental

writes

■ Endurance: 1,000,000 data changes

■ Data retention greater than 40 years

■ Packages available: 8-pin DIP or 8-Pin SO

DS500041-1

Instruction

Decoder

Control Logic

and Clock

Generators

High Voltage

Generator

and

Program

Timer

Instruction

Program

Enable

Data In/Out Register

8 Bits

Data Out

Buffer

Non-Volatile

Status Register

Decoder

1 of 8,192

Address

Counter/

EEPROM Array

65,536 Bits

(8,192 x 8)

Read/Write Amps

HOLD

SCK

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NM25C640 Rev. D.2

NM25C640 64K-Bit Serial CMOS EEPROM

(Serial Periphrial Interface (SPI) Synchronous Bus)

Connection Diagram

Dual-In-Line Package (N)

and SO Package (M8)

Top View

Pin Names

CS Chip Select Input

SO Serial Data Output

WP Write Protect

Ground

SI Serial Data Input

SCK Serial Clock Input

HOLD Suspends Serial Data

Power Supply

Ordering Information

NM 25 C XX LZ E XX Letter Description

Package N 8-Pin DIP

M8 8-Pin SO

Temp. Range None 0 to 70°C

V -40 to +125°C

E -40 to +85°C

Voltage Operating Range Blank 4.5V to 5.5V

L 2.7V to 4.5V

LZ 2.7V to 4.5V and

<1µA Standby Current

Density/Mode 640 64K, mode 0

C CMOS

Interface 25 SPI

NM Fairchild Nonvolatile

Memory

HOLD

SCK

NM25C640

DS500041-2

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NM25C640 Rev. D.2

NM25C640 64K-Bit Serial CMOS EEPROM

(Serial Periphrial Interface (SPI) Synchronous Bus)

Standard Voltage 4.5 ≤ V

≤ 5.5V Specifications

Absolute Maximum Ratings (Note 1)

Ambient Storage Temperature -65°C to +150°C

All Input or Output Voltage with

Respect to Ground +6.5V to -0.3V

Lead Temp. (Soldering, 10 sec.) +300°C

ESD Rating 2000V

Operating Conditions

Ambient Operating Temperature

NM25C640 0°C to +70°C

NM25C640E -40°C to +85°C

NM25C640V -40°C to +125°C

Power Supply (V

) 4.5V to 5.5V

DC and AC Electrical Characteristics 4.5V ≤ V

≤ 5.5V (unless otherwise specified)

Symbol Parameter Conditions Min Max Units

Operating Current CS = V

3mA

CCSB

Standby Current CS = V

50 µA

Input Leakage V

= 0 to V

-1 +1 µA

Output Leakage V

OUT

= GND to V

-1 +1 µA

CMOS Input Low Voltage -0.3 V

* 0.3 V

CMOS Input High Voltage V

* 0.7 V

+ 0.3 V

Output Low Voltage I

= 2.1 mA 0.4 V

Output High Voltage I

= -0.8 mA V

- 0.8 V

SCK Frequency 2.75 MHz

Input Rise Time 2.0 µs

Input Fall Time 2.0 µs

CLH

Clock High Time (Note 2) 155 ns

CLL

Clock Low Time (Note 2) 155 ns

CSH

Min CS High Time (Note 3) 240 ns

CSS

CS Setup Time 176 ns

DIS

Data Setup Time 50 ns

HDS

HOLD Setup Time 90 ns

CSN

CS Hold Time 155 ns

DIN

Data Hold Time 50 ns

HDN

HOLD Hold Time 90 ns

Output Delay C

= 200 pF 135 ns

Output Hold Time 0 ns

HOLD to Output Low Z 240 ns

Output Disable Time C

= 200 pF 290 ns

HOLD to Output High Z 240 ns

Write Cycle Time 1–32 Bytes 10 ms

Capacitance T

= 25°C, f = 2.1/1 MHz (Note 4)

Symbol Test Typ Max Units

OUT

Output Capacitance 3 8 pF

Input Capacitance 2 6 pF

Note 1: Stress above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the

device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Note 2: The f

frequency specification specifies a minimum clock period of 1/f

. Therefore, for every f

clock cycle, t

CLH

+ t

CLL

must be equal to or greater than 1/f

. For

example, if the 2.1MHz period = 476ns and t

CLH

= 190ns, t

CLL

must be 286ns.

Note 3: CS must be brought high for a minimum of t

CSH

between consecutive instruction cycles.

Note 4: This parameter is periodically sampled and not 100% tested.

AC Test Conditions

Output Load C

= 200 pF

Input Pulse Levels 0.1 * V

– 0.9 * V

Timing Measurement Reference Level 0.3 * V

- 0.7 • V

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