Name: Apple X304
Brand: Apple
SKU: 8574542
Rating: 5 (1 reviews)

TABLE_TABLEOFCONTENTS_ITEM

Apple Inc.

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

II NOT TO REPRODUCE OR COPY IT

3

B

7

BRANCH

DRAWING NUMBER

SIZE

D

SHEET

R

DATE

D

A

C

PAGE

A

C

3456

D

B

87 6 5 4 21

12

APPD

CK

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

DRAWING TITLE

DESCRIPTION OF REVISION

REV ECN

REVISION

PROPRIETARY PROPERTY OF APPLE INC.

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

X304 MLB SCHEMATIC - DVT

Schematic / PCB #’s

051-1573

8.0.0

1 OF 82

1 OF 120

Fri Dec 19 12:14:48 2014

ENGINEERING RELEASED

dvt1

2014-12-19

8

0003549590

SCHEM,MLB,X304

54

42

JACK_J52

12/15/2013

Power Sensors: High Side

53

41

GKOO_J52

12/06/2013

SMBus Connections

52

40

JACK_J52

11/07/2013

SMC Project Support

51

39

JACK_J52

10/24/2013

SMC Shared Support

50

38

JACK_J52

11/07/2013

SMC

49

37

JACK_J52

01/31/2014

Keyboard & Trackpad (2 of 2)

48

36

JACK_J52

01/28/2014

Keyboard & Trackpad (1 of 2)

46

35

J41

10/23/2012

External A USB3 Connector

40

34

J41

12/21/2012

Camera (2 of 2)

39

33

J45

01/24/2013

Camera (1 of 2)

37

32

YHARTANTO_J44

12/18/2012

SSD Connector

35

31

J41

11/01/2012

Wireless Support

34

30

J14

10/23/2012

DDC Crossbar

33

29

T29_RR

10/26/2012

Thunderbolt Connector B

32

28

T29_RR

10/26/2012

Thunderbolt Connector A

30

27

T29_RR

11/19/2012

Thunderbolt Mobile Support

29

26

T29_RR

12/17/2012

Thunderbolt Host (2 of 2)

28

25

T29_RR

01/19/2013

Thunderbolt Host (1 of 2)

27

24

J41_MLB

02/06/2013

LPDDR3 DRAM Termination

26

23

J41_MLB

02/06/2013

LPDDR3 DRAM Channel B (32-63)

25

22

J41_MLB

02/06/2013

LPDDR3 DRAM Channel B (00-31)

24

21

J41_MLB

02/06/2013

LPDDR3 DRAM Channel A (32-63)

23

20

J41_MLB

02/06/2013

LPDDR3 DRAM Channel A (00-31)

22

19

YHARTANTO_J44

01/02/2013

LPDDR3 VREF Margining

20

18

J41

10/23/2012

Project Chipset Support

19

17

J41

01/30/2013

Chipset Support

18

16

WFERRY_J43

12/21/2012

CPU/PCH Merged XDP

16

15

J41

01/19/2013

PCH GPIO/MISC/LPIO

15

14

J41

10/23/2012

PCH PCIe,USB,LPC,SPI,SMBus

14

13

J41

02/21/2013

PCH PM/PCI/GFX

13

12

J41

12/17/2012

PCH Audio/JTAG/SATA/CLK

12

11

J41

10/23/2012

PCH Decoupling

10

J41

10/23/2012

CPU Decoupling

9

J41

10/23/2012

CPU & PCH Grounds

8

J41

10/23/2012

CPU & PCH Power

7

J41

10/23/2012

CPU LPDDR3 Interfaces

6

J41

10/23/2012

CPU Misc,JTAG,CFG,RSVD

5

J41

10/23/2012

CPU GFX,NCTF,RSVD

4

LDUNN_J44

01/13/2013

PD Parts

3

J14

09/04/2012

BOM Configuration

2

SHART_J44

11/27/2012

BOM Configuration

82

120

J14

10/23/2012

Reference

81

119

YHARTANTO_J44

01/13/2013

PCIe Constraints

80

118

YHARTANTO_J44

01/04/2013

Project Specific Constraints

79

117

YHARTANTO_J44

01/02/2013

SMC Constraints

78

116

YHARTANTO_J44

01/09/2013

Camera Constraints

77

115

GKOO_J52

12/06/2013

TBT,DP,HDMI Constraints

76

114

YHARTANTO_J44

01/02/2013

Memory Constraints

75

113

YHARTANTO_J44

01/08/2013

PCH Constraints

74

112

YHARTANTO_J44

01/07/2013

USB Constraints

73

111

YHARTANTO_J44

01/13/2013

CPU Constraints

72

110

YHARTANTO_J44

12/14/2012

PCB Rule Definitions

71

104

GKOO_J52

12/06/2013

Functional & ICT Test

70

103

AHARTMAN_J52

10/29/2013

Memory Bit & Byte Swizzle

69

102

SHART_J44

11/19/2012

Signal Aliases

68

100

SHART_J44

01/14/2013

Power Aliases

67

97

SRAMAN_J44

01/29/2013

Display Mux: HDMI vs DP

66

95

GKOO_J52

05/01/2014

RIO Connector

65

83

GKOO_J52

05/04/2014

eDP Display Connector

64

81

AHARTMAN_J52

11/06/2013

Power Control

63

80

J41

10/23/2012

Power FETs

62

79

AHARTMAN_J52

11/06/2013

X239 Power Supply

61

78

AHARTMAN_J52

11/06/2013

Misc Power Supplies

60

77

SHART_J44

11/20/2012

LCD & KBD Backlight Driver

59

76

AHARTMAN_J52

10/29/2013

1.05V Power Supply

58

75

J14

10/23/2012

5V & 3.3V Power Supply

57

74

J41_MLB

05/21/2013

LPDDR3 Supply

56

73

J41

10/23/2012

CPU VR12.6 VCC Power Stage

55

72

J41

10/23/2012

CPU VR12.6 VCC Regulator IC

54

71

AHARTMAN_J52

11/06/2013

PBus Supply & Battery Charger

53

70

YHARTANTO_J44

01/09/2013

DC-In & Battery Connectors

52

66

JCURCIO_J44

05/13/2013

Audio: Jack Translators

51

65

JCURCIO_J44

07/25/2013

Audio: Jack Support

50

64

DIRK_J44

01/09/2013

Audio: Speaker Amps

49

63

JCURCIO_J44

07/25/2013

Audio: Codec,Digital

48

62

JCURCIO_J44

05/13/2013

Audio: Codec,Analog

47

61

YHARTANTO_J44

01/09/2013

SPI Debug Connector

46

60

J41

10/23/2012

Fan

45

58

YHARTANTO_J44

01/07/2013

Thermal Sensors

44

56

JACK_J52

10/26/2013

Power Sensors: Extended

820-4924

1

PCBF,MLB,X304

PCB

CRITICAL

051-1573

SCHEM,MLB,X304

SCH1

CRITICAL

43

55

JACK_J52

12/06/2013

Power Sensors: Load Side

1

YHARTANTO_J44

12/21/2012

Table of Contents

Contents

(.csa)

Page DateSync

(.csa)

Page Sync Date

Contents

TABLE_BOMGROUP_ITEM

TABLE_STRATEGIC__ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_STRATEGIC__ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_STRATEGIC__ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

COMMENT

PART#

TABLE_STRATEGIC_HEAD

STRATEGIC VALUE

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_STRATEGIC__ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Main DRAM Parts

Variable BOM Groups

SMC

BOM Groups

Module Parts

Sub-BOMs

Main DRAM SPD Straps

Development/Base BOMs

EFI ROM

TBT

S2 DRAM Parts

Strategic Silicon

DVT

Programmables (All Builds)

U0500

337S00109

1

CPU_BDW23:3.1G

CRITICAL

CPU,BW,SR26E,PRQ,F0-B2,3.1,28W,1.1,1168

CRITICAL

1

998-7866

CPU_SOCKET

INTERPOSER,BGA1168P, SINGLE SIDE

U0500

ALTERNATE,ENGISNS,XDP_CONN,S0PGOOD_ISL

X304_DEVEL:DVT

SYS MEMORY HYNIX

07333S0784

SYNC_DATE=11/27/2012

BOM Configuration

SYNC_MASTER=SHART_J44

U2300,U2400,U2500,U2600

8G_HYNIX_1600

CRITICAL

4

333S0785

IC,SDRAM,29nm 16Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,29nm 8Gb,LPDDR3-1600,178P FBGA

CRITICAL

4G_HYNIX_1600

U2300,U2400,U2500,U2600

4

333S0787

U2300,U2400,U2500,U2600

CRITICAL

IC,SDRAM,25nm 8Gb,LPDDR3-1600,178P FBGA

4

333S0793

4G_ELPIDA_1600

X304_PROGPARTS

SMC_PROG:PROTO0,BOOTROM_PROG,TBTROM_PROG

X304_COMMON3

XDP,SAMCONN,BKLT:PROD,CPUTHRM:ALRT,LOADRC:NO,OTHERRC:NO,DDRRC:NO,TBTRC:NO,BMONRC:NO,TPADRC:NO

EFI ROM

01

341S00235

01

S2 MEMORY

333S0700

343S0511 01

PCIE DELAY IC

DDC CROSSBAR

353S00095

01

353S3931

TBT PWR MUX

01

GREEN CLOCK

01359S0197

KEYBOARD I2C EXPANDER

02311S0597

T29,EPROM,FALCON RIDGE (V27.1) EVT2,X304

TBTROM_PROG

341S00192

1

CRITICAL

U2890

CRITICAL341S3982

U5000

SMC_PROG:PROTO0

IC,SMC-B1,EXT(V2.21A5) PROTO 0,X304

1

X304_COMMON4

SMCBOARDID:16

685-1314

BASE

1

CRITICAL

X304 MLB COMMON BOM

BASE_BOM

341S00235

U6100

CRITICAL

1

BOOTROM_PROG

EFI ROM,MLB (V0145) DVT,X304

X304_COMMON2

EDP,EDP_LS_CAP,CAMERA_3V3:S0,CAM_WAKE:NO,CAM_XTAL:NO,VCORE_FETS

X304_COMMON1

TBTHV:P15V,SKIP_5V3V3:AUDIBLE,PANEL:NEW,SSD_CLKREQ:BI

ALTERNATE,COMMON,X304_COMMON1,X304_COMMON2,X304_COMMON3,X304_COMMON4,X304_PROGPARTS

X304_COMMON

353S2888

AUDIO AMPS

01

AUDIO AMPS

353S2958

01

BAT CHARGER

353S2929

01

T29 ROM

341S00192

SMC

01341S3982

1

CRITICAL

DEVEL

DEVEL_BOM

X304 MLB DEVEL BOM

985-1319

16G_HYNIX_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

RAM_16G_HYNIX_1600

RAM_16G_HYNIX_1866

16G_HYNIX_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

VCOREFETS

VCORE FET,VSHY,X304

CRITICAL685-1318

1

VCORE_FETS

RAM_8G_HYNIX_1600

8G_HYNIX_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

8G_HYNIX_1866

IC,SDRAM,29nm 16Gb,LPDDR3-1866,178P FBGA

U2300,U2400,U2500,U2600

4

333S0786

CRITICAL

8G_HYNIX_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

RAM_8G_HYNIX_1866

16G_ELPIDA_1600

IC,SDRAM,25nm 32Gb,LPDDR3-1600,178P FBGA

U2300,U2400,U2500,U2600

4

333S0789

CRITICAL

IC,SDRAM,25nm 32Gb,LPDDR3-1866,178P FBGA

U2300,U2400,U2500,U2600

16G_HYNIX_1866

CRITICAL

4

333S0784

4G_HYNIX_1866

IC,SDRAM,29nm 8Gb,LPDDR3-1866,178P FBGA

U2300,U2400,U2500,U2600

4

333S0788

CRITICAL

IC,SDRAM,25nm 16Gb,LPDDR3-1600,178P FBGA

CRITICAL

U2300,U2400,U2500,U2600

4

333S0791

8G_ELPIDA_1600

8G_ELPIDA_1866

IC,SDRAM,25nm 16Gb,LPDDR3-1866,178P FBGA

CRITICAL

U2300,U2400,U2500,U2600

4

333S0792

4G_HYNIX_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

RAM_4G_HYNIX_1600

4G_HYNIX_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM_4G_HYNIX_1866

16G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

RAM_16G_ELPIDA_1600

16G_ELPIDA_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

RAM_16G_ELPIDA_1866

8G_SAMSUNG_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

RAM_8G_SAMSUNG_1600

8G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

RAM_8G_ELPIDA_1600

8G_SAMSUNG_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAM_8G_SAMSUNG_1866

4G_ELPIDA_1600,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

RAM_4G_ELPIDA_1600

4G_ELPIDA_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM_4G_ELPIDA_1866

8G_ELPIDA_1866,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

RAM_8G_ELPIDA_1866

4G_SAMSUNG_1600,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

RAM_4G_SAMSUNG_1600

8G_SAMSUNG_1866

CRITICAL

U2300,U2400,U2500,U2600

IC,SDRAM,23nm 16Gb,LPDDR3-1866,178P FBGA

4

333S00004

4G_SAMSUNG_1866

CRITICAL

U2300,U2400,U2500,U2600

IC,SDRAM,23nm 8Gb,LPDDR3-1866,178P FBGA

4

333S00002

U2300,U2400,U2500,U2600

IC,SDRAM,25nm 32Gb,LPDDR3-1600,178P FBGA

16G_HYNIX_1600

CRITICAL

4

333S0783

IC,SDRAM,25nm 32Gb,LPDDR3-1866,178P FBGA

CRITICAL

U2300,U2400,U2500,U2600

4

333S0790

16G_ELPIDA_1866

4G_ELPIDA_1866

CRITICAL

U2300,U2400,U2500,U2600

IC,SDRAM,25nm 8Gb,LPDDR3-1866,178P FBGA

4

333S0794

8G_SAMSUNG_1600

CRITICAL

U2300,U2400,U2500,U2600

IC,SDRAM,23nm 16Gb,LPDDR3-1600,178P FBGA

4

333S00003

4G_SAMSUNG_1600

CRITICAL

U2300,U2400,U2500,U2600

IC,SDRAM,23nm 8Gb,LPDDR3-1600,178P FBGA

4

333S00001

U4000

IC,SDRAM,4GBIT.DDR3L-1600,HUMA,96B BGA

1

333S0700

4G_SAMSUNG_1866,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAM_4G_SAMSUNG_1866

TPAD ELEC FUSE

07

353S00200

333S00004

07

SYS MEMORY SAMSUNG

CPU

337S00068

08

SYS MEMORY MICRON

07333S0792

333S0790 07

SYS MEMORY MICRON

SYS MEMORY HYNIX

07333S0786

FALCON RIDGE

338S1247 01

TBT MUX

01353S3812

TBT MUX

01353S3814

DDC CROSSBAR

01353S3328

338S1264

S2

01

01353S3054

USB POWER/SAFETY

353S4080

AUDIO

01

337S00069

CPU

08

337S00071

CPU

08

337S00070

08

CPU

01

S2 MEMORY

333S0704

343S0649

SMC RESET CHIP

01

343S0666 01

SAK, HDMI SELECT

01

BEN

353S4160

01

VR12.6 CONTROLLER

353S00036

ALTERNATE,ENGISNS,XDP_CONN,DBGLED

X304_DEVEL:ENG

ALTERNATE

X304_DEVEL:PVT

LOADISNS,OTHERISNS,DDRISNS,TBTISNS,BMONISNS,TPADISNS

ENGISNS

1

CRITICAL

CPU_BDW23:2.7G

U0500

337S00107

CPU,BW,SR26K,PRQ,F0-B2,2.7,28W,1.05,1168

U0500

CPU,BW,SR26H,PRQ,F0-B2,2.9,28W,1.1,1168

337S00108

CRITICAL

1

CPU_BDW23:2.9G

MOSFET,N-CH,30V,15.3A,12M,8P 3.3X3.3 DFN

CRITICAL

VCORE_FET:VSHY

2

376S1194

Q7310,Q7320

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

U2800

CRITICAL

1

338S1247

MOSFET,N-CH,30V,22A,6.0M,8P 3.3X3.3 DFN

CRITICAL

VCORE_FET:VSHY

376S1193

2

Q7311,Q7321

338S1264

IC,BCM15700A2KFEB4G,S2 CMRA,8X8,208FCBGA

CRITICAL

1

U3900

MOSFET,N-CH,30V,52A,5.9MO,3.3X3.3 DFN8

CRITICAL

Q7310,Q7320

2

376S00036

VCORE_FET:ONSMI

MOSFET,N-CH,30V,64A,3.5MO,3.3X3.3 DFN8

VCORE_FET:ONSMI

2

376S00037

Q7311,Q7321

CRITICAL

dvt1

051-1573

8.0.0

2 OF 120

2 OF 82

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

BOM Variants

Alternate Parts

740S00003

ALL

AEM alt to Tyco

740S0135

639-00035

PCBA,MLB,NO CPU,X304

BASE_BOM,DEVEL_BOM,RAM_8G_HYNIX_1866

VCORE FET,VSHY,X304

685-1318

VCORE_FET:VSHY

VCORE FET,ONSMI,X304 VCORE_FET:ONSMI

685-00022

376S0761

376S00014

Toshiba alt to Vishay

ALL

ALL353S00231

353S3987

NXP alt to TI

ALL131S00041

Murata alt to Taiyo Yuden

131S00040

ALL

TFT alt to Cyntec

107S00011

107S00015

107S00032

107S00031

TFT alt to Cyntec

ALL

BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_8G_ELPIDA_1866

MLB,BDW2+3,3.1GHz,8GB-EP-1866,X304

639-00784

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_8G_SAMSUNG_1866

639-00781

MLB,BDW2+3,2.9GHz,8GB-SM-1866,X304

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_16G_ELPIDA_1866

639-00780

MLB,BDW2+3,2.9GHz,16GB-EP-1866,X304

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_8G_SAMSUNG_1866

MLB,BDW2+3,2.7GHz,8GB-SM-1866,X304

639-00776

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_16G_ELPIDA_1866

MLB,BDW2+3,2.7GHz,16GB-EP-1866,X304

639-00775

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_8G_ELPIDA_1866

MLB,BDW2+3,2.7GHz,8GB-EP-1866,X304

639-00774

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_16G_HYNIX_1866

MLB,BDW2+3,2.7GHz,16GB-HY-1866,X304

639-00773

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.7G,RAM_8G_HYNIX_1866

MLB,BDW2+3,2.7GHz,8GB-HY-1866,X304

639-00772

X304_DEVEL:ENG

DEV,MLB,X304

985-1319

X304_COMMON

685-1314

COMMON,MLB,X304

353S00095

353S3328

ALL

Pericom alt to TI

138S0706

ALL

138S0739

Samsung alt to Murata

ALL

376S00074

Toshiba alt for Diodes Dual

376S0855

ALL

128S0329128S0311 NEC alt to Sanyo

107S00030

107S00029

TFT alt to Cyntec

ALL

353S00133

ALL

353S2741 Onsemi alt to TI

107S0226

107S00024

ALL

Yageo alt to Cyntec

372S0186 372S0185

ALL

NXP alt to Diodes

353S00135

ALL

Onsemi alt to Fairchild

353S2220

371S0749

ALL

371S00017

Diodes alt to Onsemi

371S00019

Rohm alt to Rohm371S0463

ALL

Diodes alt to NXP

311S00015

311S0450

ALL

ALLANY

353S00107

353S3239

Onsemi alt to Intersil

311S00013

ALL

311S0508

Diodes alt to NXP

311S00008

311S0271

ALL

Diodes alt to NXP

311S00014

311S0515

ALL

Diodes alt to NXP

ALL

353S2220

353S00034

Pericom alt to Fairchild

ALL

128S0436

Kemet alt to Sanyo

128S0392

155S0897

ALL

155S0914

Panasonic alt to TDK

On Semi alt to Infineon

ALL

377S0155 377S0184

ALL

Elpida alt to Hynix for S2 Camera DDR3 Memory

333S0700333S0704

Onsemi alt to Vishay for CPU Core Mosfets

685-1318

685-00022

ALL

371S0713

ALL

ST Micro alt to Diodes

371S0558

371S00018

Rohm alt to Rohm371S0619

ALL

376S1053

Diodes alt to Fairchild

376S0604

Panasonic alt to Sanyo

128S0445 128S0392

ALL

197S0479 197S0478 Epson alt to NDK

ALL

127S0164

Rohm alt to Vishay

ALL

127S0162

ALL

377S00011

377S0184

Infineon alt to Infineon

128S0397 128S0325

ALL

Kemet alt to Sanyo

138S1101

Samsung alt to Murata for LCD BKL caps

138S0738

ALL

155S0513155S0660

Murata alt to TDK

ALL

Murata alt to TDK

ALL

155S0694 155S0387

Murata, TDK, Samsung, Taiyo Yuden alt to Murata, TDK

138S0578

ALL

138S0614

ALL

353S4070 353S4069

Pericom alt to TI DP Mux U9750

NXP alt to TI DP Mux U9750

ALL

353S4068 353S4069

138S0843

ALL

138S0674

Samsung alt to Murata (BKLT)

ALL

107S0250

TFT alt to Cyntec

107S0248

NDK alt to TXC

ALL

197S0542 197S0544

Cyntec alt to TFT

107S0254

ALL

107S0241

353S3452

ALL

353S1286

Maxim alt to Microchip

ALL

138S0725

Samsung alt to Murata

138S0724

ALL

Cyntec alt to Vishay

152S1645152S0461

ALL

Epson alt to NDK197S0480197S0481

ALL

Diodes alt to On Semi

376S0820376S1080

311S0426

ALL

Diodes alt to NXP

311S00007

128S0284

ALL

128S0386

Kemet alt to Sanyo

128S0220

ALL

128S0398

Kemet alt to Sanyo

311S0541

ONsemi alt to Toshiba

311S0649

ALL

138S0811138S0846

Samsung alt to Murata (BKLT)

128S0364

ALL

Sanyo 2nd Factory alt

128S0264

376S0855

NXP Alt for Diodes Dual

ALL

376S1129

376S1128376S1089

ALL

NXP Alt for Diodes Single

ALL

197S0545 Epson alt to TXC197S0544

BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_8G_SAMSUNG_1866

MLB,BDW2+3,3.1GHz,8GB-SM-1866,X304

639-00786

BOM Configuration

SYNC_DATE=09/04/2012

SYNC_MASTER=J14

TI alt to NXP

ALL

353S3812353S3814

MLB,BDW2+3,2.9GHz,8GB-HY-1866,X304

639-00777

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_8G_HYNIX_1866

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_16G_HYNIX_1866

MLB,BDW2+3,2.9GHz,16GB-HY-1866,X304

639-00778

MLB,BDW2+3,2.9GHz,8GB-EP-1866,X304

639-00779

BASE_BOM,DEVEL_BOM,CPU_BDW23:2.9G,RAM_8G_ELPIDA_1866

BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_8G_HYNIX_1866

639-00782

MLB,BDW2+3,3.1GHz,8GB-HY-1866,X304

BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_16G_HYNIX_1866

639-00783

MLB,BDW2+3,3.1GHz,16GB-HY-1866,X304

BASE_BOM,DEVEL_BOM,CPU_BDW23:3.1G,RAM_16G_ELPIDA_1866

639-00785

MLB,BDW2+3,3.1GHz,16GB-EP-1866,X304

BASE_BOM,DEVEL_BOM,CPU_SOCKET,RAM_8G_HYNIX_1866

639-00036

PCBA,MLB,CPU SOCKET,X304

dvt1

051-1573

8.0.0

3 OF 120

3 OF 82

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

IPD FLEX BRACKET BOSSES (860-00166)

RIO FLEX BRACKET BOSSES (860-00166)

SH0435 & SH0436 removed.

Mounting Holes & Slots

Memory Shield CAN (806-00037)

(998-3975)

SNOWMAN-SHAPED SLOT AT LEFT OF MEMORY BANK

Shield Cans

USB can Ground slot

(998-5879)

Upper TBT can Ground slot

Lower TBT can Ground slot

(862-0118)

(998-3975)

(998-1195)

USB can Ground slot

USB Cage

Rubber Mount Standoffs (860-1448)

TBT Cage

ABOVE GUMSTICK CARD IN MIDDLE OF BOARD

(998-5879)

SNOWMAN-SHAPED SLOT AT RIGHT OF MEMORY BANK

(862-0118)

THERMAL MODULE STANDOFF (860-00165)

FAN STANDOFF (860-00183)SSD STANDOFF (860-00164)

POGO PINS (870-00607)

2.9OD1.2ID-1.35H-SM

SM

POGO-2.3OD-5.5H-X304

5.0OD2.0H

3.5OD1.85ID-2.0H

4.5OD1.85ID-1.78H-SM4.5OD1.85ID-1.78H-SM

4.5OD1.85ID-1.78H-SM 4.5OD1.85ID-1.78H-SM

POGO-2.3OD-5.5H-X304

SM

2.9OD1.2ID-1.35H-SM2.9OD1.2ID-1.35H-SM

SM

SHLD-FENCE-MLB-DRAM-X304

3.5OD1.85ID-2.0H

SM

SHIELD-FENCE-MLB-T29-X304

OMIT

4P5R2P3-3P5B

SM

SHLD-J44-MLB

STDOFF-4.5ID1.73H-SM

OMIT

6.19X4.60-SNOWMAN

OMIT

6.19X4.60-SNOWMAN

TH-NSP

SL-1.1X0.45-1.4x0.75

TH-NSP

SL-1.1X0.45-1.4x0.75

TH-NSP

SL-1.1X0.5-1.4x0.8

TH-NSP

2.9OD1.2ID-1.35H-SM

SYNC_MASTER=LDUNN_J44

BOM_COST_GROUP=PD PARTS

SYNC_DATE=01/13/2013

PD Parts

SH0432

1

SH0433

1

ZT0411

1

SH0451

1

SH0441

1

ZT0413

1

ZT0414

1

TH0405

1

TH0404

1

TH0403

1

TH0400

1

SH0460

1

2

SH0462

1

2

SH0464

1

2

SH0466

1

2

SH0461

1

2

SH0465

1

2

SH0463

1

2

SH0467

1

2

SH0440

1

SH0443

1

SH0421

1

SH0420

1

SH0426

1

SH0427

1

SH0469

1

2

SH0468

1

2

SH0452

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

42

43

44

45

46

47

48

49

5

50

51

52

53

54

55

56

57

58

59

6

60

61

62

63

64

7

8

9

SH0471

1

SH0450

1

dvt1

051-1573

8.0.0

4 OF 120

4 OF 82

OUT

BI

DDI

EDP

SYM 1 OF 19

EDP_TXN0

EDP_TXP1

EDP_TXN1

EDP_TXP0

DDI1_TXP2

DDI1_TXN2

DDI2_TXP3

DDI2_TXN3

DDI2_TXP2

DDI2_TXN2

DDI2_TXP1

DDI2_TXN1

DDI2_TXP0

DDI1_TXP1

DDI1_TXN1

DDI1_TXP0

DDI1_TXN0

DDI2_TXN0

DDI1_TXP3

DDI1_TXN3

EDP_RCOMP

EDP_DISP_UTIL

EDP_AUXN

EDP_AUXP

EDP_TXP3

EDP_TXN3

EDP_TXP2

EDP_TXN2

SYM 17 OF 19

DAISY_CHAIN_NCTF

SPARE

SYM 18 OF 19

RSVD

TP

NC NC

NCNC

NC

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

MCP Daisy-Chain Strategy:

Each corner of CPU has two testpoints.

NO_TEST NO_TEST

Other corner test signals connected in

daisy-chain fashion. Continuity should

exist between both TP’s on each corner.

eDP Port Assignment:

Internal panel

DDI Port Assignments:

if necessary)

(MUXed with HDMI

TBT Sink 1

TBT Sink 0

69

65 77

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

TP-P6

1/20W

1%

201

MF

24.9

25 77

69

BOM_COST_GROUP=CPU

CPU GFX,NCTF,RSVD

SYNC_MASTER=J41

SYNC_DATE=10/23/2012

MCP_DC_B2

MCP_DC_A60

MCP_DC_A4

MCP_DC_A62

MCP_DC_AV1

MCP_DC_AW1

MCP_DC_AW63

MCP_DC_AY60

DP_TBTSNK0_ML_C_N<1>

DP_INT_ML_C_N<0>

DP_INT_ML_C_P<1>

DP_INT_ML_C_N<1>

DP_INT_ML_C_P<0>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<2>

=DP_TBTSNK1_ML_C_P<3>

=DP_TBTSNK1_ML_C_N<3>

=DP_TBTSNK1_ML_C_P<2>

=DP_TBTSNK1_ML_C_N<2>

=DP_TBTSNK1_ML_C_P<1>

=DP_TBTSNK1_ML_C_N<1>

=DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_ML_C_N<0>

=DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<3>

DP_INT_AUXCH_C_N

DP_INT_AUXCH_C_P

DP_INT_ML_C_P<3>

DP_INT_ML_C_N<3>

DP_INT_ML_C_P<2>

DP_INT_ML_C_N<2>

PPVCOMP_S0_CPU

TP_EDP_DISP_UTIL

MCP_EDP_RCOMP

TRUE

MCP_DC_C1_C2

TRUE

MCP_DC_A3_B3

TRUE

MCP_DC_A61_B61

TRUE

MCP_DC_AW2_AY2

TRUE

MCP_DC_AW61_AY61

TRUE

MCP_DC_AW3_AY3

TRUE

MCP_DC_AW62_AY62

TRUE

MCP_DC_AW62_AY62

TRUE

MCP_DC_A61_B61

TRUE

MCP_DC_A3_B3

TRUE

MCP_DC_B62_B63

TRUE

MCP_DC_AW61_AY61

TRUE

MCP_DC_AW3_AY3

TRUE

MCP_DC_AW2_AY2

TP0531

1

TP0500

1

TP0510

1

TP0501

1

TP0511

1

TP0520

1

TP0521

1

TP0530

1

R0530

1

2

U0500

C54

B58

B55

A57

C55

C58

A55

B57

C51

C53

C49

A53

C50

B54

B50

B53

A45

B45

A43

D20

C45

A47

C47

A49

B46

B47

C46

B49

U0500

A3

A4

A60

A61

A62

AV1

AW1

AW2

AW3

AW61

AW62

AW63

AY2

AY3

AY60

AY61

AY62

B2

B3

B61

B62

B63

C1

C2

U0500

AL1

AM11

AP7

AT2

AU10

AU15

AU44

AV44

AW14

AY14

D15

F22

H22

J21

N23

R23

T23

U10

5 OF 82

5 OF 120

8.0.0

051-1573

dvt1

8

73

5

BI

NC

SYM 2 OF 19

MISC

THERMAL

JTAG

DDR3

PWR

SM_PG_CNTL1

SM_DRAMRST*

SM_RCOMP1

SM_RCOMP2

SM_RCOMP0

PROCHOT*

PROCPWRGD

PECI

CATERR*

BPM7*

BPM6*

BPM5*

BPM4*

BPM3*

BPM2*

BPM1*

BPM0*

PROC_TDO

PROC_TDI

PROC_TRST*

PROC_TMS

PROC_TCK

PREQ*

PRDY*

PROC_DETECT*

RESERVED

SYM 19 OF 19

VSS

RSVD

CFG_RCOMP

RSVD

TD_IREF

CFG0

CFG1

CFG5

CFG4

CFG3

CFG2

CFG6

CFG10

CFG9

CFG8

CFG7

CFG11

CFG15

CFG14

CFG13

CFG12

CFG18

CFG16

CFG17

CFG19

RSVD

RSVD_TP

RSVD

PROC_OPI_COMP

RSVD

RSVD_B43

BI

OUT

NC

BI

OUT

IN

OUT

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

(IPD)

and are only for debug access

These can be placed close to J1800

CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED

CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid

issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE

CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK

(IPU)

1/20W

5%

201

MF

1K

NOSTUFF

1/20W

5%

201

MF

1K

HSW_PRE_ES2

1/20W

5%

201

MF

1K

NOSTUFF

1/20W

5%

201

MF

1K

NOSTUFF

1/20W

5%

201

MF

1K

NOSTUFF

6

16 73

6

16 73

6

16 73

6

16 73

6

16 73

6

16 73

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

38 39 55 73

1/20W

5%

201

MF

62

1/20W

5%

201

MF

56

39 73

38 73

1/20W

5%

201

MF

10K

PLACE_NEAR=U0500.C61:12.7mm

16 73

16

16 73

1/20W

1%

201

MF

100

PLACE_NEAR=U0500.AU61:12.7mm

1/20W

1%

201

MF

121

PLACE_NEAR=U0500.AV60:12.7mm

1/20W

1%

201

MF

200

PLACE_NEAR=U0500.AU60:12.7mm

70

17

1/20W

1%

201

MF

49.9

1/20W

1%

201

MF

49.9

1/20W

1%

201

MF

8.25K

1/20W

5%

201

MF

1K

EDP

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

SYNC_DATE=10/23/2012

CPU Misc,JTAG,CFG,RSVD

CPU_PROCHOT_L

=PP1V05_S0_CPU_VCCST

CPU_CFG<0>

CPU_CFG<1>

CPU_CFG<8>

CPU_CFG<10>

CPU_CFG<9>

CPU_CFG<4>

XDP_CPU_PREQ_L

XDP_CPU_TCK

XDP_CPU_TMS

XDP_CPU_TRST_L

XDP_CPU_TDI

XDP_CPU_TDO

XDP_BPM_L<0>

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

CPU_PECI

CPU_PWRGD

CPU_PROCHOT_R_L

CPU_SM_RCOMP<0>

CPU_SM_RCOMP<2>

CPU_SM_RCOMP<1>

=MEM_RESET_L

CPU_MEMVTT_PWR_EN_LSVDDQ

XDP_CPU_PRDY_L

XDP_BPM_L<6>

XDP_BPM_L<7>

CPU_OPI_RCOMP

TP_MCP_RSVD_C62

TP_MCP_RSVD_C63

TP_MCP_RSVD_AU63

TP_MCP_RSVD_AV63

CPU_CFG<19>

CPU_CFG<17>

CPU_CFG<16>

CPU_CFG<18>

CPU_CFG<12>

CPU_CFG<13>

CPU_CFG<14>

CPU_CFG<15>

CPU_CFG<11>

CPU_CFG<7>

CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<10>

CPU_CFG<6>

CPU_CFG<2>

CPU_CFG<3>

CPU_CFG<5>

CPU_CFG<1>

CPU_CFG<0>

PCH_TD_IREF

CPU_CFG_RCOMP

TP_MCP_RSVD_L60

TP_MCP_RSVD_A51

TP_MCP_RSVD_B51

CPU_CFG<4>

XDP_BPM_L<1>

CPU_CATERR_L

R0610

1

2

R0611

12

R0620

1

2

R0652

1

2

R0651

1

2

R0650

1

2

R0680

1

2

R0690

1

2

R0685

1

2

R0634

1

2

R0640

1

2

R0639

1

2

R0638

1

2

R0631

1

2

R0630

1

2

U0500

J60

H60

H61

H62

K59

H63

K60

J61

K61

N62

J62

K62

D61

E60

F63

F62

E61

E59

K63

C61

AV15

AV61

AU60

AV60

AU61

U0500

AC60

AC62

V60

U60

T63

T62

T61

T60

AA62

AA61

U63

U62

AC63

AA63

AA60

Y62

Y61

Y60

V62

V61

V63

AY15

A5

AV62

B43

D1

D58

E1

H18

J20

N60

P20

R20

A51

AU63

AV63

B51

C62

C63

L60

W23

Y22

B12

N21

P22

6 OF 82

6 OF 120

8.0.0

051-1573

dvt1

8

15 16 17 55 68

6

16 73

6

16 73

6

16 73

6

16 73

6

16 73

6

16 73

73

BI

OUT

BI

OUT

BI

SYM 3 OF 19

MEMORY CHANNEL A

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ55

SA_DQ56

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ45

SA_DQ46

SA_DQ42

SA_DQ43

SA_DQ44

SA_DQ40

SA_DQ41

SA_DQ39

SA_DQ37

SA_DQ38

SA_DQ34

SA_DQ36

SA_DQ32

SA_DQ33

SA_DQ29

SA_DQ30

SA_DQ31

SA_DQ27

SA_DQ28

SA_DQ24

SA_DQ25

SA_DQ22

SA_DQ23

SA_DQ21

SA_DQ19

SA_DQ20

SA_DQ17

SA_DQ18

SA_DQ16

SA_DQ14

SA_DQ15

SA_DQ11

SA_DQ13

SA_DQ10

SA_DQ9

SA_DQ7

SA_DQ8

SA_DQ6

SA_DQ4

SA_DQ5

SA_DQ3

SA_DQ1

SA_DQ0

SA_CLK1*

SA_CLK0

SA_CLK0*

SA_DQ12

SM_VREF_DQ1

SM_VREF_CA

SM_VREF_DQ0

SA_DQ35

SA_DQ26

SA_DQ2

SA_CLK1

SA_CS0*

SA_CS1*

SA_CKE0

SA_CKE1

SA_CKE2

SA_CKE3

SA_ODT0

SA_RAS*

SA_WE*

SA_CAS*

SA_MA0

SA_MA2

SA_MA1

SA_MA3

SA_MA4

SA_MA5

SA_MA7

SA_MA6

SA_MA8

SA_MA10

SA_MA9

SA_MA12

SA_MA11

SA_MA13

SA_MA14

SA_MA15

SA_BA2

SA_BA0

SA_BA1

SA_DQSP0

SA_DQSP2

SA_DQSP1

SA_DQSP3

SA_DQSP4

SA_DQSP5

SA_DQSP6

SA_DQSP7

SA_DQSN1

SA_DQSN0

SA_DQSN2

SA_DQSN4

SA_DQSN3

SA_DQSN5

SA_DQSN6

SA_DQSN7

SYM 4 OF 19

MEMORY CHANNEL B

SB_DQ0

SB_DQ1

SB_DQ2

SB_DQ3

SB_DQ4

SB_DQ5

SB_CKE0

SB_DQ6

SB_CKE1

SB_DQ7

SB_CKE2

SB_DQ8

SB_CKE3

SB_DQ9

SB_DQ10 SB_CS0*

SB_DQ11 SB_CS1*

SB_DQ12

SB_DQ13 SB_ODT0

SB_DQ14

SB_DQ15 SB_RAS*

SB_DQ16

SB_WE*

SB_DQ17 SB_CAS*

SB_DQ18

SB_DQ19

SB_BA0

SB_DQ20

SB_BA1

SB_DQ21

SB_BA2

SB_DQ22

SB_DQ23

SB_MA0

SB_DQ24

SB_MA1

SB_DQ25

SB_MA2

SB_DQ26

SB_MA3

SB_DQ27

SB_MA4

SB_DQ28

SB_MA5

SB_DQ29

SB_MA6

SB_DQ30

SB_MA7

SB_DQ31

SB_MA8

SB_DQ32

SB_MA9

SB_DQ33 SB_MA10

SB_DQ34 SB_MA11

SB_DQ35 SB_MA12

SB_MA13

SB_DQ37 SB_MA14

SB_DQ38 SB_MA15

SB_DQ39

SB_DQ40

SB_DQSN0

SB_DQ41

SB_DQSN1

SB_DQ42

SB_DQSN2

SB_DQ43

SB_DQSN3

SB_DQ44

SB_DQSN4

SB_DQ45

SB_DQSN5

SB_DQ46

SB_DQSN6

SB_DQ47

SB_DQSN7

SB_DQ48

SB_DQ49

SB_DQSP0

SB_DQ50

SB_DQSP1

SB_DQ51

SB_DQSP2

SB_DQ52

SB_DQSP3

SB_DQ53

SB_DQSP4

SB_DQ54

SB_DQSP5

SB_DQ55

SB_DQSP6

SB_DQ56

SB_DQSP7

SB_DQ57

SB_DQ58

SB_DQ59

SB_DQ60

SB_DQ61

SB_DQ62

SB_DQ63

SB_DQ36

SB_CK0*

SB_CK0

SB_CK1*

SB_CK1

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

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PAGE TITLE

SHEET

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CAA5

CAB9

RSVD1

CAB6

CAB1

CAB8

RSVD4

CAA2

CAA4

CAB9

CAA4

CAB7

CAB8

CAA9

CAB4

RSVD2

CAB2

CAB3

CAB1

CAA3

CAA1

CAA7

CAA6

CAB0

CAA8

CAB5

CAA0

CAA2

LPDDR3

CAA5

CAB5

CAB3

CAB2

CAB4

CAB6

LPDDR3

CAA3

CAA1

CAB7

CAA7

CAA6

CAB0

CAA9

CAA8

CAA0

RSVD3

70 71 76

70 76

70

20 21 24 76

20 24 76

21 24 76

20 24 76

70

70 76

21 24 76

19 76

22 24 76

23 24 76

22 24 76

23 24 76

22 23 24 76

70

70 76

70 71 76

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BOM_COST_GROUP=CPU

CPU LPDDR3 Interfaces

SYNC_DATE=10/23/2012

SYNC_MASTER=J41

MEM_A_DQ<33>

MEM_A_DQ<34>

=MEM_A_A<12>

MEM_B_DQ<36>

MEM_B_DQ<42>

MEM_B_DQ<12>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_DQ<29>

MEM_B_DQ<17>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_A_DQS_N<2>

MEM_A_DQS_N<0>

=MEM_A_A<14>

=MEM_A_A<13>

=MEM_A_A<11> MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<37>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<3>

MEM_A_DQS_N<4>

MEM_A_DQS_N<1>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<1>

MEM_A_DQS_P<2>

MEM_A_DQS_P<0>

=MEM_A_BA<1>

=MEM_A_A<15>

=MEM_A_A<9>

=MEM_A_A<10>

=MEM_A_A<8>

=MEM_A_A<7>

=MEM_A_A<4>

=MEM_A_A<3>

=MEM_A_CAS_L

=MEM_A_ODT<0>

MEM_A_CKE<3>

MEM_A_CKE<2>

MEM_A_CKE<1>

MEM_A_CS_L<1>

MEM_A_CLK_P<1>

MEM_A_DQ<2>

MEM_A_DQ<26>

MEM_A_DQ<35>

CPU_DIMMA_VREFDQ

CPU_DIMM_VREFCA

CPU_DIMMB_VREFDQ

MEM_A_CLK_N<1>

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DQ<3>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<6>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<9>

MEM_A_DQ<10>

MEM_A_DQ<13>

MEM_A_DQ<11>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<19>

MEM_A_DQ<21>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<32>

MEM_A_DQ<36>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

=MEM_A_BA<2>

=MEM_A_A<0>

=MEM_A_A<1>

=MEM_A_A<6>

MEM_B_CLK_P<1>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQS_P<7>

MEM_B_DQ<56>

MEM_B_DQS_P<6>

MEM_B_DQ<55>

MEM_B_DQS_P<5>

MEM_B_DQ<54>

MEM_B_DQS_P<4>

MEM_B_DQ<53>

MEM_B_DQS_P<3>

MEM_B_DQ<52>

MEM_B_DQS_P<2>

MEM_B_DQ<51>

MEM_B_DQS_P<1>

MEM_B_DQ<50>

MEM_B_DQS_P<0>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQS_N<7>

MEM_B_DQ<47>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQ<44>

MEM_B_DQS_N<3>

MEM_B_DQ<43>

MEM_B_DQS_N<2>

MEM_B_DQS_N<1>

MEM_B_DQ<41>

MEM_B_DQS_N<0>

MEM_B_DQ<40>

MEM_B_DQ<39>

=MEM_B_A<15>MEM_B_DQ<38>

=MEM_B_A<14>

=MEM_B_A<13>

=MEM_B_A<12>

=MEM_B_A<11>

=MEM_B_A<10>MEM_B_DQ<33>

=MEM_B_A<9>

MEM_B_DQ<32>

=MEM_B_A<8>

MEM_B_DQ<31>

=MEM_B_A<7>

MEM_B_DQ<30>

=MEM_B_A<6>

=MEM_B_A<5>

MEM_B_DQ<28>

=MEM_B_A<4>

MEM_B_DQ<27>

=MEM_B_A<3>

=MEM_B_A<2>

=MEM_B_A<1>

MEM_B_DQ<24>

=MEM_B_A<0>

MEM_B_DQ<23>

MEM_B_DQ<22>

=MEM_B_BA<2>MEM_B_DQ<21>

=MEM_B_BA<1>MEM_B_DQ<20>

=MEM_B_BA<0>MEM_B_DQ<19>

MEM_B_DQ<18>

=MEM_B_CAS_L

=MEM_B_WE_L

MEM_B_DQ<16>

=MEM_B_RAS_LMEM_B_DQ<15>

MEM_B_DQ<14>

=MEM_B_ODT<0>

MEM_B_DQ<13>

MEM_B_DQ<11>

MEM_B_CS_L<0>

MEM_B_DQ<10>

MEM_B_DQ<9>

MEM_B_CKE<3>

MEM_B_DQ<8>

MEM_B_CKE<2>

MEM_B_DQ<7>

MEM_B_CKE<1>

MEM_B_DQ<6>

MEM_B_CKE<0>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_CS_L<1>

MEM_A_DQ<39>

=MEM_A_A<5>

=MEM_A_A<2>

MEM_A_CS_L<0>

MEM_A_CKE<0>

=MEM_A_BA<0>

=MEM_A_WE_L

=MEM_A_RAS_L

MEM_A_DQ<14>

MEM_A_DQ<20>

MEM_A_DQ<27>

MEM_A_DQ<12>

MEM_A_DQ<15>

MEM_A_DQ<16>

MEM_A_DQ<28>

U0500

AU35

AV35

AY41

AU34

AU43

AW43

AY42

AY43

AV37

AU37

AY36

AW36

AP33

AR32

AH63

AH62

AP63

AP62

AM61

AM60

AP61

AP60

AP58

AR58

AM57

AK57

AK63

AL58

AK58

AR57

AN57

AP55

AR55

AM54

AK54

AL55

AK55

AK62

AR54

AN54

AY58

AW58

AY56

AW56

AV58

AU58

AV56

AU56

AH61

AY54

AW54

AY52

AW52

AV54

AU54

AV52

AU52

AK40

AK42

AH60

AM43

AM45

AK45

AK43

AM40

AM42

AM46

AK46

AM49

AK49

AK61

AM48

AK48

AM51

AK51

AK60

AM63

AM62

AJ61

AN62

AM58

AM55

AV57

AV53

AL43

AL48

AJ62

AN61

AN58

AN55

AW57

AW53

AL42

AL49

AU36

AY37

AP35

AW41

AU41

AR35

AV42

AU42

AR38

AP36

AU39

AR36

AV40

AW39

AY39

AU40

AP32

AY34

AW34

AP49

AR51

AP51

U0500

AL35

AM36

AU49

AM33

AN38

AM38

AL38

AK38

AY49

AU50

AW49

AV50

AM32

AK32

AY31

AW31

AY25

AW25

AV27

AU27

AV25

AU25

AM29

AK29

AL28

AK28

AY29

AR29

AN29

AR28

AP28

AN26

AR26

AR25

AP25

AK26

AM26

AW29

AK25

AL25

AY23

AW23

AY21

AW21

AV23

AU23

AV21

AU21

AV31

AY19

AW19

AY17

AW17

AV19

AU19

AV17

AU17

AR21

AR22

AU31

AL21

AM22

AN22

AP21

AK21

AK22

AN20

AR20

AK18

AL18

AV29

AK20

AM20

AR18

AP18

AU29

AY27

AW27

AW30

AV26

AN28

AN25

AW22

AV18

AN21

AN18

AV30

AW26

AM28

AM25

AV22

AW18

AM21

AM18

AP40

AR40

AK36

AV47

AU47

AK33

AR46

AP46

AP42

AR42

AR45

AP45

AW46

AY46

AY47

AU46

AL32

AM35

AK35

dvt1

051-1573

8.0.0

7 OF 120

7 OF 82

OUT

IN

NC

BI

NC

IN

OUT

IN

NC

OUT

NC

IN

NC

HSW ULT POWER

SYM 12 OF 19

VCC

VCCST

RSVD

RSVD_TP

VSS

PWR_DEBUG*

VSS

VCC_SENSE

RSVD

VCC

RSVD

VDDQ

RSVD

VCC

VDDQ

VCCIOA_OUT

RSVD

VIDALERT*

RSVD

VIDSOUT

VIDSCLK

VR_EN

VCCST_PWRGD

VR_READY

VCCIO_OUT

RSVD

SUS OSCILLATOR

SERIAL IO

THERMAL SENSOR

SYM 13 OF 19

USB2

LPT LP POWER

CORE

SPI RTC

HSIO

OPI

USB3

AZALIA/HDA

VRM/USB2/AZALIA

GPIO/LCC

ICC

VCCHSIO

VCCUSB3PLL

VCCSATA3PLL

VCCAPLL

DCPSUS3

VCCHDA

DCPSUS2

VCCDSW3_3

VCCCLK

VCCACLKPLL

DCPSUS4

VCCRTC

DCPRTC

VCCSPI

VCCASW

VCC1P05

DCPSUSBYP

VCCASW

DCPSUS1

VCCTS1_5

VCCSDIO

RSVD

VCCAPLL

VCC1_05

VCC3_3

VCCCLK

VCCSUS3_3

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

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SHEET

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DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BDW-ULT current estimates from Broadwell Mobile ULT Processor EDS vol.1 Doc# 514405, Rev.: 0.9v1

Wildcat Point-LP current estimates from Wildcat Point-LP PCH EDS, Doc# 515621, Rev. 0.9

Note [1] current numbers from clarification email, from Srini, dated 9/10/2012 2:11pm.

NOTE: Aliases not used on CPU supply outputs

18mA Max

185mA Max[1]

1499mA Max[1]

Max load: 300mA

R0800.2:

1.1A Max (LPDDR3: 1.2V)

VCCCLK: 200mA Max

40mA Max[1]

59mA Max[1]

57mA Max

1mA Max[1]

1.4A Max (DDR3: 1.5-1.35V)

32A Max

???mA Max

11mA Max

17mA Max

3.3mA Max[1]

VCCCLK: 200mA Max

31mA Max

to avoid any extraneous connections.

R0810.2:

1838mA Max

29mA Max[1]

42mA Max

WF: RSVD on Sawtooth Peak rev 1.0

114mA Max

WF: RSVD on Sawtooth Peak rev 1.0

R0802.2:

Powered in DeepSx

213mA Max[1]

WF: RSVD on Sawtooth Peak rev 1.0

Max load: 300mA

3mA Max

473mA Max[1]

41mA Max

0.3mA Max[1]

1/20W

1%

201

MF

130

PLACE_NEAR=U0500.L63:2.54mm

55 73

16

1/20W

5%

201

MF

100

PLACE_NEAR=U0500.C50:50.8mm

55 73

16 17 73

17 55

17

55 73

BYPASS=R0899:U0500:2.54mm

1UF

6.3V

10%

402

CERM

1/20W

1%

201

MF-LF

5.11

PLACE_NEAR=U0500.AG19:2.54MM

55 73

10V

20%

402

CERM

0.1UF

BYPASS=U0500.AE7::6.35mm

BYPASS=U0500.AG10::6.35mm

10V

20%

402

CERM

0.1UF

10V

20%

402

CERM

0.1UF

BYPASS=U0500.AG10::6.35mm

6.3V

10%

402

CERM

1UF

BYPASS=U0500.AG10::6.35mm

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

1/20W

5%

0201

MF

0

1/20W

5%

0201

MF

0

1/20W

5%

201

MF

43

PLACE_NEAR=U0500.L62:38.1mm

PLACE_NEAR=R0810.1:2.54mm

1/20W

1%

201

75

MF

BOM_COST_GROUP=CPU

CPU & PCH Power

SYNC_DATE=10/23/2012

SYNC_MASTER=J41

CPU_VIDSCLK

=PP1V05_S0_CPU_VCCST

TP_CPU_RSVD_P61

=PPVCC_S0_CPU

=PP3V3_SUS_PCH_VCC_SPI

=PP1V05_S0M_PCH_VCCASW

=PP1V5_S0_PCH_VCCTS

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S5_PCH_VCCDSW

=PP3V3R1V5_S0SW_PCH_VCCSUSHDA

PP1V05_S0_PCH_VCC_ICC

PP1V05_S0_PCH_VCCACLKPLL

=PP1V05_S0_PCH_VCCCLK

PP1V05_S0SW_PCH_VCCUSB3PLL

=PP3V3_SUS_PCH_VCCSUS_GPIO

PP1V05_S0_PCH_VCCAPLL_OPI

=PP1V05_S0_PCH_VCCIO_USB2

=PP3V3R1V8_S0_PCH_VCCSDIO

=PP1V05_S0_PCH_VCCIO_HSIO

=PP3V3_SUS_PCH_VCCSUS_ICC

PP1V05_S0SW_PCH_VCCSATA3PLL

=PP1V05_S0SW_PCH_VCCHSIO

CPU_VCCSENSE_P

CPU_VIDALERT_L

=PPVMEMIO_S0_CPU

=PPVCC_S0_CPU

=PP1V05_S0_CPU_VCCST

=PP3V3_S0_PCH_VCCTS

=PP1V05_S0M_PCH_VCCASW

CPU_VIDSOUT

TP_CPU_RSVD_N59

TP_CPU_RSVD_N61

=PP1V05_S0_PCH_VCC

=PPVRTC_G3_PCH

=PP3V3_SUS_PCH_VCCSUS_RTC

TP_CPU_RSVD_P60

CPU_VIDSCLK_R

CPU_VIDALERT_R_L

CPU_PWR_DEBUG

CPU_VIDSOUT_R

CPU_VCCST_PWRGD

CPU_VR_EN

CPU_VR_READY

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=1.05V

PPVOUT_S0_PCH_DCPRTC

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=1.05V

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=1.05V

TP_PPVCCIO_S0_CPU

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=1.05V

PPVOUT_S5_PCH_DCPSUSBYP

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PPVCOMP_S0_CPU

VOLTAGE=1.05V

R0811

12

R0812

12

R0810

12

R0800

1

2

R0802

1

2

R0860

1

2

C0899

1

2

R0899

12

C0895

1

2

C0892

1

2

C0891

1

2

C0890

1

2

U0500

H59

AA23

AA59

AB23

AC58

AC59

AD23

AD59

AD60

AE59

AE60

AG58

J58

L59

N58

T59

N59

N61

P60

P61

U59

V59

F59

AB57

AD57

AG57

C24

C28

C32

C36

C40

C44

C48

C52

C56

E23

E25

E27

E29

E31

E33

E35

E37

E39

E41

E43

E45

E47

E49

E51

E53

E55

E57

F24

F28

F32

F36

F40

F44

F48

F52

F56

G23

G25

G27

G29

G31

G33

G35

G37

G39

G41

G43

G45

G47

G49

G51

G53

G55

G57

H23

J23

K23

K57

L22

M23

M57

P57

E63

U57

W57

A59

E20

AC22

AE22

AE23

B59

AH26

AJ31

AJ33

AJ37

AN33

AP43

AR48

AY35

AY40

AY44

AY50

L62

N63

L63

F60

C59

D63

P62

U0500

AE7

AD10

AD8

AH13

J13

AB8

AG19

AG20

AC20

K18

M20

V21

Y20

AE8

AF22

AG16

AG17

H11

H15

J11

N8

P9

K14

K16

V8

W9

A20

AA21

W21

AE9

AF9

AG13

AG14

AG8

J17

J18

K19

R21

T21

AH10

AH14

K9

L10

M9

AG10

B11

T9

U8

Y8

AA9

AC9

AE20

AE21

AH11

J15

B18

dvt1

8 OF 120

8 OF 82

8.0.0

051-1573

6 8

15 16 17 55 68

18

8

10 44 68

11 14 68

8

11 68

68

11 68

11 17 63

11

11 12

11 68

11 14

11 68

11

11 68

11 40 68

68

11 12

11 68

10 68

8

10 44 68

6 8

15 16 17 55 68

11 68

8

11 68

18

11 68

12 13 68

11 68

73

5

OUT

SYM 14 OF 19

VSS

SYM 15 OF 19

VSS

SYM 16 OF 19

VSS

VSS_SENSE

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

201

MF

1/20W

100

5%

PLACE_NEAR=U0500.E62:50.8mm

55 73

BGA

CRITICAL

OMIT_TABLE

BROADWELL-ULT

2C+GT2

OMIT_TABLE

CRITICAL

BGA

BROADWELL-ULT

2C+GT2

OMIT_TABLE

BGA

BROADWELL-ULT

2C+GT2

CRITICAL

BOM_COST_GROUP=CPU

CPU & PCH Grounds

SYNC_MASTER=J41

SYNC_DATE=10/23/2012

CPU_VCCSENSE_N

R0960

1

2

U0500

A11

A14

A18

A24

A28

A32

A36

A40

A44

A48

A52

A56

AA1

AA58

AB10

AB20

AB22

AB7

AC61

AD21

AD3

AD63

AE10

AE5

AE58

AF11

AF12

AF14

AF15

AF17

AF18

AG1

AG11

AG21

AG23

AG60

AG61

AG62

AG63

AH17

AH19

AH20

AH22

AH24

AH28

AH30

AH32

AH34

AH36

AH38

AH40

AH42

AH44

AH49

AH51

AH53

AH55

AH57

AJ13

AJ14

AJ23

AJ25

AJ27

AJ29

AJ35

AJ39

AJ41

AJ43

AJ45

AJ47

AJ50

AJ52

AJ54

AJ56

AJ58

AJ60

AJ63

AK23

AK3

AK52

AL10

AL13

AL17

AL20

AL22

AL23

AL26

AL29

AL31

AL33

AL36

AL39

AL40

AL45

AL46

AL51

AL52

AL54

AL57

AL60

AL61

AM1

AM17

AM23

AM31

AM52

AN17

AN23

AN31

AN32

AN35

AN36

AN39

AN40

AN42

AN43

AN45

AN46

AN48

AN49

AN51

AN52

AN60

AN63

AN7

AP10

AP17

AP20

U0500

AP22

AP23

AP26

AP29

AP3

AP31

AP38

AP39

AP48

AP52

AP54

AP57

AR11

AR15

AR17

AR23

AR31

AR33

AR39

AR43

AR49

AR5

AR52

AT13

AT35

AT37

AT40

AT42

AT43

AT46

AT49

AT61

AT62

AT63

AU1

AU16

AU18

AU20

AU22

AU24

AU26

AU28

AU30

AU33

AU51

AU53

AU55

AU57

AU59

AV14

AV16

AV20

AV24

AV28

AV33

AV34

AV36

AV39

AV41

AV43

AV46

AV49

AV51

AV55

AV59

AV8

AW16

AW24

AW33

AW35

AW37

AW4

AW40

AW42

AW44

AW47

AW50

AW51

AW59

AW60

AY11

AY16

AY18

AY22

AY24

AY26

AY30

AY33

AY4

AY51

AY53

AY57

AY59

AY6

B20

B24

B26

B28

B32

B36

B4

B40

B44

B48

B52

B56

B60

C11

C14

C18

C20

C25

C27

C38

C39

C57

D12

D14

D18

D2

D21

D23

D25

D26

D27

D29

D30

D31

U0500

AH16

AH46

D33

D34

D35

D37

D38

D39

D41

D42

D43

D45

D46

D47

D49

D5

D50

D51

D53

D54

D55

D57

D59

D62

D8

E11

E17

F20

F26

F30

F34

F38

F42

F46

F50

F54

F58

F61

G18

G22

G3

G5

G6

G8

H13

H17

H57

J10

J22

J59

J63

K1

K12

L13

L15

L17

L18

L20

L58

L61

L7

M22

N10

N3

P59

P63

R10

R22

R8

E62

T1

T58

U20

U22

U61

U9

V10

V23

V3

V58

V7

W20

W22

Y10

Y59

Y63

9 OF 82

9 OF 120

8.0.0

051-1573

dvt1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Added 2 extra 2.2uF per Harris Beach v0.9 schematic

Apple implementation : 18x 22uF 0603 stuff, 80x 22uF 0603 nostuff

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff

CPU VCC Decoupling

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 0.9 unless stated otherwise

CPU VDDQ DECOUPLING

Apple implementation : 2x 2.2uF 0402, 6x 10uF 0402

1x Bulk nostuff, Harris Beach has 2x nostuff

Intel recommendation (Table 5-4): 2x 2.2uF 0402, 6x 10uF 0603

CPU VCC Decoupling

NOTE: 38X capacitors are STUFFED and have been changed to 12pF for Noise Floor Reasons (Radar # 17754026).

OMIT_TABLE

4V

X6S

0402

20%

10UF

CRITICAL

6.3V

CERM-X5R

0402-1

OMIT_TABLE

20%

10UF

OMIT_TABLE

0402-1

20%

6.3V

10UF

CERM-X5R

0402-1

10UF

CERM-X5R

20%

6.3V

OMIT_TABLE

10UF

CERM-X5R

0402-1

20%

6.3V

OMIT_TABLE

10UF

CERM-X5R

0402-1

20%

6.3V

OMIT_TABLE

10UF

20%

6.3V

CERM-X5R

0402-1

OMIT_TABLE

6.3V

20%

402-LF

CERM

2.2UF 2.2UF

6.3V

20%

402-LF

CERM

6.3V

402-LF

20%

CERM

2.2UF

402-LF

CERM

20%

6.3V

2.2UF

2V

20%

CASE-B2-SM

TANT

270UF

2V

20%

CASE-B2-SM

TANT

270UF

NO STUFF

CRITICAL

0402

20%

10UF

X6S

4V

2%

12PF

CRITICAL

50V

0402

C0G-CERM

0402

NO STUFF

4V

10UF

X6S

20%

CRITICAL

OMIT_TABLE

10UF

20%

CRITICAL

0402

X6S

4V 4V

X6S

20%

0402

CRITICAL

10UF

OMIT_TABLE

CRITICAL

NO STUFF

0402

X6S

4V

10UF

20%

X6S

0402

4V

20%

10UF

NO STUFF

CRITICAL CRITICAL

0402

50V

12PF

C0G-CERM

2%

10UF

4V

20%

0402

X6S

CRITICAL

OMIT_TABLE

50V

C0G-CERM

12PF

CRITICAL

2%

0402

OMIT_TABLE

0402

CRITICAL

10UF

4V

20%

X6S

20%

OMIT_TABLE

CRITICAL

10UF

0402

X6S

4V

OMIT_TABLE

CRITICAL

10UF

X6S

0402

20%

4V

C0G-CERM

50V

12PF

0402

2%

CRITICAL

10UF

X6S

CRITICAL

4V

20%

0402

NO STUFF

C0G-CERM

12PF

CRITICAL

50V

2%

0402

CRITICAL

NO STUFF

4V

20%

0402

X6S

10UF

0402

CRITICAL

4V

20%

X6S

10UF

NO STUFF

CRITICAL

NO STUFF

0402

4V

10UF

X6S

20%

CRITICAL

C0G-CERM

0402

12PF

50V

2%

OMIT_TABLE

20%

CRITICAL

10UF

0402

4V

X6S

10UF

CRITICAL

0402

NO STUFF

X6S

20%

4V

10UF

20%

4V

X6S

0402

NO STUFF

CRITICAL

10UF

20%

CRITICAL

4V

X6S

0402

OMIT_TABLE

C0G-CERM

50V

12PF

2%

CRITICAL

0402

10UF

4V

X6S

0402

CRITICAL

20%

NO STUFF

CRITICAL

10UF

NO STUFF

0402

X6S

4V

20%

CRITICAL

12PF

50V

2%

C0G-CERM

04020402

50V

2%

C0G-CERM

12PF

CRITICAL

C0G-CERM

0402

CRITICAL

50V

12PF

2%2%

12PF

0402

CRITICAL

50V

C0G-CERM

10UF

NO STUFF

X6S

4V

20%

0402

CRITICAL

12PF

CRITICAL

50V

0402

C0G-CERM

2%

10UF

NO STUFF

CRITICAL

4V

0402

X6S

20%

CRITICAL

C0G-CERM

50V

2%

12PF

0402

CRITICAL

10UF

NO STUFF

4V

20%

0402

X6S

CRITICAL

0402

12PF

50V

2%

C0G-CERM

2%

0402

50V

12PF

C0G-CERM

0402

12PF

50V

2%

C0G-CERM

0402

50V

2%

12PF12PF

2%

0402

50V

C0G-CERM

20%

CRITICAL

10UF

4V

X6S

0402

OMIT_TABLE

0402

C0G-CERM

50V

12PF

2%

X6S

0402

NO STUFF

4V

20%

10UF

NO STUFF

10UF

20%

X6S

0402

4V

NO STUFF

4V

0402

X6S

10UF

20%

50V

12PF

C0G-CERM

2%

0402

10UF

NO STUFF

0402

4V

X6S

20%

0402

C0G-CERM

12PF

50V

2%

0402

NO STUFF

20%

4V

10UF

X6S

12PF

0402

50V

2%

C0G-CERM

0402

50V

2%

C0G-CERM

12PF

50V

2%

C0G-CERM

0402

20%

10UF

0402

X6S

NO STUFF

4V

X6S

0402

4V

10UF

NO STUFF

20%

X6S

0402

10UF

4V

NO STUFF

20%

NO STUFF

4V

20%

X6S

0402

10UF

4V

20%

0402

X6S

10UF

NO STUFF

CRITICAL

20%

OMIT_TABLE

4V

X6S

0402

10UF

NO STUFF

10UF

20%

4V

0402

X6SX6S

0402

4V

10UF

20%

NO STUFF

12PF

50V

0402

2%

C0G-CERM

X6S

10UF

4V

20%

0402

NO STUFF

0402

X6S

4V

20%

10UF

CRITICAL

OMIT_TABLE

0402

10UF

NO STUFF

4V

20%

X6S

NO STUFF

4V

0402

20%

X6S

10UF

50V

12PF

2%

C0G-CERM

0402

NO STUFF

4V

10UF

20%

X6S

0402

NO STUFF

20%

4V

0402

X6S

10UF

C0G-CERM

2%

12PF

50V

0402

10UF

4V

X6S

0402

20%

CRITICAL

OMIT_TABLE

C0G-CERM

12PF

50V

0402

2%

NO STUFF

10UF

0402

4V

20%

X6S

50V

C0G-CERM

12PF

0402

2%

C0G-CERM

0402

50V

12PF

2%

4V

NO STUFF

0402

20%

X6S

10UF

50V

0402

2%

C0G-CERM

12PF

4V

NO STUFF

0402

10UF

20%

X6S

NO STUFF

10UF

0402

4V

20%

X6S

12PF

0402

50V

C0G-CERM

2%

NO STUFF

10UF

20%

4V

X6S

0402

C0G-CERM

12PF

0402

50V

2%

NO STUFF

4V

20%

0402

X6S

10UF

NO STUFF

4V

20%

0402

X6S

10UF

12PF

50V

0402

2%

C0G-CERM

4V

20%

0402

X6S

10UF

NO STUFF

4V

20%

0402

X6S

10UF

NO STUFF

POLY-TANT

2.5V

20%

SM

470UF-0.0045OHM

CRITICAL

C0G-CERM

12PF

CRITICAL

0402

50V

2% 2%

C0G-CERM

12PF

50V

0402

CRITICAL CRITICAL

OMIT_TABLE

0402

4V

X6S

20%

10UF

CRITICAL

12PF

2%

50V

0402

C0G-CERM

12PF

50V

CRITICAL

0402

2%

C0G-CERM

4V

20%

10UF

CRITICAL

OMIT_TABLE

0402

X6S

NO STUFF

X6S

4V

20%

10UF

CRITICAL

0402

OMIT_TABLE

0402

X6S

4V

20%

10UF

CRITICAL

OMIT_TABLE

20%

10UF

4V

X6S

CRITICAL

0402

NO STUFF

CRITICAL

4V

20%

0402

X6S

10UF

OMIT_TABLE

CRITICAL

10UF

X6S

0402

20%

4V

5%

NP0-C0G

12PF

0201

25V

NP0-C0G

12PF

0201

5%

25V

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

SYNC_DATE=10/23/2012

CPU Decoupling

C1000,C1004,C1008,C1012,C1018,C1019,C1020,C1022,C1026,C1034,C1065,C1070,C1074,C105A,C105C,C105D,C104F,C105F

CAP,CER,10UF,20%,4V,X6S,HRZTL,0402

138S0942

18

CRITICAL

138S0801

6

CAP,CER,10UF,20%,6.3V,HRZTL,0402

CRITICAL

C1050,C1051,C1052,C1053,C1054,C1055

=PPVCC_S0_CPU

=PPVMEMIO_S0_CPU

C1000

1

2

C1050

1

2

C1051

1

2

C1052

1

2

C1053

1

2

C1054

1

2

C1055

1

2

C1040

1

2

C1041

1

2

C1042

1

2

C1043

1

2

C1060

1

2

C1061

1

2

C1001

1

2

C1002

1

2

C1003

1

2

C1004

1

2

C1008

1

2

C1009

1

2

C1010

1

2

C1011

1

2

C1012

1

2

C1014

1

2

C1018

1

2

C1019

1

2

C1020

1

2

C1021

1

2

C1084

1

2

C1083

1

2

C1082

1

2

C1081

1

2

C1077

1

2

C1075

1

2

C1074

1

2

C1073

1

2

C1072

1

2

C1070

1

2

C1097

1

2

C1096

1

2

C1095

1

2

C1094

1

2

C1093

1

2

C1092

1

2

C1091

1

2

C1090

1

2

C1089

1

2

C1088

1

2

C1087

1

2

C1086

1

2

C1085

1

2

C1038

1

2

C1037

1

2

C1036

1

2

C1035

1

2

C1034

1

2

C1033

1

2

C1032

1

2

C1029

1

2

C109A

1

2

C1099

1

2

C1098

1

2

C107B

1

2

C107A

1

2

C1069

1

2

C1068

1

2

C108F

1

2

C1067

1

2

C108E

1

2

C1066

1

2

C108D

1

2

C108C

1

2

C1065

1

2

C1028

1

2

C1027

1

2

C1049

1

2

C1048

1

2

C1026

1

2

C1047

1

2

C1025

1

2

C1024

1

2

C1046

1

2

C1045

1

2

C1023

1

2

C1022

1

2

C1044

1

2

C1039

1

2

C1064

1

2

C108B

1

2

C1063

1

2

C108A

1

2

C1062

1

2

C109F

1

2

C109E

1

2

C1059

1

2

C1058

1

2

C109D

1

2

C1057

1

2

C109C

1

2

C1056

1

2

C109B

1

2

C1031

1

23

C1030

1

2

C104E

1

2

C104F

1

2

C106D

1

2

C106E

1

2

C105A

1

2

C105B

1

2

C105C

1

2

C105D

1

2

C105E

1

2

C105F

1

2

C1079

1

2

C1080

1

2

10 OF 120

dvt1

051-1573

8.0.0

10 OF 82

8

44 68

8

68

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

PCH VCCACLKPLL FILTER/BYPASS

PCH VCCCLK FILTER/BYPASS

(PCH 3.3V SUSPEND RTC PWR)

Wildcat Point-LP current estimates from Wildcat Point-LP PCH EDS, Doc# 515621, Rev. 0.9

as well as from clarification email, from Srini, dated 9/10/2012 2:11pm.

PCH VCCSUSHDA BYPASS

(PCH 3.3V/1.8V SDIO PWR)

(PCH 3.3V/1.5V HDA PWR)

(PCH 3.3V SUSPEND PWR)

(PCH 3.3V DSW PWR)

(PCH 1.05V ACLK PLL PWR)

PCH VCCIO BYPASS

(PCH 1.05V USB2 PWR)

(PCH 3.3V THERMAL PWR)

PCH VCC3_3 BYPASS

PCH VCCCLK BYPASS

(PCH 1.05V CLK PWR)

(PCH 1.05V OPI PLL PWR)

(PCH 1.05V ME CORE PWR)

PCH VCCASW BYPASS

(PCH 1.05V CORE PWR)

PCH VCC BYPASS

PCH VCCSUS3_3 BYPASS

PCH VCCDSW3_3 BYPASS

(PCH 1.05V SATA3 PLL PWR)

41mA Max

83mA Max 42mA Max

??mA Max

31mA Max

57mA Max

??mA Max

(PCH 1.05V PCIe/SATA/USB3 PWR)

PCH VCCHSIO BYPASS

PCH VCCSATA3PLL FILTER/BYPASS

(PCH 3.3V GPIO/LPC PWR)

PCH VCC3_3 BYPASS

PCH OPI VCCAPLL FILTER/BYPASS

PCH VCCSDIO BYPASS

PCH VCCSUS3_3 BYPASS

(PCH 3.3V SPI PWR)

(PCH 1.05V VCCCLK PWR)

(PCH 1.05V USB3 PLL PWR)

PCH VCCUSB3PLL FILTER/BYPASS

PCH VCCSPI BYPASS

NO STUFF

0.1UF

CERM

402

20%

10V

BYPASS=U0500.Y8::6.35mm

NO STUFF

CRITICAL

2.2UH-240MA-0.221OHM

0603

0

MF-LF

402

5%

1/16W

X6S

0805

20%

BYPASS=U0500.B18::12.7mm

4V

47UF

X6S

0805

20%

BYPASS=U0500.B11::12.7mm

47UF

4V

NO STUFF

47UF

CERM-X5R

0805-1

20%

4V

BYPASS=U0500.B11::12.7mm

BYPASS=U0500.AA21::12.7mm

NO STUFF

47UF

CERM-X5R

0805-1

20%

4V

BYPASS=U0500.AA21::12.7mm

NO STUFF

47UF

CERM-X5R

0805-1

20%

4V

X6S

0805

20%

BYPASS=U0500.J18::12.7mm

4V

47UF

X6S

0805

20%

BYPASS=U0500.J18::12.7mm

47UF

4V

X6S

0805

20%

BYPASS=U0500.A20::12.7mm

47UF

4V

X6S

0805

20%

BYPASS=U0500.A20::12.7mm

47UF

4V

NO STUFF

BYPASS=U0500.AH10::6.35mm

1UF

CERM

402

10%

6.3V

BYPASS=U0500.AH14::6.35mm

1UF

CERM

402

10%

6.3V

BYPASS=U0500.K14::6.35mm

0.1UF

CERM

402

20%

10V

1UF

CERM

402

10%

6.3V

BYPASS=U0500.AH11::6.35mm

BYPASS=U0500.AG16::6.35mm

1UF

CERM

402

10%

6.3V

1UF

CERM

10%

6.3V

402

BYPASS=U0500.L10::6.35mm

OMIT_TABLE

BYPASS=U0500.M9::6.35mm

10UF

CERM-X5R

20%

6.3V

0402-1

BYPASS=U0500.J17::6.35mm

1UF

CERM

402

10%

6.3V

BYPASS=U0500.J11::12.7mm

10UF

X5R

603

20%

6.3V

BYPASS=U0500.AE9::12.7mm

NO STUFF

22UF

X5R-CERM-1

603

20%

6.3V

BYPASS=U0500.J11::6.35mm

1UF

CERM

402

10%

6.3V

BYPASS=U0500.AE8::6.35mm

1UF

CERM

402

10%

6.3V

BYPASS=U0500.AE9::6.35mm

1UF

CERM

402

10%

6.3V

BYPASS=U0500.R21::6.35mm

1UF

CERM

402

10%

6.3V

X5R-CERM-1

603

20%

6.3V

BYPASS=U0500.AC9::12.7mm

22UF

BYPASS=U0500.V8::12.7mm

22UF

X5R-CERM-1

603

20%

6.3V

BYPASS=U0500.U8::6.35mm

1UF

CERM

402

10%

6.3V

1UF

CERM

10%

6.3V

BYPASS=U0500.K9::6.35mm

402

1UF

BYPASS=U0500.J18::6.35mm

X5R

402

10%

10V

CRITICAL

2.2UH-240MA-0.221OHM

0603

BYPASS=U0500.B18::6.35mm

1UF

X5R

402

10%

10V

CRITICAL

0603

2.2UH-240MA-0.221OHM

BYPASS=U0500.B11::6.35mm

X5R

402

10%

10V

1UF

CRITICAL

2.2UH-240MA-0.221OHM

0603

MF-LF

402

5%

1/16W

0

BYPASS=U0500.A20::6.35mm

1UF

X5R

402

10%

10V

0603

CRITICAL

2.2UH-240MA-0.221OHM

0

MF-LF

402

5%

1/16W

BYPASS=U0500.AA21::6.35mm

10%

1UF

X5R

402

10V

CRITICAL138S0801

1

CAP,CER,10UF,20%,6.3V,HRZTL,0402

C1262

SYNC_DATE=10/23/2012

PCH Decoupling

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

=PP1V05_S0SW_PCH_VCCHSIO

=PP3V3_SUS_PCH_VCC_SPI

=PP3V3_S5_PCH_VCCDSW

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_PCH_VCCACLKPLL_R

=PP1V05_S0SW_PCH_VCCPLL_HSIO

VOLTAGE=1.05V

PP1V05_S0_PCH_VCC_ICC

MIN_NECK_WIDTH=0.075 MM

MIN_LINE_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.075 MM

PP1V05_S0SW_PCH_VCCSATA3PLL

PP1V05_S0SW_PCH_VCCUSB3PLL

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.075 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.075 MM

PP1V05_S0_PCH_VCCACLKPLL

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.075 MM

PP1V05_S0_PCH_VCCAPLL_OPI

=PP3V3R1V8_S0_PCH_VCCSDIO

=PP1V05_S0_PCH_PLLFILTERS

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.2 MM

PP1V05_S0_PCH_VCC_ICC_R

=PP1V05_S0_PCH_VCC

=PP1V05_S0M_PCH_VCCASW

=PP1V05_S0_PCH_VCCCLK

=PP3V3_S0_PCH_VCCTS

=PP3V3_S0_PCH_VCC3_3_GPIO =PP1V05_S0_PCH_VCCIO_USB2

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3R1V5_S0SW_PCH_VCCSUSHDA

=PP3V3_SUS_PCH_VCCSUS_RTC

C1210

1

2

C1206

1

2

C1202

1

2

C1200

1

2

C1214

1

2

C1264

1

2

C1261

1

2

C1262

1

2

C1266

1

2

C1255

1

2

C1250

1

2

C1256

1

2

C1257

1

2

C1251

1

2

C1267

1

2

C1204

1

2

C1212

1

2

C1208

1

2

C1260

1

2

C1277

1

2

L1275

12

C1297

1

2

L1295

12

C1292

1

2

L1290

12

R1275

12

C1272

1

2

L1270

12

R1270

12

C1282

1

2

L1280

12

R1280

12

C1295

1

2

C1290

1

2

C1291

1

2

C1280

1

2

C1281

1

2

C1275

1

2

C1276

1

2

C1270

1

2

C1271

1

2

11 OF 82

12 OF 120

8.0.0

051-1573

dvt1

8

68

8

14 68

8

68

8

12

8

14

8

12

8

40 68

68

8

68

8

68

8

68

8

68

8

68

8

68

8

68

8

17 63

8

68

IN IN

IN

OUT

BI

AUDIO

SYM 5 OF 19

SATA

JTAG

RTC

RSVD

HDA_DOCK_EN*/I2S1_TXD

HDA_BCLK/I2S0_SCLK

RTCX1

RTCX2

RTCRST*

INTVRMEN

INTRUDER*

SRTCRST*

HDA_RST*/I2S_MCLK

HDA_SYNC/I2S0_SFRM

HDA_SDI0/I2S0_RXD

HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

HDA_DOCK_RST*/I2S1_SFRM

I2S1_SCLK

SATA_RN0/PERN6_L3

SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2

SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1

SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0

SATA_TP3/PETP6_L0

SATA0GP/GPIO34

SATA1GP/GPIO35

SATA2GP/GPIO36

SATA3GP/GPIO37

SATA_IREF

PCH_TRST*

PCH_TDI

PCH_TCK

PCH_TDO

RSVD

PCH_TMS

JTAGX

RSVD

RSVD SATALED*

SATA_RCOMP

SYM 6 OF 19

CLOCK SIGNALS

CLKOUT_LPC_1

CLKOUT_LPC_0

CLKOUT_ITPXDP_N

CLKOUT_ITPXDP_P

PCIECLKRQ5*/GPIO23

PCIECLKRQ4*/GPIO22

CLKOUT_PCIE_N5

CLKOUT_PCIE_P5

PCIECLKRQ3*/GPIO21

CLKOUT_PCIE_P4

CLKOUT_PCIE_N4

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE_P3

CLKOUT_PCIE_N3

PCIECLKRQ1*/GPIO19

CLKOUT_PCIE_P2

CLKOUT_PCIE_N2

PCIECLKRQ0*/GPIO18

CLKOUT_PCIE_P1

CLKOUT_PCIE_N1

CLKOUT_PCIE_N0

XTAL24_OUT

XTAL24_IN

CLKOUT_PCIE_P0

TESTLOW

DIFFCLK_BIASREF

RSVD

OUT

IN

NC

IN

OUT

IN

OUT

IN

NC

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC

OUT

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPD-PLTRST#)

SATA Port assignments:

SSD Lane 3

SSD Lane 1

SSD Lane 2

(IPU)

(IPD)

SSD Lane 0

PCIe Port assignments:

(IPD-PWROK)

(IPD)

Secondary HDD/SSD

Unused

Primary HDD/SSD

(IPD-PLTRST#)

(IPU)

Reserved: ODD

16 73

201

10K

5% MF

1/20W

201

5% MF

100K

1/20W

16

1/20W

100K

201

MF5%

16 73

CRITICAL

2C+GT2

BROADWELL-ULT

OMIT_TABLE

BGA

2C+GT2

OMIT_TABLE

BROADWELL-ULT

BGA

CRITICAL

49 75

PLACE_NEAR=U0500.AU8:1.27mm

1/20W

5% MF

33

201

1/20W

5%

33

MF

PLACE_NEAR=U0500.AV11:1.27mm

201

49 71 75

MF

201

5%

1/20W

33

PLACE_NEAR=U0500.AW8:1.27mm

17 75

330K

1/20W

5%

201

MF

1/20W

5%

201

MF

1M

1UF

402

10%

10V

X5R

20K

MF

201

5%

1/20W

X5R

402

1UF

10%

10V

MF

1/20W

20K

201

5%

16

3.01K

PLACE_NEAR=U0500.C12:2.54mm

MF

1/20W

1%

201

32 71 81

12 66

66 71 81

49 75

12 33

34 71 81

25 71 81

12 25

32 71 81

12 32

MF

201

1%

1/20W

3.01K

PLACE_NEAR=U0500.C26:2.54mm

17 75

10K

MF5%

201

1/20W

5%

10K

1/20W

201

MF

1/20W

5%

10K

MF

201

5%

10K

1/20W

MF

201

17 75

17

MF5%

1/20W

33

201

PLACE_NEAR=U0500.AU11:1.27mm

1/20W

5%

100K

201

MF

201

5%

1/20W

MF

100K

5%

201

100K

1/20W

MF

1/20W

5%

201

20K

MF

BOM_COST_GROUP=CPU

SYNC_MASTER=J41

SYNC_DATE=12/17/2012

PCH Audio/JTAG/SATA/CLK

PCH_CLK24M_XTALIN

PCH_DIFFCLK_BIASREF

FW_CLKREQ_L

AP_CLKREQ_L

PCIE_CLK100M_AP_P

TP_ITPXDP_CLK100MP

TP_ITPXDP_CLK100MN

PCH_INTVRMEN

TP_PCH_I2S1_SCLK

XDP_PCH_TDO

PCH_JTAGX

TP_PCH_I2S1_SFRM

HDA_RST_L

HDA_BIT_CLK

HDA_SYNC

HDA_SDOUT

=PPVRTC_G3_PCH

PCH_SATALED_L

XDP_PCH_TMS

XDP_PCH_TCK

XDP_PCH_TDI

XDP_PCH_TRST_L

PCIE_SSD_R2D_C_P<0>

PCIE_SSD_D2R_N<0>

PCIE_SSD_R2D_C_N<1>

PCIE_SSD_D2R_P<1>

PCIE_SSD_D2R_N<1>

PCIE_SSD_R2D_C_P<2>

PCIE_SSD_R2D_C_N<2>

PCIE_SSD_D2R_N<2>

PCIE_SSD_R2D_C_P<3>

PCIE_SSD_R2D_C_N<3>

PCIE_SSD_D2R_P<3>

PCIE_SSD_D2R_N<3>

HDA_SDOUT_R

TP_HDA_SDIN1

HDA_SYNC_R

HDA_RST_R_L

PCH_SRTCRST_L

PCH_INTRUDER_L

RTC_RESET_L

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX1

HDA_BIT_CLK_R

TP_PCH_I2S1_TXD

PCIE_SSD_D2R_P<0>

PCIE_SSD_R2D_C_N<0>

PP1V05_S0SW_PCH_VCCSATA3PLL

PCH_TESTLOW_C34

TP_PCIE_CLK100M_ENETSDP

PCH_CLK24M_XTALOUT

TP_PCIE_CLK100M_ENETSDN

PCIE_CLK100M_CAMERA_N

PCIE_CLK100M_CAMERA_P

ENETSD_CLKREQ_L

TP_PCIE_CLK100M_FWN

TP_PCIE_CLK100M_FWP

PCIE_CLK100M_TBT_N

PCIE_CLK100M_TBT_P

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

TBT_CLKREQ_L

SSD_CLKREQ_L

LPC_CLK24M_SMC_R

PCH_TESTLOW_AK8

PCIE_SSD_D2R_P<2>

PCIE_SSD_R2D_C_P<1>

XDP_SSD_PCIE3_SEL_L

XDP_SSD_PCIE0_SEL_L

XDP_SSD_PCIE1_SEL_L

PCH_TESTLOW_AL8

PCH_TESTLOW_C35

HDA_SDIN0

TP_LPC_CLK24M_LPCPLUS

PP1V05_S0_PCH_VCCACLKPLL

PCH_SATA_RCOMP

XDP_SSD_PCIE2_SEL_L

ENETSD_CLKREQ_L

PCH_SATALED_L

PCIE_CLK100M_AP_N

CAMERA_CLKREQ_L

AP_CLKREQ_L

FW_CLKREQ_L

TBT_CLKREQ_L

=PP3V3_S0_PCH_GPIO

SSD_CLKREQ_L

R1313

12

R1312

12

R1311

12

R1310

12

R1302

1

2

R1301

1

2

C1300

1

2

R1300

1

2

C1303

1

2

R1303

1

2

R1370

1

2

R1380

1

2

R1390

12

R1391

12

R1392

12

R1393

12

R1341

12

R1344

12

R1340

12

R1342

12

R1345

12

R1375

12

R1343

12

U0500

AW8

AW10

AV10

AU8

AY10

AU12

AU11

AV11

AY8

AU6

AV7

AE63

AE62

AD61

AE61

AD62

AU62

AC4

AL11

AV2

K10

L11

AU7

AW5

AY5

V1

U1

V6

AC1

A12

C12

J5

J8

J6

F5

H5

H8

H6

E5

B15

A17

B14

C17

A15

B17

C15

D17

U3

AV6

U0500

B35

A35

AN15

AP15

C43

B41

C41

B38

A39

B37

C42

A41

B42

C37

B39

A37

C26

U2

Y5

AD1

N1

U5

T2

K21

M21

AK8

AL8

C34

C35

A25

B25

13 OF 120

8.0.0

051-1573

dvt1

12 OF 82

12

69

75

69

8

13 68

12

17 75

69

75

69

8

11

69

12 71

69

8

11

75

12 71

12

12 33

12 66

12

12 25

13 15 18 26 65 68

12 32

IN

OUT

IN

OUT

SYSTEM POWER MANAGEMENT

SYM 8 OF 19

SLP_WLAN*/GPIO29

SLP_S0*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUSWARN*/SUSPWRDNACK/GPIO30

RSMRST*

PCH_PWROK

APWROK

SYS_RESET*

SUSACK*

PLTRST*

SYS_PWROK

DPWROK

DSWVRMEN

CLKRUN*/GPIO32

WAKE*

SLP_S5*/GPIO63

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

SLP_LAN*

SIDEBAND

eDP

DISPLAY

PCI

SYM 9 OF 19

GPIO53

GPIO51

GPIO54

GPIO52

GPIO55

PME*

PIRQC*/GPIO79

PIRQD*/GPIO80

PIRQA*/GPIO77

PIRQB*/GPIO78

EDP_BKLEN

EDP_BKLCTL

EDP_HPD

DDPC_HPD

DDPC_AUXP

DDPB_AUXP

DDPB_HPD

DDPB_AUXN

DDPC_AUXN

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPB_CTRLCLK

DDPB_CTRLDATA

EDP_VDDEN

OUT

IN

OUT

BI

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

NC

08

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

(IPD-PLTRST#)

(IPU)

(IPD-PLTRST#)

(IPU)

R1400 kept for debug purposes.

SLP_S0# Isolation

(IPD-DeepSx)

U1420 ensures signal will only be high in S0.

SLP_S0# can be driven high outside of S0

64 75

13 18 38

40

CRITICAL

OMIT_TABLE

BGA

BROADWELL-ULT

2C+GT2

BGA

OMIT_TABLE

CRITICAL

BROADWELL-ULT

2C+GT2

13 32

15 16 18

17

17 75

16 17 38 75

17 38 71 75

13 64

13 17 18 38 64 66 71

13 18 31 37 38 64 66

13 38 64

39

38 71

13 38 71

13 31 33 75

100K

MF

1/20W

201

5%

38 75

330K

MF

201

5%

1/20W

13 65

65 71

13 65

25 77

69

25 77

30

69

30

25

69

65

100K

MF 201

1/20W

5%

100K

MF

1/20W

2015%

MF 2015%

1/20W

100K

5%

100K

201

1/20W

MF

5%

1/20W

MF

10K

201

NO STUFF

MF

1/20W

0201

0

5%

MF

100K

1/20W

2015%

13 26

13 38

13 71

13 69

13 71

13 27 38

10K

MF

1/20W

201

5%

MF

1/20W

201

5%

10K

100K

MF5% 201

1/20W

100K

MF

1/20W

2015%

100K

MF

1/20W

2015%

201

100K

MF

1/20W

5%

201

MF

100K

1/20W

5%

38 39

13 64

1K

MF

1/20W

201

5%

10K

MF

1/20W

201

5%

100K

MF

201

5%

1/20W

100K

MF

1/20W

201

5%

201

100K

MF

1/20W

5%

201

100K

MF

1/20W

5%

201

MF

100K

1/20W

5%

13 16 38 75

SOT891

74LVC1G08

CRITICAL

10%

10V

0.1UF

0201

X5R-CERM

SYNC_DATE=02/21/2013SYNC_MASTER=J41

PCH PM/PCI/GFX

BOM_COST_GROUP=CPU

ENET_LOW_PWR

DP_AUXCH_ISOL_L

ODD_PWR_EN_L

SSD_BOOT

PM_DSW_PWRGD

PM_SLP_S4_L

PM_SLP_S3_L

=PP3V3_S5_PCH_GPIO

ENET_LOW_PWR

AUD_PWR_EN

SSD_BOOT

DP_TBTSNK0_AUXCH_C_P

=DP_TBTSNK1_AUXCH_C_N

AUD_IP_PERIPHERAL_DET

TBT_PWR_REQ_L

SMC_RUNTIME_SCI_L

EDP_BKLT_EN

EDP_BKLT_PWM

DP_INT_HPD

=DP_TBTSNK1_HPD

=DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK0_HPD

DP_TBTSNK0_AUXCH_C_N

=DP_TBTSNK1_DDC_CLK

=DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_DDC_CLK

DP_TBTSNK0_DDC_DATA

EDP_PANEL_PWR

PCIE_WAKE_L

TP_PCH_SLP_WLAN_L

PCH_PM_SLP_S0_L

PM_BATLOW_L

SMC_ADAPTER_EN

PM_PWRBTN_L

PCH_SUSWARN_L

PM_RSMRST_L

PM_PCH_PWROK

PM_PCH_APWROK

PM_SYSRST_L

PCH_SUSACK_L

PLT_RESET_L

PM_PCH_SYS_PWROK

PCH_DSWVRMEN

PM_CLKRUN_L

PM_SLP_S5_L

PM_CLK32K_SUSCLK_R

LPC_PWRDWN_L

TP_PM_SLP_A_L

PM_SLP_SUS_L

TP_PCH_SLP_LAN_L

=PP3V3_S0_PCH_GPIO

=PPVRTC_G3_PCH

PCIE_WAKE_L

PM_CLKRUN_L

DP_AUXCH_ISOL_L

PM_SLP_S0_L

PM_SLP_S4_L

PM_SLP_S3_L

AUD_IP_PERIPHERAL_DET

TP_PCI_PME_L

AUD_PWR_EN

PM_PWRBTN_L

PM_BATLOW_L

EDP_BKLT_EN

SMC_RUNTIME_SCI_L

ODD_PWR_EN_L

=PP3V3_S0_PCH_GPIO

PM_SLP_SUS_L

EDP_PANEL_PWR

TBT_PWR_REQ_L

PM_SLP_S0_L

PM_SLP_S5_L

AUD_IPHS_SWITCH_EN

R1400

1

2

R1451

1

2

R1450

1

2

R1446

12

R1445

12

R1442

12

R1443

12

R1441

12

R1440

12

R1455

12

R1410

12

R1447

12

R1448

12

R1449

12

R1431

12

R1430

12

R1405

12

R1452

12

R1460

12

R1461

12

R1462

12

R1464

12

R1463

12

U1420

2

1

3

6

4

C1420

1

2

U0500

AJ8

AB5

AN4

V5

AV5

AW7

AY7

AG7

AL7

AW6

AL5

AJ7AF3

AT4

AJ6

AP5

AP4

AM5

AG4

AK2

AE6

AV4

AG2

AC3

AJ5

U0500

C5

B5

B9

C9

C8

B6

A6

D9

D11

A8

B8

A9

D6

C6

R5

L1

L4

L3

U7

U6

P4

N4

N2

AD4

13 OF 82

dvt1

051-1573

8.0.0

14 OF 120

5

13 32

15 68

13 71

13 64

69

75

71

69

12 13 15 18 26 65 68

8

12 68

13 31 33 75

13 38 71

13 69

13 18 31 37 38 64 66

13 17 18 38 64 66 71

13 71

69

13 16 38 75

13 27 38

13 65

13 38

13 71

12 13 15 18 26 65 68

13 64

13 65

13 26

13 18 38

13 38 64

13 71

OUT

IN

OUT

IN

OUT

USB

PCI-E

SYM 11 OF 19

PCIE_RCOMP

PCIE_IREF

RSVD

PETP4

PETN4

PERP4

PERN4

PETP3

PETN3

PERP3

PERN3

PETP5_L3

PETN5_L3

PETP5_L2

PETN5_L2

PERP5_L2

PERN5_L2

PETP5_L1

PETN5_L1

PERP5_L1

PERN5_L1

USB2P7

USB2N7

PERP5_L3

PERN5_L3

PETP5_L0

PETN5_L0

PERP5_L0

PERN5_L0

OC1*/GPIO41

OC0*/GPIO40

OC2*/GPIO42

OC3*/GPIO43

RSVD

USBRBIAS*

USBRBIAS

USB2N0

USB2P0

USB2N1

USB2P1

USB2N2

USB2P2

USB2N3

USB2P3

USB2N4

USB2P4

USB2N5

USB2P5

USB2N6

USB2P6

PERN1/USB3RN3

PERN2/USB3RN4

PERP1/USB3RP3

PERP2/USB3RP4

PETN1/USB3TN3

PETN2/USB3TN4

PETP1/USB3TP3

PETP2/USB3TP4

USB3RN1

USB3RN2

USB3RP1

USB3RP2

USB3TN1

USB3TN2

USB3TP1

USB3TP2

SYM 7 OF 19

LPC

SMBUS

SPI

C-LINK

SPI_IO3

SPI_MISO

SPI_IO2

SPI_CS2*

SPI_MOSI

SPI_CS0*

SPI_CS1*

LFRAME*

LAD2

LAD3

LAD1

SPI_CLK

LAD0

SMBALERT*/GPIO11

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK_GPIO75

SML1ALERT*/PCHHOT*/GPIO73

SML1DATA/GPIO74

CL_CLK

CL_DATA

CL_RST*

BI

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC

OUT

IN

OUT

IN

OUT

IN

NC

BI

IN

BI

OUT

BI

OUT

BI

OUT

IN

BI

OUT

BI

OUT

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU/IPD)

Ext A (SS)

Ext B (SS)

SML1ALERT# pull-up not provided on this

(IPU/IPD)

Reserved: Camera

USB Port Assignments:

page, may be wire-ORed into other signals.

Otherwise, 100k pull-up to 3.3V SUS required.

Thunderbolt lane 1

Camera

(& Ethernet if combo)

Thunderbolt lane 3

Thunderbolt lane 2

PCIe Port Assignments:

Thunderbolt lane 0

Reserved: FireWire

AirPort

Ext A (LS/FS/HS)

Ext B (LS/FS/HS)

BT

IR

(IPU/IPD)

(IPU)

(IPD)

SD Card Reader

(IPU)

USB3 Port Assignments:

Unused

Trackpad

Reserved: SD (HS)

25 71 81

1/20W

5% 201MF

100K

1/20W

5% 201MF

100K

14 16

40

14 16

25 71 81

14 71

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

36 71 74

25 71 81

66 74

66 71 74

34 81

34 71 81

66 71 81

1/20W

1%

201

MF

3.01K

PLACE_NEAR=U0500.A27:2.54mm

66 71 74

35 71 74

25 71 81

35 71 74

1/20W

1%

201

MF

22.6

PLACE_NEAR=U0500.AJ10:2.54mm

69

25 71 81

69

31 74

66 74

25 71 81

35 74

38 71 75

1/20W

5% 201MF

33

1/20W

5% 201MF

33

25 71 81

1/20W

5% 201MF

33

1/20W

5% 201MF

33

1/20W

5% 201MF

33

47 75

41 75

25 71 81

41 75

41 71 75

47 75

25 71 81

14 47 75

1/20W

5% 201MF

100K

1/20W

5% 201MF

1K

1/20W

5% 201MF

100K

1/20W

5% 201MF

1K

1/20W

5% 201MF

100K

1/20W

5% 201MF

100K

BOM_COST_GROUP=CPU

PCH PCIe,USB,LPC,SPI,SMBus

SYNC_DATE=10/23/2012

SYNC_MASTER=J41

USB3_EXTB_R2D_C_P

USB3_EXTB_D2R_P

USB3_EXTA_D2R_N

USB3_EXTA_D2R_P

USB3_EXTA_R2D_C_P

USB3_EXTB_D2R_N

PCH_USB_RBIAS

USB_IR_N

USB_BT_N

TP_USB_SDN

TP_USB_SDP

=PP3V3_SUS_PCH_VCC_SPI

XDP_USB_EXTA_OC_L

LPC_AD<2>

LPC_FRAME_L

LPC_AD<0>

LPC_AD<3>

=PP3V3_SUS_PCH_GPIO

PCH_SMBALERT_L

TP_CLINK_RESET_L

TP_CLINK_DATA

TP_CLINK_CLK

SML_PCH_1_DATA

PCH_SML1ALERT_L

SML_PCH_1_CLK

SML_PCH_0_DATA

SML_PCH_0_CLK

WOL_EN

LPC_AD_R<0>

SPI_CLK_R

LPC_AD_R<1>

LPC_AD_R<3>

LPC_AD_R<2>

LPC_FRAME_R_L

TP_SPI_CS1_L

SPI_CS0_R_L

SPI_MOSI_R

TP_SPI_CS2_L

SPI_IO<2>

SPI_MISO

SPI_IO<3>

XDP_USB_EXTC_OC_L

XDP_USB_EXTD_OC_L

XDP_USB_EXTB_OC_L

WOL_EN

SPI_IO<2>

SPI_IO<3>

PCIE_CAMERA_R2D_C_P

PCIE_CAMERA_R2D_C_N

USB3RPCIE_SD_R2D_C_N

PCIE_CAMERA_D2R_P

USB_IR_P

USB_EXTB_P

USB_EXTB_N

USB_EXTA_P

USB_EXTA_N

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_N<3>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_P<2>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_N<3>

PCIE_AP_R2D_C_N

TP_PCIE_FW_D2RN

USB3RPCIE_SD_D2R_N

LPC_AD<1>

TP_PCIE_FW_D2RP

TP_PCIE_FW_R2D_CN

XDP_USB_EXTD_OC_L

PCH_SMBALERT_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTB_OC_L

XDP_USB_EXTA_OC_L

PCH_PCIE_RCOMP

USB3_EXTA_R2D_C_N

PCIE_TBT_D2R_P<3>

PP1V05_S0SW_PCH_VCCUSB3PLL

PCIE_CAMERA_D2R_N

USB3RPCIE_SD_R2D_C_P

USB3RPCIE_SD_D2R_P

TP_PCIE_FW_R2D_CP

TP_USB_CAMERAP

TP_USB_CAMERAN

TP_USB_5P

TP_USB_5N

SMBUS_PCH_DATA

SMBUS_PCH_CLK

USB3_EXTB_R2D_C_N

USB_TPAD_P

PCIE_AP_R2D_C_P

PCIE_AP_D2R_P

PCIE_AP_D2R_N

PCIE_TBT_R2D_C_P<3>

USB_BT_P

USB_TPAD_N

R1500

1

2

R1570

1

2

R1543

12

R1542

12

R1544

12

R1540

12

R1541

12

R1591

12

R1549

12

R1590

12

R1548

12

R1582

12

R1583

12

R1580

12

R1581

12

U0500

AL3

AT1

AH2

AV3B27

A27

G17

F15

G11

F13

F10

F8

H10

E6

F17

G15

F11

G13

E10

E8

G10

F6

C30

B31

C29

B29

C23

B23

B21

B22

C31

A31

B30

A29

C22

A23

C21

A21

AM10

AN10

E13

E15

AN8

AR7

AR8

AR10

AM15

AM13

AP11

AR13

AM8

AT7

AP8

AT10

AL15

AN13

AN11

AP13

G20

E18

H20

F18

C33

B33

B34

A33

AJ11

AJ10

U0500

AF2

AD2

AF4

AU14

AW12

AY12

AW11

AV12

AN2

AP2

AH1

AL2

AN1

AK1

AU4

AU3

AH3

AA3

Y7

Y4

AC2

Y6

AF1

AA4

AA2

14 OF 82

15 OF 120

8.0.0

051-1573

dvt1

74

69

8

11 68

14 16

68

14

69

14 16

14 71

14 47 75

69

14

75

8

11

69

IN

OUT

BI

OUT

IN

LPIO

GPIO

CPU/MISC

SYM 10 OF 19

SPKR/GPIO81

GPIO10

GPIO9

GPIO46

GPIO45

GPIO14

GPIO25

GPIO13

HSIOPC/GPIO71

GPIO50

GPIO49

GPIO48

GPIO44

GPIO47

GPIO59

GPIO58

GPIO57

GPIO56

GPIO26

GPIO27

GPIO28

GPIO24

GPIO16

GPIO17

GPIO15

LAN_PHY_PWR_CTRL/GPIO12

GPIO8

BMBUSY*/GPIO76

SDIO_D3/GPIO69

SDIO_D2/GPIO68

SDIO_D1/GPIO67

I2C0_SDA/GPIO4

UART1_TXD/GPIO1

UART1_CTS*/GPIO3

UART0_RTS*/GPIO93

UART0_CTS*/GPIO94

UART1_RXD/GPIO0

GSPI0_MOSI/GPIO86

GSPI1_CS*/GPIO87

GSPI1_CLK/GPIO88

GSPI0_CLK/GPIO84

GSPI0_MISO/GPIO85

GSPI0_CS*/GPIO83

RSVD

PCH_OPI_COMP

RCIN*/GPIO82

SERIRQ

GSPI1_MISO/GPIO89

GSPI_MOSI/GPIO90

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART1_RST*/GPIO2

I2C1_SDA/GPIO6

I2C0_SCL/GPIO5

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

SDIO_D0/GPIO66

SDIO_POWER_EN/GPIO70

DEVSLP0/GPIO33

DEVSLP1/GPIO38

DEVSLP2/GPIO39

THERMTRIP*

OUT

IN

OUT

BI

IN

OUT

IN

BI

NC

OUT

NC

OUT

BI

OUT

IN

OUT

IN

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

R1616 should also be stuffed if

TBTLC for CR, S0 for RR

platform does not use SD card

Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down.

Pull-up/down on chipset support page (depends on TBT controller)

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS

(IPD-PLTRST#)

STUFFED R1632

GPIO12:

(IPD-DeepSx)

(IPD-PLTRST#)

(IPD)

RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

(IPD)

(IPD-RSMRST#)

Requires connection to SMC via 1K series R

(IPD-PLTRST#)

Pull-up on TBT page

MF

1/20W

5% 201

10K

201

100K

1/20W

5% MF

5% 201

100K

1/20W

MF

5%

1/20W

100K

201MF

100K

1/20W

5% 201MF

MF 2015%

100K

1/20W

100K

1/20W

5% 201MF

100K

1/20W

5% 201MF

MF 2015%

1/20W

100K

1/20W

5% 201MF

MF 2015%

1/20W

100K

1/20W

201

100K

MF

5%

201MF5%

1K

1/20W

MF 2015%

1/20W

100K

1/20W

5%

MF

201

13 15 16 18

18

15 38 71

66

15 31

201

100K

MF

5%

1/20W

13 15 16 18

15 67

15 18

2015%

100K

MF

1/20W

2C+GT2

BROADWELL-ULT

CRITICAL

OMIT_TABLE

BGA

15 37 75

100K

MF

201

5%

1/20W

RAMCFG3:H

15 37 75

15 37

18 33

201

MF

5%

100K

1/20W

BAT54XV2T1

SOD-523

69

100K

MF

201

5%

1/20W

RAMCFG2:H

MF

5%

1M

1/20W

201

15 36 71

0201

1/20W

5%

0

MF

0

MF

0201

1/20W

5%

201

100K

MF

5%

1/20W

RAMCFG1:H RAMCFG0:H

5%

201

MF

100K

1/20W

26

15 71

15 65

15 71

65 71

40

15 16

15 16 18

15 16

15 32 64

15 71

15 66

15 25

15 16

15 18

15 63

15 47 71

15 18

15 32

15 31

32

15 38

15 66

39 75

15 16

15 16 18

18

15 16

5%

1K

1/20W

MF

201

1/20W

MF

100K

5% 201

MF

100K

1/20W

2015%

100K

MF5% 201

1/20W

5% MF

1/20W

100K

SD_ON_MLB

201

MF

1/20W

201

100K

5%

MF

1/20W

100K

5% 201

MF 201

100K

1/20W

5%

1/20W

MF 201

100K

5%

MF 201

1/20W

5%

100K

MF 2015%

100K

1/20W

201MF

100K

1/20W

5%

201

100K

5%

1/20W

MF

MF5%

100K

201

1/20W

201MF

100K

5%

1/20W

MF 2015%

1/20W

100K

201MF5%

1/20W

100K

201

1/20W

MF

100K

5%

1/20W

201MF

100K

5%

100K

201

1/20W

MF5%

5% MF

1/20W

100K

201

1/20W

5% MF 201

100K

10K

201

MF

1/20W

5%

MF5%

1/20W

201

100K

MF

1/20W

1%

49.9

201

PLACE_NEAR=U0500.AW15:2.54mm

201MF5%

1/20W

100K

1/20W

5% 201MF

100K

MF

1/20W

5% 201

1/20W

5%

100K

MF 201

100K

MF

1/20W

5% 201

47K

1/20W

MF5% 201

5%

47K

MF

1/20W

201

MF

1/20W

5% 201

47K

201MF

1/20W

5%

47K

RAMCFG_SLOT

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

PCH GPIO/MISC/LPIO

SYNC_MASTER=J41 SYNC_DATE=01/19/2013

BOM_COST_GROUP=CPU

ENET_MEDIA_SENSE

=TBT_GO2SX_BIDIR

HDMI_TBT_MUX_SEL_GPIO12

PLT_RESET_L

PCH_GSPI0_CLK

BT_PWRRST_L

XDP_JTAG_ISP_TCK

TBT_PWR_EN

SD_PWR_EN

XDP_MLB_RAMCFG3

PCH_HSIO_PWR_EN

JTAG_TBT_TMS_PCH

PCH_TBT_PCIE_RESET_L

PCH_I2C1_SDA

PCH_STRP_TOPBLK_SWP_L

TBT_POC_RESET_L

PCH_I2C1_SCL

XDP_MLB_RAMCFG3

XDP_LPCPLUS_GPIO

XDP_PCH_GPIO17

TP_MEM_VDD_SEL_1V5_L

XDP_MLB_RAMCFG0

PCH_I2C0_SDA

PCH_UART1_TXD

PCH_UART1_CTS_L

JTAG_ISP_TDO

AP_RESET_L

PCH_UART1_RXD

PCH_GSPI0_MOSI

TPAD_SPI_CLK

PCH_GSPI0_CS_L

PCH_OPI_COMP

=TBT_CIO_PLUG_EVENT

PCH_UART1_RTS_L

PCH_I2C0_SCL

XDP_MLB_RAMCFG2

PCH_I2C0_SDA

PCH_I2C1_SCL

=PP1V05_S0_CPU_VCCST

XDP_MLB_RAMCFG0

PCH_UART1_RXD

PCH_UART1_RTS_L

PCH_I2C0_SCL

PCH_I2C1_SDA

PCH_UART1_CTS_L

PCH_UART1_TXD

HDMITBTMUX_FLAG_L

AP_S0IX_WAKE_L

TPAD_SPI_MOSI

TPAD_SPI_MISO

PCH_GSPI0_CS_L

PCH_GSPI0_MISO

PCH_GSPI0_MOSI

TPAD_SPI_CS_L

TPAD_SPI_CLK

XDP_MLB_RAMCFG1

HDMITBTMUX_FLAG_L

AP_S0IX_WAKE_L

TPAD_SPI_MISO

TPAD_SPI_CS_L

XDP_JTAG_ISP_TDI

SD_RESET_L

SMC_WAKE_SCI_L

TPAD_USB_IF_EN

LCD_PSR_EN

XDP_MLB_RAMCFG1

CAMERA_PWR_EN_PCH

HDD_PWR_EN

XDP_SDCONN_STATE_CHANGE_L

TPAD_SPI_INT_GPIO28_L

TPAD_SPI_INT_GPIO46_L

TPAD_SPI_INT_L

TPAD_SPI_INT_GPIO46_L

TPAD_SPI_MOSI

SSD_PWR_EN

TPAD_SPI_INT_GPIO28_L

=PP3V3_S0_PCH_GPIO

TPAD_SPI_IF_EN

SPIROM_USE_MLB

JTAG_ISP_TDO

LPC_SERIRQ

LCD_PSR_EN

ENET_MEDIA_SENSE

BT_PWRRST_L

XDP_PCH_GPIO76

TPAD_SPI_IF_EN

PCH_GSPI0_MISO

PCH_GSPI0_CLK

LPC_SERIRQ

PM_THRMTRIP_L

PP3V3_S0_EDP_SW

LCD_IRQ_L

PLT_RESET_L

TBT_PWR_EN

PCH_HSIO_PWR_EN

AP_S0IX_WAKE_SEL

SSD_SR_EN_L

TPAD_SPI_INT_L

PCH_TCO_TIMER_DISABLE

XDP_MLB_RAMCFG2

XDP_PCH_GPIO76

XDP_LPCPLUS_GPIO

CAMERA_PWR_EN_PCH

SPIROM_USE_MLB

JTAG_TBT_TMS_PCH

XDP_JTAG_ISP_TDI

XDP_JTAG_ISP_TCK

SD_PWR_EN

XDP_SDCONN_STATE_CHANGE_L

TPAD_USB_IF_EN

SSD_PWR_EN

SD_RESET_L

XDP_PCH_GPIO17

=PP3V3_S5_PCH_GPIO

SMC_WAKE_SCI_L

AP_S0IX_WAKE_SEL

SSD_SR_EN_L

=PP3V3_S3RS4_PCH_GPIO

=PP3V3_S0RTBTLC_PCH_GPIO

HDD_PWR_EN

=PP3V3_S0_PCH_GPIO

=PP3V3_S3SW_SD_RESET

=PP3V3_S0_PCH_GPIO

SSD_RESET_L

CAM_PCIE_RESET_L

=PP3V3_S3RS0_CAMPWREN

=PP3V3_S3_PCH_GPIO

R1650

1

2

R1655

1

2

R1652

12

R1631

1

2

R1636

1

2

R1635

1

2

R1611

1

2

R1610

12

R1614

12

R1615

12

R1616

12

R1617

12

R1618

12

R1619

12

R1620

12

R1622

12

R1623

12

R1624

12

R1625

12

R1626

12

R1627

12

R1628

12

R1630

12

R1632

12

R1633

12

R1637

12

R1638

12

R1691

12

R1694

12

R1693

12

R1695

12

R1660

12

R1661

12

R1662

12

R1663

12

R1664

12

R1665

12

R1666

12

R1667

12

R1668

12

R1669

12

R1672

12

R1674

12

R1673

12

R1675

12

R1676

12

R1678

12

R1677

12

R1679

12

R1639

1

2

R1641

12

R1629

12

R1621

1

2

R1671

1

2

R1670

12

U0500

P1

P2

L2

N5

AM2

AT3

AH4

AD6

Y1

T3

AD5

AM4

AN3

AN5

AD7

AK4

AG5

AG3

AB6

U4

Y3

P3

AG6

AP1

AL4

AT5

AU2

AM3

L6

R6

N6

L8

L5

R7

N7

K2

Y2

F3

F2

F1

G4

AM7

AW15

V4

AB21

AF20

E3

F4

D3

E4

C3

E2

C4

T4

V2

D60

G1

J2

J1

K3

J4

J3

K4

G2

R1680

1

2

D1600

AK

R1600

1

2

R1682

1

2

R1681

1

2

16 OF 120

8.0.0

051-1573

dvt1

15 OF 82

15

15 16 18

15

75

15

15 16 18

15

6 8

16 17 55 68

15 16 18

15

15 67

15 31

15 37 75

15

15 37 75

15 16 18

15 37

15

12 13 15 18 26 65 68

15 18

15 38 71

15 65

15 71

15 37

15

41 65

15 25

15 63

15 36 71

15 16

15 18

15 47 71

15 18

15 16

15 66

15 16

15 37

15 32 64

15 66

15 16

13 68

15 38

15 31

15 32

68

15 71

12 13 15 18 26 65 68

68

12 13 15 18 26 65 68

18 44

68

IN

OUT

IN

OUT

IN

OUT

IN

NC

IN

TP

OUT

IN

OUT

IN

OUT

IN

TP

OUT

IN

BI

OUT

TP

BI

TP

BI

TP

BI

OUT

BI

IN

OUT

BI

IN

BI

IN

OUT

IN

OUT

BI

TP

IN

OUT

Y

NC NC

VCC

GND

A

NC

IN

NC

IN

TP

IN

TP

VER 3

D

SG

VER 3

D

SG

IN

VER 3

D

SG

VER 3

D

SG

IN

BI

IN

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH XDP Signals

OBSDATA_B0

OBSDATA_B2

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

Non-XDP Signals

NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.

These signals do not connect to XDP connector in this architecture, only accessible

via Top-Side Probe. Nets are listed here to show XDP associations and to make clear

what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

PCH/XDP Signals

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.

VCC_OBS_AB

SSD_PCIEx_SEL_L straps are connected via 1K to common net.

LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

Unused & MLB_RAMCFGx GPIOs have TPs.

NOTE: Must not short XDP pins together!

TDI and TMS are terminated in CPU.

HOOK2

TDO

TRSTn

Merged (CPU/PCH) Micro2-XDP

OBSFN_D0

SCL

OBSDATA_A1

Use with 921-0133 Adapter Flex to

NOTE: This is not the standard XDP pinout.

TCK0

TCK1

SDA

HOOK1

OBSDATA_B3

PWRGD/HOOK0

OBSDATA_B1

OBSFN_B0

OBSDATA_A2

OBSDATA_A3

OBSFN_B1

OBSDATA_A0

ITPCLK/HOOK4

DBR#/HOOK7

OBSDATA_D3

ITPCLK#/HOOK5

OBSFN_D1

OBSDATA_D0

OBSDATA_C2

OBSDATA_C3

OBSDATA_C1

OBSFN_C1

OBSDATA_C0

OBSFN_C0

518S0847

support chipset debug.

Extra BPM Testpoints

RESET#/HOOK6

VCC_OBS_CD

OBSFN_A1

OBSFN_A0

CPU JTAG Isolation

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

XDP_PRESENT#

TMS

TDI

HOOK3

OBSDATA_D2

OBSDATA_D1

6

73

13 15 18

6

73

6

73

6

73

6

73

6

73

6

73

13 38 75

13 17 38 75

12 16 73

17 75

6

73

12 16 73

5% 201

1/20W

MF

XDP

1K

PLACE_NEAR=U0500.AG7:2.54mm

5% 201

1/20W

MF

XDP

51

PLACE_NEAR=U0500.E60:28mm

5%

0

402

MF-LF

XDP

1/16W

5%

0

0201

1/20W

MF

XDP

PLACE_NEAR=U5000.J3:2.54mm

5% 201

1/20W

MF

1K

XDP

PLACE_NEAR=U0500.C61:2.54mm

6

73

M-ST-SM1

CRITICAL

DF40RC-60DP-0.4V

XDP_CONN

6

73

6

73

6

73

6

73

6

73

6

73

6

73

6

73

6

73

6

73

TP-P6

8

5%

150

402

MF-LF

1/16W

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.F62:28mm

12 16 73

5%

XDP

MF-LF

402

1/16W

1K

5% 201

1/20W

MF

51

PLACE_NEAR=U0500.AE62:28mm

NO STUFF

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.AD62:28mm

5% 201

1/20W

MF

51

XDP

PLACE_NEAR=U0500.AD61:28mm

XDP

5% 201

1/20W

MF

51

PLACE_NEAR=U0500.AE61:28mm

5% 201

1/20W

MF

1K

PLACE_NEAR=U0500.AE63:28mm

NO STUFF

5%

0

0201

1/20W

MF

XDP

PLACE_NEAR=J1800.58:28mm

12 16 73

6

73

6

73

6

16 73

XDP

CERM-X5R

0201

6.3V

0.1UF

10%

15

14

6

73

66

TP-P6

14 35

15 18

14

TP-P6

XDP

CERM-X5R

0201

6.3V

0.1UF

10%

TP-P6

15 18

TP-P6

15 18

TP-P6

15 18

12

15

15 18

12

5% 201

1/20W

MF

1K

5% 201

1/20W

MF

1K

6

73

5% 201

1/20W

MF

1K

5% 201

1/20W

MF

1K

32

15

6

73

15

15 18

71

TP-P6

XDP

CERM-X5R

0201

6.3V

0.1UF

10%

0.1UF

CERM-X5R

0201

XDP

6.3V

10%

6

73

12 16

5% 201

1/20W

MF

PLACE_NEAR=U0500.AU62:28mm

NO STUFF

51

SOT891

74LVC1G07GF

16V

0201

X5R-CERM

0.1UF

10%

6

73

5%

201

1/20W

MF

330K

17 38 64

TP-P6

18

TP-P6

DMN5L06VK-7

SOT563

XDP

CRITICAL

SIGNAL_MODEL=DMN5L06VK_7

PLACE_NEAR=J1800.51:28mm

XDP

CRITICAL

SOT563

PLACE_NEAR=J1800.53:28mm

SIGNAL_MODEL=DMN5L06VK_7

DMN5L06VK-7

6

73

SOT563

SIGNAL_MODEL=DMN5L06VK_7

DMN5L06VK-7

XDP

CRITICAL

PLACE_NEAR=J1800.55:28mm

CRITICAL

PLACE_NEAR=J1800.57:28mm

XDP

SOT563

DMN5L06VK-7

SIGNAL_MODEL=DMN5L06VK_7

6

73

41

6

16 73

6

73

8

17 73

6

73

6

73

6

73

SYNC_MASTER=WFERRY_J43

CPU/PCH Merged XDP

SYNC_DATE=12/21/2012

BOM_COST_GROUP=CPU SUPPORT

CPU_CFG<19>

CPU_CFG<18>

CPU_CFG<15>

XDP_SYS_PWROK

XDP_CPU_TMS

CPU_CFG<11>

CPU_CFG<3>

CPU_CFG<12>

CPU_PWR_DEBUG

CPU_CFG<4>

ALL_SYS_PWRGD

XDP_PCH_TMS

XDP_PCH_TRST_L

XDP_CPU_TCK

XDP_BPM_L<6>

XDP_BPM_L<7>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

PCH_JTAGX

XDP_PCH_TDI

XDP_CPU_TDO

XDP_PCH_TDO

=PP1V05_S0_CPU_VCCST

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

CPU_CFG<0>

CPU_CFG<2>

XDP_BPM_L<1>

CPU_CFG<5>

CPU_CFG<6>

CPU_CFG<7>

=SMBUS_XDP_SCL

XDP_PCH_TCK

CPU_VCCST_PWRGD

XDP_CPU_PWRBTN_L

PM_PWRBTN_L

PCH_JTAGX

PM_PCH_SYS_PWROK

CPU_CFG<17>

CPU_CFG<16>

CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<13>

CPU_CFG<14>

XDP_CPURST_L

PLT_RESET_L

XDP_PCH_TRST_L

CPU_CFG<10>

XDP_PCH_TCK

XDP_CPU_VCCST_PWRGD

SSD_PCIE_SEL_L

USB_EXTA_OC_L

USB_EXTB_OC_L

SDCONN_STATE_CHANGE_L

JTAG_ISP_TCK

LPCPLUS_GPIO

XDP_MLB_RAMCFG0

XDP_USB_EXTC_OC_L

XDP_USB_EXTD_OC_L

XDP_MLB_RAMCFG1

XDP_SSD_PCIE1_SEL_L

XDP_PCH_GPIO76

=SMBUS_XDP_SDA

JTAG_ISP_TDI

XDP_SSD_PCIE0_SEL_L

XDP_SSD_PCIE2_SEL_L

XDP_PCH_GPIO17

XDP_SSD_PCIE3_SEL_L

XDP_MLB_RAMCFG3

XDP_MLB_RAMCFG2

=PP1V05_SUS_PCH_JTAG

XDP_CPU_TCK

XDP_CPU_TRST_L

XDP_CPU_TDO

XDP_TRST_L

XDP_PCH_TDO

=PP1V05_S0_XDP

XDP_BPM_L<0>

CPU_CFG<1>

XDP_CPU_TDI

XDP_CPU_PRESENT_L

XDP_PCH_TDI

XDP_JTAG_CPU_ISOL_L

XDP_PCH_TMS

XDP_DBRESET_L

=PP5V_S0_XDPJTAGISOL

=PP3V3_S5_XDPJTAGISOL

XDP_USB_EXTA_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

XDP_SDCONN_STATE_CHANGE_L

MAKE_BASE=TRUE

XDP_JTAG_ISP_TCK

MAKE_BASE=TRUE

XDP_JTAG_ISP_TDI

MAKE_BASE=TRUE

XDP_LPCPLUS_GPIO

MAKE_BASE=TRUE

XDP_CPUPCH_TRST_L

C1801

1

2

C1800

1

2

R1805

12

R1813

21

R1804

12

R1802

12

R1800

12

J1800

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

61

62

6364

78

9

TP1806

1

TP1807

1

TP1805

1

TP1804

1

TP1803

1

TP1802

1

R1830

1

2

R1810

12

R1831

1

2

R1896

21

R1892

21

R1891

21

R1890

21

R1899

21

R1835

12

TP1870

1

TP1874

1

TP1876

1

TP1877

1

TP1878

1

R1881

12

R1882

12

R1883

12

R1884

12

TP1887

1

C1804

1

2

C1806

1

2

R1897

21

U1845

2

3

1

5

6

4

C1845

1

2

R1845

1

2

TP1873

1

TP1886

1

Q1840

3

5

4

Q1840

6

2

1

Q1842

3

5

4

Q1842

6

2

1

16 OF 82

dvt1

051-1573

8.0.0

18 OF 120

75

12 16 73

12 16

6

16 73

12 16 73

6

16 73

12 16 73

6 8

15 17 55 68

75

12 16 73

73

68

73

68

73

OUT

IN

BIIN

OUT

IN

OUT

NC

OUT

IN

NC

OUT

IN

NC

AY

NC NC

VCC

GND

NC

IN

OUT

IN

Y

A

B

08

Y

A

B

08

OUT

IN

OUT

IN

YA

B

NC

GND

VCC

32.768K

GND

THRM

VOUT

X2

X1

25M_A

25M_B

25M_C

VIOE_25M_A

VIOE_25M_B

VIOE_25M_C

VG3HOT

NC

VDD

PAD

NC

VER 3

D

SG

VER 3

D

SG

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

PCH ME Disable Strap

SMC controls strap enable to allow in-field control of strap setting.

PCH PWROK Generation

Must be powered if any VDDIO is powered.

This looks a little ugly to support

For SB RTC Power

to reduce VBAT draw.

+V3.3A should be first

create VDD_RTC_OUT.

internally ORed to

VBAT and +V3.3A are

Coin-Cell: VBAT (300-ohm & 10uF RC)

Coin-Cell & G3Hot: 3.42V G3Hot

GreenCLK 25MHz Power

Coin-Cell & No G3Hot: 3.3V S5

No Coin-Cell: 3.3V S5

No bypass necessary

PCH 24MHz Outputs

CAM XTAL Power

PCH Reset Button

IPD = 9-50k

VCCST (1.05V S0) PWRGD

Memory VTT Enable Level-Shifter

CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

33uW when driven-low

Vih(min) = 1.8V

TPS51916 I(leak) = +/- 1uA,

WF: Do we need this?

available ~3.3V power

pin 5 must receive S5 power (Stuff R2042)

new and old parts. With GreenCLK Rev C

Chipset uses 24MHz crystal, GreenCLK kept to save 1x 25MHz crystal & 1x 32kHz crystal

No Coin-Cell: 3.42V G3Hot (no RC)

PCH 24MHz Crystal

NOTE: 30 PPM or better required for RTC accuracy

TBT XTAL Power

System RTC Power Source & 32kHz / 25MHz Clock Generator

12 75

25 74

6.3V

X5R

1UF

20%

0201

6.3V

20%

1UF

X5R

0201

25V

CERM

0201

12PF

5%

25V

CERM

0201

12PF

5%

38

201

1/20W

MF

22

PLACE_NEAR=U0500.AN15:5.1mm

5%

12 75

13 38 71 75 16 75

16V

0.1UF

X5R-CERM

10%

0201

MF

0

1/20W

0201

5%

NO STUFF

201

1/20W

MF

1M

5%

0

1/20W

MF

XDP

5%

0201

0

1/16W

MF-LF

SILK_PART=SYS RESET

NO STUFF

5%

402

201

1/20W

MF

10K

5%

201

1/20W

MF

100K

5%

1K

5%

201

1/20W

MF

12 75

38

0.1UF

10%

16V

X5R-CERM

0201

34 74

201

1/20W

MF

1M

5%

0

1/20W

MF

0201

5%

C0G

6.8PF

+/-0.1PF

25V

0201

6.8PF

C0G

+/-0.1PF

25V

0201

12 75

12

8

16 73

201

1/20W

MF

10K

5%

16V

X5R-CERM

10%

0.1UF

0201

13 18 38 64 66 71

201

1/20W

MF

330K

5%

SOT891

74AUP1G07GF

0.1UF

10%

16V

X5R-CERM

0201

6

57

26 27 38 39 75

16 17 38 64

74LVC2G08GT/S505

SOT833

BYPASS=U1950::5MM

X5R-CERM

10%

16V

0.1UF

0201

74LVC2G08GT/S505

CKPLUS_WAIVE=UNCONNECTED_PINS

SOT833

CKPLUS_WAIVE=UNCONNECTED_PINS

0

1/20W

MF

0201

5%

0

1/20W

MF

NO STUFF

0201

5%

1/20W

201

MF

1K

5%

13 16 38 75

13 75

13

0

1/20W

MF

NO STUFF

0201

5%

201

1/20W

MF

10K

5%

201

1/20W

MF

10K

5%

8

55

8

55

201

1/20W

MF

NO STUFF

100K

5%

74AUP1G09

SOT891

CRITICAL

SLG3NB148CV

CRITICAL

TQFN

CKPLUS_WAIVE=PwrTerm2Gnd

CRITICAL

3.20X2.50MM-SM1

24.000MHZ-20PPM-6PF

OMIT

CRITICAL

25.000MHZ-12PF-20PPM

SM-3.2X2.5MM

DMN5L06VK-7

SOT563

SIGNAL_MODEL=DMN5L06VK_7

SOT563

DMN5L06VK-7

SIGNAL_MODEL=DMN5L06VK_7

Chipset Support

SYNC_DATE=01/30/2013SYNC_MASTER=J41

BOM_COST_GROUP=CPU SUPPORT

197S0480

Y1905

1

XTAL,25MHZ,20PPM,12PF,3.2X2.5X.6MM,85C

CPU_VCCST_PWRGD

SPI_DESCRIPTOR_OVERRIDE

SPI_DESCRIPTOR_OVERRIDE_L

SYSCLK_CLK25M_X1

=PP3V3_S3RS0_SYSCLKGEN

LPC_CLK_SMC

=PPVDDIO_S3RS0_CAMCLK

SYSCLK_CLK25M_TBT

SYSCLK_CLK25M_CAMERA

SYSCLK_CLK25M_X2_R

=PPVRTC_G3_OUT

=PP3V3_S0_SB_PM

CPUVR_PGOOD_R

PM_PCH_APWROK

PM_S0_PGOOD

PM_PCH_SYS_PWROK

=DDRVTT_EN

=PP3V3_S0_MEM_VTTPWRCTL

=PP1V2_S3_MEM_VTTPWRCTL

=PP5V_S0_PCH_STRAP

SYS_PWROK_R

LPC_CLK24M_SMC_R

PCH_CLK24M_XTALOUT

HDA_SDOUT_R

=PP3V3_S0_SB_PM

PM_SYSRST_L

XDP_DBRESET_L

=PP3V42_G3H_CSPWRGD

CPUVR_PGOOD

CPU_VR_EN

ALL_SYS_PWRGD

SMC_DELAYED_PWRGD

=PP1V05_S0_CPU_VCCST

=PP3V3_S5_CSPWRGD

ALL_SYS_PWRGD

PCH_CLK24M_XTALOUT_R

=PPVBAT_G3H_SYSCLK

=PPVDDIO_TBTLC_CLK

PCH_CLK32K_RTCX1

PCH_CLK32K_RTCX2

=PP3V3_S5_SYSCLK

PM_SLP_S3_L

SYSCLK_CLK25M_X2

PCH_CLK24M_XTALIN

CPU_MEMVTT_PWR_EN_LSVDDQ

=PP3V3R1V5_S0SW_PCH_VCCSUSHDA

SPI_DESCRIPTOR_OVERRIDE_LS5V

MAKE_BASE=TRUE

CPU_VR_READY

MEMVTT_PWR_EN

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_RTC_CLK32K_RTCX2

LPC_CLK24M_SMC

MAKE_BASE=TRUE

PM_PCH_PWROK

MAKE_BASE=TRUE

C1902

1

2

C1910

1

2

C1905

12

C1906

12

R1927

12

C1924

1

2

R1905

12

R1906

1

2

R1996

12

R1997

1

2

R1995

1

2

R1920

1

2

R1921

1

2

C1922

1

2

R1916

1

2

R1915

12

C1915

12

C1916

12

R1931

1

2

C1930

1

2

R1970

1

2

U1970

2

3

1

5

6

4

C1970

1

2

U1950

1

2

4

8

7

C1950

1

2

U1950

5

6

4

8

3

R1963

2

1

R1960

2

1

R1962

12

R1951

12

R1950

1

2

R1955

1

2

R1961

1

2

U1930

2

1

36

4

U1900

9

8

15

12

7

10

16

17

5

13

11

6

14

1

4

3

Y1915

24

13

Y1905

24

13

Q1920

3

5

4

Q1920

6

2

1

dvt1

051-1573

8.0.0

19 OF 120

17 OF 82

5

2

74

18

33

74

68

17 68

75

68

75

17 68

68

6 8

15 16 55 68

68

16 17 38 64

75

68

18 68

74

8

11 63

71 75

OUT

IN

OUT

IN

OUT

IN

OUT

YA

B

NC

GND

VCC

NC

IN

OUT

IN

OUT

IN

OUT

VCC

1A 1Y

2A 2Y

GND

IN

OUT

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

VER 3

D

SG

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(For development only)

Power State Debug LEDs

To SMC

Buffered

Scrub for Layout Optimization

Platform Reset Connections

To PCH

From RR

From PCH

and TDI as well for PCH glitch-prevention.

S0 pull-up on PCH page

GreenCLK 25MHz Power

SDCONN_STATE_CHANGE Isolation

R2042 should be stuffed for GreenCLK C

GreekCLK A or B depending on S2 rail

R2041/2 should be stuffed for

MAKE_BASE

Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs

THUNDERBOLT PULL-UP

REDWOOD RIDGE PLUG_EVENT IS ACTIVE-LOW, ALWAYS DRIVEN (PULL-UP)

Pull-downs for chip-down RAM systems

RAM Configuration Straps

Multi-router designs also require different circuitry.

different isolation techniques will likely be necessary.

NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for

NOTE: Solution shown is for LPT-LP. Other PCH’s may require isolation on TCK

Pin N61 needs a TP for Power to perform iFDIM test

Isolation ensures no leakage to RR or PCH

TBTLC can be on when S0 is off, and vice-versa

Redwood Ridge JTAG Isolation

Renaming the pins N61 and P61 to remove automatic diffpari property

S0 pull-up on PCH page

To PCH

To RR

RAMCFG3:L

201

5%

1/20W

MF

10K

RAMCFG2:L

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

RAMCFG1:L

1/20W

RAMCFG0:L

5%

201

MF

10K

DBGLED

PLACE_SIDE=BOTTOM

LTQH9G-SM

SILK_PART=S5_ON

GREEN-56MCD-2MA-2.65V

LTQH9G-SM

DBGLED

PLACE_SIDE=BOTTOM

SILK_PART=STBY_ON

GREEN-56MCD-2MA-2.65V

DBGLED

1/20W

5%

201

MF

20K

PLACE_SIDE=BOTTOM

1/16W

5%

402

MF-LF

0

DBGLED

1/20W

5%

201

MF

20K

DBGLED

LTQH9G-SM

DBGLED

SILK_PART=S3_ON

GREEN-56MCD-2MA-2.65V

PLACE_SIDE=BOTTOM

DBGLED

1/20W

5%

201

MF

20K

LTQH9G-SM

DBGLED

SILK_PART=S0I3_ON

PLACE_SIDE=BOTTOM

GREEN-56MCD-2MA-2.65V

5%

201

20K

DBGLED

1/20W

MF

15 16

64

13 31 37 38 64 66

13 17 38 64 66 71

1/20W

201

20K

MF

5%

DBGLED

SILK_PART=S0_ON

PLACE_SIDE=BOTTOM

DBGLED

LTQH9G-SM

GREEN-56MCD-2MA-2.65V

13 38

16V

10%

0201

X5R-CERM

0.1UF

MC74VHC1G08

CRITICAL

SC70-HF

201

MF

5%

1/20W

100K

1/20W

MF

0201

5%

0

13 15 16

38

15

MF

201

5%

1/20W

100K

25 75

0201

NO STUFF

1/20W

MF

5%

0

15 33

15

16

CERM-X5R

0.1UF

BYPASS=U2030.5::5MM

0201

6.3V

10%

74AUP1G09

SOT891

CRITICAL

1/20W

470K

201

MF

5%

201

5%

1/20W

MF

470K

66

25

0201

1/20W

0

MF

5%

NOSTUFF

15

BYPASS=U2030::3mm

0201

10%

10V

X5R-CERM

0.1UF

33

1/20W

5%

0201

MF

0

1/20W

0201

5%

MF

0

NO STUFF

I1608

1/20W

MF

0201

5%

0

NO STUFF

25

15

1/20W

100K

5%

201

MF

10V

20%

402

CERM

0.1UF

MF

5%

201

1/20W

100K

25

15

SOT891

74LVC2G07

16

25

DMN5L06VK-7

SOT563

DMN5L06VK-7

DBGLED

SOT563

DMN5L06VK-7

DBGLED

SOT563

DMN5L06VK-7

SOT563

DBGLED

DMN5L06VK-7

DBGLED

SOT563

MC74VHC1G08

SC70-HF

CRITICAL

BYPASS=U2030::3mm

X5R-CERM

0.1UF

0201

10V

10%

BYPASS=U2030::3mm

201

MF

5%

1/20W

10K

201

1/20W

MF

5%

33

BOM_COST_GROUP=CPU SUPPORT

SYNC_MASTER=J41

Project Chipset Support

SYNC_DATE=10/23/2012

TRUE

TBT_CIO_PLUG_EVENT_L

=PP3V3_S0_PCH_GPIO

PP3V3_TBTLC

JTAG_TBT_TMS

XDP_MLB_RAMCFG0

XDP_MLB_RAMCFG1

XDP_MLB_RAMCFG2

JTAG_ISP_TDO

JTAG_TBT_TCK

JTAG_TBT_TDI

MAKE_BASE=TRUE

TP_CPU_RSVDN61

TP_CPU_RSVDP61

MAKE_BASE=TRUE

=TBT_CIO_PLUG_EVENT

=PP3V3_S3RS0_SYSCLKGEN

VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP3V3_S5RS3RS0_SYSCLKGEN

MIN_LINE_WIDTH=0.5 MM

=PP3V3_S3_SYSCLKGEN

=PP3V3_S5_SYSCLK

=PP3V3_S0_SYSCLKGEN

JTAG_TBT_TDO

JTAG_TBT_TMS_PCH

TP_CPU_RSVD_P61

JTAG_ISP_TDI

MAKE_BASE=TRUE

JTAG_ISP_TCK

MAKE_BASE=TRUE

TP_CPU_RSVD_N61

=PP3V3_S4_SMC

SDCONN_STATE_CHANGE_RIO

XDP_MLB_RAMCFG3

CAMERA_PWR_EN

CAMERA_PWR_EN_R

=PP3V3_S4_CAMPWREN

CAMERA_PWR_EN_PCH

SMC_PME_SDCONN

=PP3V3_S3_SDBUF

=SMC_PME_SDCONN_L

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=3.3V

PP3V3_S5_DBGLED

DBGLED_S0

CAMERA_PWR_EN_RC

=PP3V3_S3RS0_CAMPWREN

DBGLED_S0_D

PM_SLP_S0_L

SDCONN_STATE_CHANGE_L

SMC_PME_S4_DARK_L

=PP3V3_S0_RSTBUF

PLT_RESET_L

SMC_LRESET_L

TBT_PCIE_RESET_L

CAM_PCIE_RESET_L

PLT_RST_BUF_L

PCH_TBT_PCIE_RESET_L

MAKE_BASE=TRUE

DBGLED_S4 DBGLED_S3

DBGLED_S0I3

DBGLED_S0I3_D

PM_SLP_S3_L

DBGLED_S3_D

PM_SLP_S4_L

DBGLED_S4_D

S4_PWR_EN

=PP3V3_S5_DBGLEDS

DBGLED_S5

R2050

1

2

R2051

1

2

R2052

1

2

R2053

1

2

D2090

A

K

D2091

A

K

R2090

1

2

R2094

12

R2091

1

2

D2092

A

K

R2092

1

2

D2093

A

K

R2093

1

2

R2095

1

2

D2095

A

K

C2071

1

2

U2071

3

2

1

4

5

R2070

1

2

R2072

12

R2015

1

2

R2089

12

C2031

1

2

U2031

2

1

36

4

R2031

1

2

R2032

1

2

R2030

12

C2030

1

2

R2042

12

R2040

12

R2041

12

R2061

1

2

C2060

1

2

R2062

1

2

U2060

1

6

3

4

25

Q2030

3

5

4

Q2090

3

5

4

Q2030

6

2

1

Q2090

6

2

1

Q2091

6

2

1

Q2091

3

5

4

U2030

3

2

1

4

5

C2034

1

2

R2034

1

2

R2033

12

dvt1

051-1573

8.0.0

20 OF 120

18 OF 82

5

12 13 15 26 65 68

25 26 68

17 68

68

8

39 40 68

68

15 44

38 39

68

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: CPU DAC output step sizes:

DDR3 (1.5V) 7.70mV per step

DDR3L (1.35V) 6.99mV per step

LPDDR3 (1.2V) ?.??mV per step

6.36mV / step @ output

0.000V - 2.397V (0x00 - 0xBA)

LPDDR3 (1.2V)

VRef Dividers

CPU-Based Margining

NOTE: CPU has single output for VREFCA.

NOTE: LPDDR3 assumes TPS51916 supply with 28.7k/57.6k divider

3.53mV / step @ output

+25uA - -25uA (- = sourced)

0.000V - 2.694V (0x00 - 0xD1)

DDR3L assumes TPS51916 supply with 19.6k/57.6k divider

+21uA - -21uA (- = sourced)

4.28mV / step @ output

VREFCA. Connected to 4 DRAMs.

Always used, regardless

of margining option.

0.000V - 1.354V (0x00 - 0x69)

+82uA - -82uA (- = sourced)

6.36mV / step @ output

+73uA - -73uA (- = sourced)

0.000V - 1.199V (0x00 - 0x5D)

0.300V - 0.900V (+/- 300mV)

MEM A VREF DQ

1.343V (DAC: 0x68)

LPDDR3 (1.2V)

Margined target:

DAC step size:

VRef current:

Nominal value

DAC range:

0.675V (DAC: 0x34)

0.337V - 1.013V (+/- 337.5mV)

4

C

DDR3L (1.35V)

MEM B VREF CA

3

C

MEM A VREF CA

2

B

MEM B VREF DQ

A

1

PCA9557D Pin:

DAC Channel:

0.800V - 1.600V (+/- 400mV)

MEM VREG

D

5

1.200V (DAC: 0x5D)

DDR3L (1.35V)

0.972V - 1.714V (+/- 371mV)

0.600V (DAC: 0x2E.5)

7

76

7

76

7

76

1/20W

201

24.9

MF

1%

0.022UF

6.3V

X5R-CERM

0201

10%

24.9

MF

201

1%

1/20W

6.3V

0.022UF

X5R-CERM

0201

10%

201

24.9

MF

1%

1/20W

0.022UF

X5R-CERM

0201

10%

6.3V

10

MF

201

1%

1/20W

MF

10

201

1%

1/20W

5.1

MF

0201

1%

8.2K

MF

201

1%

1/20W

PLACE_NEAR=R2221.2:1mm

8.2K

MF

201

1%

1/20W

8.2K

MF

201

1%

1/20W

8.2K

MF

201

1%

1/20W

PLACE_NEAR=R2241.2:1mm

8.2K

MF

201

1%

1/20W

PLACE_NEAR=R2261.2:1mm

8.2K

MF

201

1%

1/20W

LPDDR3 VREF Margining

SYNC_DATE=01/02/2013

SYNC_MASTER=YHARTANTO_J44

BOM_COST_GROUP=CPU SUPPORT

MEM_VREFDQ_B_RC

CPU_DIMM_VREFCA

PPVREF_S3_MEM_VREFCA

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.2 mm

PPVREF_S3_MEM_VREFDQ_A

MEM_VREFDQ_A_RC

MEM_VREFCA_RC

CPU_DIMMA_VREFDQ

=PPDDR_S3_MEMVREF

PPVREF_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.2 mm

CPU_DIMMB_VREFDQ

R2260

12

C2260

1

2

R2240

12

C2240

1

2

R2220

12

C2220

1

2

R2223

12

R2243

12

R2263

12

R2221

1

2

R2222

1

2

R2241

1

2

R2242

1

2

R2261

1

2

R2262

1

2

22 OF 120

dvt1

19 OF 82

8.0.0

051-1573

68

BI

VSSQ

VSS

VDDQ

VDDCA

VDD2

VDD1

VSSCA

SYM 2 OF 2

ZQ1

ZQ0

NC

DQ1

DQ22

NU

CA7

VREFDQ

VREFCA

DQS3_T

DQS1_T

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ31

DQ30

DQ3

DQ29

DQ28

DQ27

DQ26

DQ24

DQ23

DQ20

DQ2

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ12

DQ11

DQ10

DQ0

CKE1

CA5

CA4

CA3

CA1

CA0

CA6

CK_C

DQ25

DQS1_C

DQS0_C

ODT

CA2

DQS2_T

DQS0_T

CA9

DQ21

DQS3_C

DQS2_C

CK_T

CKE0

CA8

DM3

CS1*

DM0

DM1

DM2

CS0*

DQ13

SYM 1 OF 2

BI

NC

IN

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10uF caps are shared between DRAM.

PLACEMENT_NOTE:

LPDDR3 CHANNEL A (0-31)

Distribute evenly.

70

10UF

20%

25V

0603

X5R-CERM

0603

X5R-CERM

20%

25V

10UF

1UF

402

10V

X5R

10%

70

10%

0.1UF

16V

0201

X5R-CERM

10V

1UF

10%

X5R

402

10V

402

1UF

10%

X5R

16V

10%

0.1UF

X5R-CERM

0201

X5R

402

10%

1UF

10V

70

10V

X5R

1UF

10%

402

10V

X5R

402

1UF

10%

25V

0603

10UF

20%

X5R-CERM

10%

1UF

X5R

10V

402

10%

X5R

10V

1UF

402

10%

402

X5R

10V

1UF

70

X5R-CERM

20%

0603

25V

10UF

X5R-CERM

20%

10UF

0603

25V

20%

0603

25V

X5R-CERM

10UF

0603

X5R-CERM

25V

20%

10UF

10%

X5R

10V

402

1UF

10%

1UF

X5R

10V

402

70

6.3V

X5R

10%

201

0.047UF

10%

6.3V

X5R

0.047UF

201

LPDDR3-1600-32GB

CRITICAL

FBGA

OMIT_TABLE

EDFB232A1MA

LPDDR3-1600-32GB

CRITICAL

OMIT_TABLE

FBGA

EDFB232A1MA

50V

CRITICAL

C0G-CERM

2%

12PF

0402

C0G-CERM

2%

12PF

50V

CRITICAL

0402

C0G-CERM

2%

12PF

50V

CRITICAL

0402

70

C0G-CERM

2%

12PF

50V

CRITICAL

0402

C0G-CERM

2%

50V

CRITICAL

0402

12PF

C0G-CERM

2%

CRITICAL

0402

50V

12PF

70

24 70 76

70

24 70 76

7

24 76

7

24 76

7

24 76

7

24 76

7

21 24 76

7

21 24 76

21 24 70 76

70

243

1%

1/20W

MF

201 201

MF

1/20W

243

1%

70

BOM_COST_GROUP=DRAM

SYNC_MASTER=J41_MLB

SYNC_DATE=02/06/2013

LPDDR3 DRAM Channel A (00-31)

=PP1V2_S3_MEM_VDD2

=PP1V2_S3_MEM_VDDCA

=PP1V2_S3_MEM_VDDQ

=PP1V2_S3_MEM_VDDCA

=MEM_A_DQ<13>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CAA<8>

MEM_A_CKE<0>

MEM_A_CLK_P<0>

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<3>

=MEM_A_DQ<21>

MEM_A_CAA<9>

=MEM_A_DQS_P<0>

=MEM_A_DQS_P<2>

MEM_A_CAA<2>

MEM_A_ODT<0>

=MEM_A_DQS_N<0>

=MEM_A_DQS_N<1>

=MEM_A_DQ<25>

MEM_A_CLK_N<0>

MEM_A_CAA<6>

MEM_A_CAA<0>

MEM_A_CAA<1>

MEM_A_CAA<5>

MEM_A_CKE<1>

=MEM_A_DQ<0>

=MEM_A_DQ<10>

=MEM_A_DQ<11>

=MEM_A_DQ<12>

=MEM_A_DQ<15>

=MEM_A_DQ<16>

=MEM_A_DQ<17>

=MEM_A_DQ<18>

=MEM_A_DQ<19>

=MEM_A_DQ<2>

=MEM_A_DQ<20>

=MEM_A_DQ<23>

=MEM_A_DQ<24>

=MEM_A_DQ<26>

=MEM_A_DQ<27>

=MEM_A_DQ<28>

=MEM_A_DQ<29>

=MEM_A_DQ<3>

=MEM_A_DQ<30>

=MEM_A_DQ<31>

=MEM_A_DQ<6>

=MEM_A_DQ<7>

=MEM_A_DQ<8>

=MEM_A_DQ<9>

=MEM_A_DQS_P<1>

=MEM_A_DQS_P<3>

PP0V6_S3_MEM_VREFCA_A

PP0V6_S3_MEM_VREFDQ_A

MEM_A_CAA<7>

=MEM_A_DQ<22>

=MEM_A_DQ<1>

MEM_A_ZQ<0>

MEM_A_ZQ<1>

=MEM_A_DQ<5>

=MEM_A_DQ<14>

MEM_A_CAA<4>

MEM_A_CAA<3>

=MEM_A_DQ<4>

=PP1V8_S3_MEM

=PP1V2_S3_MEM_VDD2

=PP1V2_S3_MEM_VDDQ

R2300

1

2

R2301

1

2

C2306

1

2

C2307

1

2

C2302

1

2

C2300

1

2

C2303

1

2

C2304

1

2

C2301

1

2

C2305

1

2

C2310

1

2

C2311

1

2

C2312

1

2

C2320

1

2

C2321

1

2

C2322

1

2

C2324

1

2

C2323

1

2

C2333

1

2

C2332

1

2

C2331

1

2

C2330

1

2

C2341

1

2

C2340

1

2

U2300

A3

A4

A5

A6

A10

U3

U4

U5

U6

U10

A8

A9

J6

K5

K6

K12

L5

P4

P5

P6

U8

U9

D4

D5

D6

G5

H5

H6

H12

J5

F2

G2

H3

L2

M2

A11

C12

K8

K11

L12

N8

N12

R12

U11

E8

E12

G12

H8

H9

H11

J9

J10

B2

B5

N4

N5

R4

R5

T2

T3

T4

T5

H2

C5

E4

E5

F5

J12

K2

L6

M5

C3

D3

F4

G3

G4

P3

M4

J4

B6

B12

K10

L9

M6

M12

N6

P12

R6

T6

T12

C6

D12

E6

F6

F12

G6

G9

H10

U2300

R2

P2

N2

N3

M3

F3

E3

E2

D2

C2

J2

J3

K3

K4

L3

L4

L8

G8

P8

D8

P9

N9

F9

F8

E11

E10

E9

D9

T8

T9

T10

T11

N10

R8

R9

R10

R11

C11

C10

C9

C8

B11

B10

N11

B9

B8

M8

M9

M10

M11

F11

F10

L11

L10

G11

G10

P11

P10

D11

D10

C4

K9

R3

A1

A2

U12

U13

A12

A13

B1

B13

T1

T13

U1

U2

J8

H4

J11

B3

B4

C2334

1

2

C2335

1

2

C2336

1

2

C2337

1

2

C2338

1

2

C2339

1

2

20 OF 82

dvt1

8.0.0

051-1573

23 OF 120

20 21 22 23 68

21 68 76

20 21 22 23 68

BI

IN

BI

ZQ1

ZQ0

NC

DQ1

DQ22

NU

CA7

VREFDQ

VREFCA

DQS3_T

DQS1_T

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ31

DQ30

DQ3

DQ29

DQ28

DQ27

DQ26

DQ24

DQ23

DQ20

DQ2

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ12

DQ11

DQ10

DQ0

CKE1

CA5

CA4

CA3

CA1

CA0

CA6

CK_C

DQ25

DQS1_C

DQS0_C

ODT

CA2

DQS2_T

DQS0_T

CA9

DQ21

DQS3_C

DQS2_C

CK_T

CKE0

CA8

DM3

CS1*

DM0

DM1

DM2

CS0*

DQ13

SYM 1 OF 2

VSSQ

VSS

VDDQ

VDDCA

VDD2

VDD1

VSSCA

SYM 2 OF 2

BI

NC

IN

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10uF caps are shared between DRAM.

LPDDR3 CHANNEL A (32-63)

PLACEMENT_NOTE:

Distribute evenly.

70

X5R-CERM

20%

10UF

0603

25V

10V

X5R

402

10%

1UF

10V

X5R

402

1UF

10%

10V

402

1UF

10%

X5R

10UF

20%

25V

X5R-CERM

0603

70

20 24 70 76

201

MF

1/20W

1%

243

1%

243

1/20W

MF

201

10%

201

0.047UF

X5R

6.3V

70

201

0.047UF

10%

X5R

6.3V

25V

20%

10UF

X5R-CERM

0603

20%

25V

0603

10UF

X5R-CERM

25V

0603

10UF

20%

X5R-CERM

FBGA

CRITICAL

OMIT_TABLE

LPDDR3-1600-32GB

EDFB232A1MA

LPDDR3-1600-32GB

OMIT_TABLE

FBGA

CRITICAL

EDFB232A1MA

70

C0G-CERM

2%

12PF

50V

CRITICAL

0402

C0G-CERM

2%

0402

12PF

50V

CRITICAL

C0G-CERM

2%

12PF

50V

CRITICAL

0402

C0G-CERM

2%

12PF

50V

CRITICAL

0402

70

24 70 76

70

24 70 76

7

24 76

7

24 76

7

24 76

7

24 76

7

20 24 76

7

20 24 76

70

10%

1UF

402

X5R

10V

10%

1UF

402

X5R

10V

X5R

402

1UF

10%

10V

X5R

402

1UF

10%

70

25V

0603

10UF

20%

X5R-CERM

25V

0603

20%

X5R-CERM

10UF

10%

1UF

402

X5R

10V

0201

16V

X5R-CERM

0.1UF

10%

1UF

402

X5R

10V

0201

10%

X5R-CERM

16V

0.1UF

10%

1UF

402

X5R

10V

X5R

402

1UF

10%

10V

BOM_COST_GROUP=DRAM

SYNC_MASTER=J41_MLB

SYNC_DATE=02/06/2013

LPDDR3 DRAM Channel A (32-63)

MEM_A_CS_L<0>

MEM_A_CLK_N<1>

MEM_A_CS_L<1>

MEM_A_ZQ<2>

=PP1V2_S3_MEM_VDDCA

=PP1V2_S3_MEM_VDD2

=PP1V8_S3_MEM

=MEM_A_DQ<34>

=MEM_A_DQ<39>

=MEM_A_DQS_P<6>

=MEM_A_DQS_P<5>

=MEM_A_DQS_N<7>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<4>

=MEM_A_DQS_P<4>

=MEM_A_DQ<46>

=MEM_A_DQS_P<7>

=MEM_A_DQ<35>

=MEM_A_DQ<45>

=MEM_A_DQ<50>

=MEM_A_DQ<36>

=MEM_A_DQ<37>

=MEM_A_DQ<38>

=MEM_A_DQ<41>

=MEM_A_DQ<62>

=MEM_A_DQ<63>

=MEM_A_DQ<61>

=MEM_A_DQ<59>

=MEM_A_DQ<60>

=MEM_A_DQ<57>

=MEM_A_DQ<58>

=MEM_A_DQ<56>

=MEM_A_DQ<54>

=MEM_A_DQ<55>

=MEM_A_DQ<52>

=MEM_A_DQ<53>

=MEM_A_DQ<51>

=MEM_A_DQ<49>

=MEM_A_DQ<47>

=MEM_A_DQ<48>

=MEM_A_DQ<44>

=MEM_A_DQ<42>

=MEM_A_DQ<43>

=MEM_A_DQ<40>

=MEM_A_DQ<33>

=MEM_A_DQ<32>

MEM_A_CAB<7>

PP0V6_S3_MEM_VREFDQ_A

PP0V6_S3_MEM_VREFCA_A

MEM_A_CKE<3>

MEM_A_CAB<5>

MEM_A_CAB<4>

MEM_A_CAB<3>

MEM_A_CAB<1>

MEM_A_CAB<0>

MEM_A_CAB<6>

MEM_A_ODT<0>

MEM_A_CAB<2>

MEM_A_CAB<9>

MEM_A_CLK_P<1>

MEM_A_CKE<2>

MEM_A_CAB<8>

=PP1V8_S3_MEM

=PP1V2_S3_MEM_VDDQ

MEM_A_ZQ<3>

=PP1V2_S3_MEM_VDD2

=PP1V2_S3_MEM_VDDQ

=PP1V2_S3_MEM_VDDCA

C2430

1

2

C2431

1

2

C2410

1

2

C2411

1

2

C2432

1

2

C2412

1

2

C2420

1

2

C2400

1

2

C2421

1

2

C2401

1

2

C2422

1

2

C2402

1

2

C2423

1

2

C2403

1

2

C2404

1

2

C2405

1

2

C2406

1

2

R2400

1

2

R2401

1

2

C2440

1

2

C2441

1

2

C2433

1

2

C2407

1

2

C2424

1

2

U2400

R2

P2

N2

N3

M3

F3

E3

E2

D2

C2

J2

J3

K3

K4

L3

L4

L8

G8

P8

D8

P9

N9

F9

F8

E11

E10

E9

D9

T8

T9

T10

T11

N10

R8

R9

R10

R11

C11

C10

C9

C8

B11

B10

N11

B9

B8

M8

M9

M10

M11

F11

F10

L11

L10

G11

G10

P11

P10

D11

D10

C4

K9

R3

A1

A2

U12

U13

A12

A13

B1

B13

T1

T13

U1

U2

J8

H4

J11

B3

B4

U2400

A3

A4

A5

A6

A10

U3

U4

U5

U6

U10

A8

A9

J6

K5

K6

K12

L5

P4

P5

P6

U8

U9

D4

D5

D6

G5

H5

H6

H12

J5

F2

G2

H3

L2

M2

A11

C12

K8

K11

L12

N8

N12

R12

U11

E8

E12

G12

H8

H9

H11

J9

J10

B2

B5

N4

N5

R4

R5

T2

T3

T4

T5

H2

C5

E4

E5

F5

J12

K2

L6

M5

C3

D3

F4

G3

G4

P3

M4

J4

B6

B12

K10

L9

M6

M12

N6

P12

R6

T6

T12

C6

D12

E6

F6

F12

G6

G9

H10

C2434

1

2

C2435

1

2

C2436

1

2

C2437

1

2

dvt1

8.0.0

051-1573

21 OF 82

24 OF 120

20 21 22 23 68

20 68 76

20 21 22 23 68

BI

IN

BI

ZQ1

ZQ0

NC

DQ1

DQ22

NU

CA7

VREFDQ

VREFCA

DQS3_T

DQS1_T

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ31

DQ30

DQ3

DQ29

DQ28

DQ27

DQ26

DQ24

DQ23

DQ20

DQ2

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ12

DQ11

DQ10

DQ0

CKE1

CA5

CA4

CA3

CA1

CA0

CA6

CK_C

DQ25

DQS1_C

DQS0_C

ODT

CA2

DQS2_T

DQS0_T

CA9

DQ21

DQS3_C

DQS2_C

CK_T

CKE0

CA8

DM3

CS1*

DM0

DM1

DM2

CS0*

DQ13

SYM 1 OF 2

VSSQ

VSS

VDDQ

VDDCA

VDD2

VDD1

VSSCA

SYM 2 OF 2

BI

NC

IN

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Distribute evenly.

10uF caps are shared between DRAM.

LPDDR3 CHANNEL B (0-31)

PLACEMENT_NOTE:

70

20%

X5R-CERM

10UF

0603

25V

10%

1UF

402

X5R

10V

10%

1UF

402

X5R

10V

10%

1UF

402

X5R

10V

X5R-CERM

25V

20%

10UF

0603

70

23 24 70 76

201

MF

1/20W

1%

243

1%

243

1/20W

MF

201

0.047UF

X5R

6.3V

10%

201

0.047UF

10%

X5R

6.3V

70

10UF

20%

0603

25V

X5R-CERM

25V

0603

10UF

20%

X5R-CERM

10UF

0603

25V

X5R-CERM

20%

CRITICAL

OMIT_TABLE

LPDDR3-1600-32GB

FBGA

EDFB232A1MA

LPDDR3-1600-32GB

CRITICAL

OMIT_TABLE

FBGA

EDFB232A1MA

12PF

50V

CRITICAL

0402

2%

C0G-CERM

12PF

50V

CRITICAL

0402

2%

C0G-CERM

70

12PF

50V

CRITICAL

0402

2%

C0G-CERM

12PF

50V

CRITICAL

0402

2%

C0G-CERM

70

24 70 76

70

24 70 76

7

24 76

7

24 76

7

24 76

7

24 76

7

23 24 76

7

23 24 76

70

10V

X5R

402

1UF

10%

10V

X5R

402

1UF

10%

1UF

402

X5R

10V

10%

1UF

402

X5R

10V

70

X5R-CERM

20%

10UF

0603

25V

X5R-CERM

20%

10UF

0603

25V

X5R

402

1UF

10%

10V

10%

16V

0201

X5R-CERM

0.1UF

10V

X5R

402

1UF

10%

X5R-CERM

16V

10%

0201

0.1UF

10%

10V

X5R

402

1UF

10%

1UF

402

X5R

10V

BOM_COST_GROUP=DRAM

SYNC_DATE=02/06/2013

SYNC_MASTER=J41_MLB

LPDDR3 DRAM Channel B (00-31)

MEM_B_CS_L<0>

MEM_B_ODT<0>

=PP1V2_S3_MEM_VDDQ

=PP1V2_S3_MEM_VDDCA

=PP1V2_S3_MEM_VDD2

=PP1V8_S3_MEM

=MEM_B_DQ<10>

MEM_B_CLK_P<0>

=MEM_B_DQ<22>

=MEM_B_DQ<14>

=MEM_B_DQ<19>

=MEM_B_DQ<18>

=MEM_B_DQ<17>

=MEM_B_DQ<16>

=MEM_B_DQS_N<3>

=MEM_B_DQ<29>

=MEM_B_DQ<26>

=MEM_B_DQ<23>

=MEM_B_DQ<28>

=MEM_B_DQ<21>

=MEM_B_DQ<20>

=MEM_B_DQ<12>

=MEM_B_DQ<11>

=MEM_B_DQS_P<3>

=MEM_B_DQS_P<2>

=MEM_B_DQS_P<1>

=MEM_B_DQS_P<0>

=MEM_B_DQS_N<2>

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<0>

=MEM_B_DQ<31>

=MEM_B_DQ<30>

=MEM_B_DQ<27>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQ<15>

=MEM_B_DQ<13>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQ<7>

=MEM_B_DQ<6>

=MEM_B_DQ<5>

=MEM_B_DQ<4>

=MEM_B_DQ<3>

=MEM_B_DQ<2>

=MEM_B_DQ<1>

=MEM_B_DQ<0>

=PP1V2_S3_MEM_VDDQ

MEM_B_ZQ<1>

MEM_B_ZQ<0>

MEM_B_CAA<7>

PP0V6_S3_MEM_VREFDQ_B

PP0V6_S3_MEM_VREFCA_B

MEM_B_CKE<1>

MEM_B_CAA<5>

MEM_B_CAA<4>

MEM_B_CAA<3>

MEM_B_CAA<1>

MEM_B_CAA<0>

MEM_B_CAA<6>

MEM_B_CLK_N<0>

MEM_B_CAA<2>

MEM_B_CAA<9>

MEM_B_CKE<0>

MEM_B_CAA<8>

MEM_B_CS_L<1>

=PP1V2_S3_MEM_VDDCA

=PP1V8_S3_MEM

=PP1V2_S3_MEM_VDD2

C2530

1

2

C2531

1

2

C2510

1

2

C2511

1

2

C2532

1

2

C2512

1

2

C2520

1

2

C2500

1

2

C2521

1

2

C2501

1

2

C2522

1

2

C2502

1

2

C2523

1

2

C2503

1

2

C2504

1

2

C2505

1

2

C2506

1

2

R2500

1

2

R2501

1

2

C2540

1

2

C2541

1

2

C2533

1

2

C2507

1

2

C2524

1

2

U2500

R2

P2

N2

N3

M3

F3

E3

E2

D2

C2

J2

J3

K3

K4

L3

L4

L8

G8

P8

D8

P9

N9

F9

F8

E11

E10

E9

D9

T8

T9

T10

T11

N10

R8

R9

R10

R11

C11

C10

C9

C8

B11

B10

N11

B9

B8

M8

M9

M10

M11

F11

F10

L11

L10

G11

G10

P11

P10

D11

D10

C4

K9

R3

A1

A2

U12

U13

A12

A13

B1

B13

T1

T13

U1

U2

J8

H4

J11

B3

B4

U2500

A3

A4

A5

A6

A10

U3

U4

U5

U6

U10

A8

A9

J6

K5

K6

K12

L5

P4

P5

P6

U8

U9

D4

D5

D6

G5

H5

H6

H12

J5

F2

G2

H3

L2

M2

A11

C12

K8

K11

L12

N8

N12

R12

U11

E8

E12

G12

H8

H9

H11

J9

J10

B2

B5

N4

N5

R4

R5

T2

T3

T4

T5

H2

C5

E4

E5

F5

J12

K2

L6

M5

C3

D3

F4

G3

G4

P3

M4

J4

B6

B12

K10

L9

M6

M12

N6

P12

R6

T6

T12

C6

D12

E6

F6

F12

G6

G9

H10

C2534

1

2

C2535

1

2

C2536

1

2

C2537

1

2

051-1573

8.0.0

dvt1

25 OF 120

22 OF 82

20 21 22 23 68

23 68 76

20 21 22 23 68

BI

IN

BI

ZQ1

ZQ0

NC

DQ1

DQ22

NU

CA7

VREFDQ

VREFCA

DQS3_T

DQS1_T

DQ9

DQ8

DQ7

DQ6

DQ5

DQ4

DQ31

DQ30

DQ3

DQ29

DQ28

DQ27

DQ26

DQ24

DQ23

DQ20

DQ2

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ12

DQ11

DQ10

DQ0

CKE1

CA5

CA4

CA3

CA1

CA0

CA6

CK_C

DQ25

DQS1_C

DQS0_C

ODT

CA2

DQS2_T

DQS0_T

CA9

DQ21

DQS3_C

DQS2_C

CK_T

CKE0

CA8

DM3

CS1*

DM0

DM1

DM2

CS0*

DQ13

SYM 1 OF 2

VSSQ

VSS

VDDQ

VDDCA

VDD2

VDD1

VSSCA

SYM 2 OF 2

BI

NC

IN

BI

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

10uF caps are shared between DRAM.

Distribute evenly.

PLACEMENT_NOTE:

LPDDR3 CHANNEL B (32-63)

70

X5R-CERM

20%

10UF

0603

25V

10V

X5R

402

1UF

10%

10V

X5R

402

10%

1UF

X5R

1UF

402

10V

10%

X5R-CERM

10UF

20%

25V

0603

22 24 70 76

70

201

MF

1/20W

1%

243

1%

243

1/20W

MF

201

X5R

201

0.047UF

6.3V

10%

201

0.047UF

10%

X5R

6.3V

70

20%

X5R-CERM

25V

0603

10UF

0603

20%

10UF

25V

X5R-CERM

0603

10UF

20%

25V

0603

20%

25V

X5R-CERM

10UF

EDFB232A1MA

FBGA

CRITICAL

OMIT_TABLE

LPDDR3-1600-32GB

EDFB232A1MA

LPDDR3-1600-32GB

CRITICAL

OMIT_TABLE

FBGA

70

C0G-CERM

2%

0402

CRITICAL

50V

12PF

C0G-CERM

2%

0402

CRITICAL

50V

12PF

C0G-CERM

2%

0402

CRITICAL

50V

12PF

C0G-CERM

2%

0402

CRITICAL

50V

12PF

70

24 70 76

70

24 70 76

7

24 76

7

24 76

7

24 76

7

24 76

7

22 24 76

7

22 24 76

70

10%

1UF

402

X5R

10V

10%

1UF

402

X5R

10V

X5R

402

1UF

10%

402

X5R

10V

1UF

10%

70

25V

0603

10UF

20%

X5R-CERM

10%

1UF

402

X5R

10V

16V

X5R-CERM

0.1UF

10%

0201

10%

1UF

402

X5R

10V

X5R-CERM

16V

0201

10%

0.1UF

10%

1UF

402

X5R

10V

10%

10V

X5R

402

1UF

LPDDR3 DRAM Channel B (32-63)

SYNC_MASTER=J41_MLB

SYNC_DATE=02/06/2013

BOM_COST_GROUP=DRAM

MEM_B_ODT<0>

MEM_B_ZQ<2>

MEM_B_ZQ<3>

=PP1V2_S3_MEM_VDDQ

=PP1V2_S3_MEM_VDD2

=PP1V8_S3_MEM

=MEM_B_DQ<51>

=MEM_B_DQS_P<7>

=MEM_B_DQS_P<6>

=MEM_B_DQS_P<5>

=MEM_B_DQS_P<4>

=MEM_B_DQS_N<7>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<4>

=MEM_B_DQ<63>

=MEM_B_DQ<62>

=MEM_B_DQ<61>

=MEM_B_DQ<60>

=MEM_B_DQ<59>

=MEM_B_DQ<58>

=MEM_B_DQ<57>

=MEM_B_DQ<56>

=MEM_B_DQ<55>

=MEM_B_DQ<54>

=MEM_B_DQ<53>

=MEM_B_DQ<52>

=MEM_B_DQ<50>

=MEM_B_DQ<49>

=MEM_B_DQ<48>

=MEM_B_DQ<47>

=MEM_B_DQ<45>

=MEM_B_DQ<44>

=MEM_B_DQ<43>

=MEM_B_DQ<42>

=MEM_B_DQ<41>

=MEM_B_DQ<40>

=MEM_B_DQ<39>

=MEM_B_DQ<38>

=MEM_B_DQ<37>

=MEM_B_DQ<36>

=MEM_B_DQ<35>

=MEM_B_DQ<34>

=MEM_B_DQ<33>

=MEM_B_DQ<32>

MEM_B_CAB<7>

PP0V6_S3_MEM_VREFDQ_B

PP0V6_S3_MEM_VREFCA_B

MEM_B_CKE<3>

MEM_B_CAB<5>

MEM_B_CAB<4>

MEM_B_CAB<3>

MEM_B_CAB<1>

MEM_B_CAB<0>

MEM_B_CAB<6>

MEM_B_CLK_N<1>

MEM_B_CAB<2>

MEM_B_CAB<9>

MEM_B_CKE<2>

MEM_B_CAB<8>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

=PP1V2_S3_MEM_VDDCA

=MEM_B_DQ<46>

=PP1V2_S3_MEM_VDDCA

=MEM_B_DQS_N<5>

=PP1V8_S3_MEM

MEM_B_CLK_P<1>

=PP1V2_S3_MEM_VDDQ

=PP1V2_S3_MEM_VDD2

C2630

1

2

C2631

1

2

C2610

1

2

C2611

1

2

C2632

1

2

C2620

1

2

C2600

1

2

C2621

1

2

C2601

1

2

C2622

1

2

C2602

1

2

C2623

1

2

C2603

1

2

C2604

1

2

C2605

1

2

C2606

1

2

R2600

1

2

R2601

1

2

C2640

1

2

C2641

1

2

C2633

1

2

C2607

1

2

C2624

1

2

C2612

1

2

U2600

R2

P2

N2

N3

M3

F3

E3

E2

D2

C2

J2

J3

K3

K4

L3

L4

L8

G8

P8

D8

P9

N9

F9

F8

E11

E10

E9

D9

T8

T9

T10

T11

N10

R8

R9

R10

R11

C11

C10

C9

C8

B11

B10

N11

B9

B8

M8

M9

M10

M11

F11

F10

L11

L10

G11

G10

P11

P10

D11

D10

C4

K9

R3

A1

A2

U12

U13

A12

A13

B1

B13

T1

T13

U1

U2

J8

H4

J11

B3

B4

U2600

A3

A4

A5

A6

A10

U3

U4

U5

U6

U10

A8

A9

J6

K5

K6

K12

L5

P4

P5

P6

U8

U9

D4

D5

D6

G5

H5

H6

H12

J5

F2

G2

H3

L2

M2

A11

C12

K8

K11

L12

N8

N12

R12

U11

E8

E12

G12

H8

H9

H11

J9

J10

B2

B5

N4

N5

R4

R5

T2

T3

T4

T5

H2

C5

E4

E5

F5

J12

K2

L6

M5

C3

D3

F4

G3

G4

P3

M4

J4

B6

B12

K10

L9

M6

M12

N6

P12

R6

T6

T12

C6

D12

E6

F6

F12

G6

G9

H10

C2634

1

2

C2635

1

2

C2636

1

2

C2637

1

2

26 OF 120

051-1573

8.0.0

dvt1

23 OF 82

20 21 22 23 68

22 68 76

20 21 22 23 68

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Intel recommends 55 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

CERM-X5R-1

20%

0.47UF

201

4V

0.47UF

20%

CERM-X5R-1

201

CERM-X5R-1

201

4V

0.47UF

20%

4V

CERM-X5R-1

20%

0.47UF

201

CERM-X5R-1

20%

4V

0.47UF

20%

CERM-X5R-1

201

4V

0.47UF

CERM-X5R-1

0.47UF

201

20%

4V

201

0.47UF

20%

4V

CERM-X5R-1

0.47UF

4V

20%

CERM-X5R-1

201

20 70 76

7

20 76

7

20 76

7

20 76

7

21 76

21 70 76

20 70 76

7

20 76

20 70 76

21 70 76

20 70 76

21 70 76

20 70 76

21 70 76

CERM-X5R-1

0.47UF

201

4V

20%

22 70 76

CERM-X5R-1

4V

201

20%

0.47UF

CERM-X5R-1

201

20%

4V

0.47UF

CERM-X5R-1

201

20%

4V

CERM-X5R-1

201

0.47UF

20%

4V

0.47UF

20%

4V

201

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

0.47UF

201

20%

4V

CERM-X5R-1

201

20%

4V

0.47UF

201

CERM-X5R-1

0.47UF

4V

20%

CERM-X5R-1

201

0.47UF

20%

4V

22 70 76

7

22 76

7

22 76

7

22 76

7

22 76

22 70 76

23 70 76

7

23 76

7

23 76

7

23 76

7

23 76

23 70 76

7

21 76

7

21 76

7

21 76

23 70 76

7

22 23 76

7

22 23 76

22 23 70 76

20 70 76

7

20 21 76

7

20 21 76

20 21 70 76

201 MF1%

1/20W

56

MF201

39

1%

1/20W

39

MF1%

1/20W

201

82

MF1%

1/20W

201

82

1%

1/20W

201 MF

56

1%

1/20W

201 MF

56

1%

1/20W

39

201 MF1%

MF

1/20W

39

2011%

1%

201

1/20W

MF

82

1% 201

1/20W

82

MF

201

56

MF

1/20W

1%

1% 201

82

MF

1/20W

1% MF201

82

1/20W

82

1% 201 MF

1/20W

56

1% 201 MF

1/20W

39

1% 201 MF

1/20W

1% 201 MF

1/20W

39

1/20W

1% 201

82

MF

2011%

1/20W

MF

82

1/20W

56

1% MF201

56

1/20W

MF2011%

MF

1/20W

2011%

39

1/20W

MF2011%

39

MF

1/20W

2011%

82

MF2011%

1/20W

56

1% MF

1/20W

201

2011%

1/20W

82

MF

1% 201

1/20W

MF

82

1% 201

82

MF

1/20W

201

1/20W

MF1%

56

1%

56

201 MF

1/20W

603

22UF

CRITICAL

X5R-CERM-1

6.3V

20%

X5R-CERM-1

CRITICAL

20%

603

22UF

6.3V

MF2011%

1/20W

56

201 MF1%

1/20W

56

MF201

1/20W

1%

56

1%

1/20W

MF201

56

MF2011%

1/20W

56

201

1/20W

MF1%

56

MF201

1/20W

56

1%

1/20W

MF

56

2011%

201

1/20W

56

MF1%

201

1/20W

MF

56

1%

56

MF

1/20W

2011%

1%

56

1/20W

201 MF

1%

56

201

1/20W

MF

1%

56

1/20W

MF201

56

1% 201 MF

1/20W

1%

56

MF

1/20W

201

1% MF

1/20W

201

56

1/20W

1% MF201

56

1/20W

1% MF201

56

201

56

1/20W

MF1%

56

201

1/20W

MF1%

56

1% 201 MF

1/20W

56

201 MF1%

1/20W

56

201 MF1%

1/20W

56

201 MF1%

1/20W

201 MF1%

56

1/20W

1%

56

201

1/20W

MF

201

1/20W

MF

56

1%

56

201 MF

1/20W

1%

56

201 MF

1/20W

12PF

0201

NP0-C0G

5%

25V

0201

NP0-C0G

25V

5%

12PF

LPDDR3 DRAM Termination

SYNC_DATE=02/06/2013

SYNC_MASTER=J41_MLB

BOM_COST_GROUP=DRAM

=PP0V6_S0_MEM_VTT_A

MEM_B_CAB<5>

MEM_B_ODT<0>

MEM_B_CS_L<1>

MEM_B_CAB<4>

MEM_B_CAB<6>

MEM_B_CAB<7>

MEM_B_CAB<8>

MEM_B_CAA<0>

MEM_B_CAA<4>

MEM_B_CAB<0>

MEM_B_CAB<2>

MEM_B_CAB<9>

MEM_A_CAB<6>

MEM_A_CAA<2>

MEM_A_CAA<4>

MEM_A_CLK_N<1>

MEM_B_CAB<1>

MEM_A_CLK_P<1>

MEM_A_CAB<5>

MEM_A_CAB<8>

MEM_A_CAA<3>

MEM_A_CKE<1>

MEM_A_CLK_N<0>

MEM_A_CKE<0>

MEM_A_CAB<0>

MEM_A_ODT<0>

MEM_A_CAB<3>

MEM_A_CAB<2>

MEM_A_CKE<2>

MEM_B_CLK_P<0>

MEM_B_CAB<3>

MEM_A_CLK_P<0>

MEM_A_CAA<5>

MEM_B_CKE<3>

MEM_B_CS_L<0>

MEM_A_CKE<3>

MEM_A_CAB<7>

MEM_A_CAA<1> MEM_B_CAA<1>

MEM_B_CAA<3>

MEM_B_CAA<2>

MEM_A_CAA<9>

MEM_A_CAA<8>

MEM_A_CAA<6>

MEM_A_CAA<7>

MEM_A_CAA<0>

MEM_A_CAB<9>

MEM_B_CKE<2>

MEM_B_CLK_N<1>

MEM_B_CAA<6>

MEM_B_CAA<7>

MEM_B_CAA<9>

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_B_CLK_N<0>

MEM_B_CLK_P<1>

MEM_B_CAA<8>

MEM_B_CAA<5>

MEM_A_CAB<4>

MEM_A_CS_L<1>

MEM_A_CAB<1>

MEM_A_CS_L<0>

=PP0V6_S0_MEM_VTT_B

C2702

1

2

C2704

1

2

C2700

1

2

C2701

1

2

C2703

1

2

C2706

1

2

C2705

1

2

C2707

1

2

C2709

1

2

C2708

1

2

C2712

1

2

C2714

1

2

C2716

1

2

C2718

1

2

C2719

1

2

C2717

1

2

C2715

1

2

C2713

1

2

C2711

1

2

C2710

1

2

R2704

12

R2705

12

R2706

12

R2707

12

R2708

12

R2709

12

R2710

12

R2719

12

R2720

12

R2721

12

R2722

12

R2723

12

R2728

12

R2729

12

R2730

12

R2744

12

R2745

12

R2746

12

R2747

12

R2748

12

R2749

12

R2750

12

R2759

12

R2760

12

R2761

12

R2762

12

R2763

12

R2768

12

R2769

12

R2770

12

R2714

12

R2754

12

C2720

1

2

C2740

1

2

R2700

12

R2701

12

R2702

12

R2703

12

R2712

12

R2713

12

R2711

12

R2718

12

R2717

12

R2716

12

R2715

12

R2724

12

R2725

12

R2726

12

R2727

12

R2740

12

R2741

12

R2742

12

R2743

12

R2751

12

R2752

12

R2753

12

R2755

12

R2756

12

R2757

12

R2758

12

R2764

12

R2765

12

R2766

12

R2767

12

C2730

1

2

C2731

1

2

dvt1

051-1573

8.0.0

27 OF 120

24 OF 82

68 68

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

IN

BI

OUT

IN

OUT

IN

OUT

BI

IN

OUT

BI

IN

OUT

IN

OUT

VCC

DO/IO1

GND

THRM_PAD

CS*

CLK

WP*

HOLD*

DI/IO0

IN

OUT

IN

MISC

PCIE GEN2

SYM 1 OF 2

PORTS

DISPLAY PORT

DPSNK1_1_P

DPSNK1_1_N

DPSRC_AUX_N

DPSRC_AUX_P

XTAL_25_OUT

REFCLK_100_IN_N

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_CIO3_TX_N/DPSRC_2_N

PB_CIO3_RX_N

PB_CIO2_TX_N/DPSRC_0_N

PB_CIO2_RX_N

PB_AUX_N

PA_DPSRC_3_N

PA_DPSRC_1_N

PA_CIO1_TX_N/DPSRC_2_N

PA_CIO1_RX_N

PA_CIO0_TX_N/DPSRC_0_N

PA_CIO0_RX_N

PA_AUX_N

GPIO_8/EN_CIO_PWR_N_OD

DPSRC_3_N

DPSRC_2_N

DPSRC_1_N

DPSRC_0_N

DPSNK1_AUX_N

DPSNK1_3_N

DPSNK1_2_N

DPSNK1_0_N

DPSNK0_AUX_N

DPSNK0_3_N

DPSNK0_2_N

DPSNK0_1_N

DPSNK0_0_N

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

PETN_0

PETP_0

PETP_1

PETN_1

PETP_2

RSENSE

PETN_2

PETP_3

PETN_3

RBIAS

PCIE_CLKREQ_OD_N

REFCLK_100_IN_P

GPIO_16/DEVICE_PCIE_RST_N

RSVD_GND

GPIO_19

GPIO_18

GPIO_17

XTAL_25_IN

TMU_CLK_OUT

GPIO_2/TMU_CLK_IN/AC_PRESENT

DPSRC_HPD_OD

DPSRC_2_P

DPSRC_3_P

DPSRC_1_P

DPSRC_0_P

GPIO_3/FORCE_PWR

GPIO_4/WAKE_OD_N

GPIO_6_OD/CIO_SDA_OD

GPIO_7_OD/CIO_SCL_OD

GPIO_9/SX_CTRL_OD*

PB_CIO2_RX_P

PB_CIO2_TX_P/DPSRC_0_P

PB_CIO3_TX_P/DPSRC_2_P

PB_CONFIG1/CIO_2_LSEO

PB_CONFIG2/CIO_2_LSOE

GPIO_15

GPIO_14

GPIO_1/PB_HV_EN/BYP0

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

PB_CIO3_RX_P

PB_DPSRC_1_P

PB_DPSRC_3_P

PB_DPSRC_HPD

PB_LSTX/CIO_3_LSEO

PB_LSRX/CIO_3_LSOE

PB_AUX_P

PERP_0

PERP_1

PERN_1

PERP_2

PERN_2

PERN_3

PWR_ON_POC_RSTN

MONDC1

MONDC0

EE_DI

THERMDA

MONOBSN

MONOBSP

EE_DO

EE_CLK

TCK

TDO

TEST_EN

TEST_PWR_GOOD

EE_CS_N

DPSNK0_3_P

DPSNK0_2_P

DPSNK0_1_P

DPSNK0_0_P

DPSNK0_HPD

DPSNK0_AUX_P

DPSNK1_3_P

DPSNK1_2_P

DPSNK1_HPD

DPSNK1_AUX_P

DPSNK1_0_P

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_P/DPSRC_2_P

PA_CIO0_TX_P/DPSRC_0_P

PA_DPSRC_3_P

PA_DPSRC_1_P

PA_CIO1_RX_P

PA_DPSRC_HPD

PA_AUX_P

PA_LSTX/CIO_1_LSEO

PA_LSRX/CIO_1_LSOE

GPIO_12/PA_DP_PWRDN/BYP2

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

PERST_OD_N

TDI

TMS

PERN_0

PERP_3

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

87 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Security strap setting is XORed with

Use AA8 GND ball for THERM_DN

depends on the code in the flash.

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

4 - GPIO_5

DEBUG: For monitoring current/voltage

SNK0 AC Coupling

SNK1 AC Coupling

(TBT_SPI_MISO)(TBT_SPI_MOSI)

(TBT_SPI_CLK)

(TBT_SPI_CS_L)

DEBUG: For monitoring clock

Divides 3.3V to 1.8V

NOTE: The following pins require testpoints:

8 - GPIO_15

9 - GPIO_11

15 - PB_LSRX

14 - PB_LSTX

13 - GPIO_10

12 - GPIO_12

10 - GPIO_14

11 - GPIO_0

5 - PCIE_RST_1_N

0 - GPIO_13

3 - GPIO_3

2 - GPIO_2

1 - GPIO_1

7 - PCIE_RST_3_N

6 - PCIE_RST_2_N

bit in the flash, so the active-level

If strap != bit then security is enabled?

Used for straps in host mode

5%

3.3K

201

1/20W

MF

13

67

201

1/20W

MF

5%

100

28

28 71 77

28

28 71 77

29

29 71 77

29

29 71 77

5%

100K

201

1/20W

MF

5%

100K

201

1/20W

MF

28 77

5%

3.3K

201

1/20W

MF

10% 16V

X5R-CERM

0.1UF

0201

13 77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

5

77

16V10%

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

16V10%

0.1UF

X5R-CERM

0201

10% 16V

X5R-CERM

0.1UF

0201

16V10%

X5R-CERM

0.1UF

0201

MF

1/20W

201

1%

1K

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

0.1UF

X5R-CERM

0201

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

0201

10% 16V

0.1UF

X5R-CERM

0201

67 77

402

CERM

6.3V

10%

1UF

BYPASS=U2890::2mm

67 77

28

29

18

29 77

29

18

28 77

28

25 27 28

28

25 28

25 29 30

29

25 29

25 26

39

12

17 74

806

1%

1/20W

201

MF

201

1/20W

5%

1K

MF

201

10K

1/20W

5%

MF

NO STUFF

12 71 81

26

0201

OMIT

NONE

NOSTUFF

NONE

MF

1/20W

201

10K

5% 5%

1/20W

MF

201

10K

MF

1/20W

201

5%

NO STUFF

MF

1/20W

201

10K

5%

NO STUFF

5%

201

1/20W

MF

100K

15

25 30

18 75

100K

MF

1/20W

201

5%

CRITICAL

OMIT_TABLE

W25X40CLXIG

USON

4MBIT

25 27

25 28 29

MF

1/20W

201

10K

5% 5%

201

1/20W

MF

10K

NO STUFF

5%

10K

1/20W

MF

201

5%

201

1/20W

MF

10K

100K

5%

201

1/20W

MF

5%

MF

1/20W

201

10K

5%

201

1/20W

MF

100K

5%

201

1/20W

MF

25 69

5%

201

1/20W

MF

100K 100K

MF

1/20W

201

5%

100K

MF

1/20W

201

5%

FALCON RIDGE

OMIT_TABLE

CRITICAL

FCBGA

X5R-CERM

16V

10%

0201

0.1UF

X5R-CERM

16V

0.1UF

10%

0201

X5R-CERM

16V

0.1UF

10%

0201

0.1UF

X5R-CERM

16V

10%

0201

5%

3.3K

201

1/20W

MF

16V

0201

X5R-CERM

10%

0.1UF

X5R-CERM

16V

10%

0.1UF

0201

X5R-CERM

16V

0.1UF

10%

0201

X5R-CERM

16V

0.1UF

10%

0201

0.1UF

X5R-CERM

10% 16V

0.1UF

0201

10% 16V

X5R-CERM

0201

0.1UF

X5R-CERM

10% 16V

5%

3.3K

201

1/20W

MF

0201

0.1UF

X5R-CERM

10% 16V

0201

10% 16V

X5R-CERM

0.1UF

0201

X5R-CERM

0.1UF

10% 16V

X5R-CERM

0201

0.1UF

10% 16V

0201

X5R-CERM

16V10%

0.1UF

14 71 81

BOM_COST_GROUP=TBT

SYNC_MASTER=T29_RR

SYNC_DATE=01/19/2013

Thunderbolt Host (1 of 2)

TBT_SPI_MOSI

DP_TBTSRC_HPD

TP_DP_TBTSRC_ML_CN<3>

DP_TBTSRC_HPD

=PP3V3_S4_TBT

TBT_EN_CIO_PWR_L

HDMITBTMUX_SEL_TBT

TBT_DDC_XBAR_EN_L

TBTDP_AUXIO_EN

=PP3V3_S4_TBT

=TBT_BATLOW_L

TBT_B_HV_EN

TBT_A_DP_PWRDN

TBTROM_WP_L

TBTROM_HOLD_L

PCIE_TBT_D2R_P<2>

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK1_ML_C_P<3>

PCIE_TBT_D2R_P<3>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_P<0>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<0>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_P<0>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_AUXCH_N

PCIE_TBT_R2D_C_N<3>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK0_ML_P<3>

PCIE_TBT_R2D_C_P<3>

DP_TBTSNK0_ML_C_P<0>

PP3V3_TBTLC

PCIE_TBT_R2D_C_N<0>

TBT_A_HV_EN

TBT_B_DP_PWRDN

PP3V3_TBTLC

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_N<0>

PP3V3_TBTLC

PCIE_TBT_R2D_P<3>

JTAG_TBT_TMS

JTAG_TBT_TDI

TBT_PCIE_RESET_L

TBT_A_HV_EN

TBT_A_CIO_SEL

TBT_A_DP_PWRDN

TBT_A_LSRX

TBT_A_LSTX

DP_TBTPA_AUXCH_C_P

DP_TBTPA_HPD

TBT_A_D2R_P<1>

DP_TBTPA_ML_C_P<1>

DP_TBTPA_ML_C_P<3>

TBT_A_R2D_C_P<0>

TBT_A_R2D_C_P<1>

TBT_A_CONFIG1_BUF

TBT_A_CONFIG2_RC

TBT_A_D2R_P<0>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_HPD

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_HPD

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_P<3>

TBT_SPI_CS_L

TBT_TEST_PWR_GOOD

TBT_TEST_EN

JTAG_TBT_TDO

JTAG_TBT_TCK

TBT_SPI_CLK

TBT_SPI_MISO

TBT_MONOBSP

TBT_MONOBSN

TP_TBT_MONDC0

TP_TBT_MONDC1

TBT_PWR_ON_POC_RST_L

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_N<2>

PCIE_TBT_R2D_N<1>

PCIE_TBT_R2D_P<1>

PCIE_TBT_R2D_P<0>

DP_TBTPB_AUXCH_C_P

TBT_B_LSRX

TBT_B_LSTX

DP_TBTPB_HPD

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML_C_P<1>

TBT_B_D2R_P<1>

TBT_B_DP_PWRDN

TBT_B_CIO_SEL

TBT_B_HV_EN

TBTDP_AUXIO_EN

TBT_DDC_XBAR_EN_L

TBT_B_CONFIG2_RC

TBT_B_CONFIG1_BUF

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_P<0>

TBT_B_D2R_P<0>

=TBT_BATLOW_L

HDMITBTMUX_SEL_TBT

=TBT_WAKE_L

TBT_PWR_EN

TP_DP_TBTSRC_ML_CP<0>

TP_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CP<3>

TP_DP_TBTSRC_ML_CP<2>

TBT_GPIO2

TBT_RBIAS

PCIE_TBT_D2R_C_P<3>

PCIE_TBT_D2R_C_N<2>

TBT_RSENSE

PCIE_TBT_D2R_C_P<2>

PCIE_TBT_D2R_C_N<1>

PCIE_TBT_D2R_C_P<1>

PCIE_TBT_D2R_C_P<0>

PCIE_TBT_D2R_C_N<0>

TBT_CIO_PLUG_EVENT_L

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_AUXCH_N

TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CN<2>

TBT_EN_CIO_PWR_L

DP_TBTPA_AUXCH_C_N

TBT_A_D2R_N<0>

TBT_A_R2D_C_N<0>

TBT_A_D2R_N<1>

TBT_A_R2D_C_N<1>

DP_TBTPA_ML_C_N<1>

DP_TBTPA_ML_C_N<3>

DP_TBTPB_AUXCH_C_N

TBT_B_D2R_N<0>

TBT_B_R2D_C_N<0>

TBT_B_D2R_N<1>

TBT_B_R2D_C_N<1>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_N<3>

PCIE_CLK100M_TBT_N

TP_DP_TBTSRC_AUXCH_CP

TP_DP_TBTSRC_AUXCH_CN

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<1>

PCIE_TBT_R2D_N<0>

SYSCLK_CLK25M_TBT

PCIE_TBT_D2R_C_N<3>

PCIE_TBT_R2D_P<2>

TP_TBT_THERM_DP

TP_TBT_XTAL25OUT

TBT_TMU_CLK_OUT

TBT_GPIO7

SYSCLK_CLK25M_TBT_R

PCIE_TBT_D2R_N<3>

PCIE_CLK100M_TBT_P

TP_TBT_PCIE_RESET0_L

TBT_DFT_STRAP_1

TBT_ROM_SECURITY_XOR

TBT_DFT_STRAP_3

TBT_CLKREQ_L

R2890

1

2

C2890

1

2

R2892

1

2

R2891

1

2

R2855

1

2

C2801

12

C2800

12

C2802

12

C2803

12

C2804

12

C2805

12

C2806

12

C2807

12

C2840

12

C2841

12

C2842

12

C2843

12

C2845

12

C2844

12

C2846

12

C2847

12

R2825

1

2

R2830

1

2

R2831

1

2

R2893

1

2

C2829

12

C2828

12

C2827

12

C2826

12

C2825

12

C2824

12

C2823

12

C2822

12

C2821

12

C2820

12

C2830

12

C2831

12

C2832

12

C2833

12

C2834

12

C2835

12

C2836

12

C2837

12

C2838

12

C2839

12

R2895

12

R2896

1

2

R2899

1

2

R2815

1

2

R2888

1

2

R2887

1

2

R2886

1

2

R2885

1

2

R2880

1

2

R2883

1

2

U2890

6

1

52

4

7

9

8

3

R2861

1

2

R2863

1

2

R2867

1

2

R2862

1

2

R2881

1

2

R2829

1

2

R2884

1

2

R2882

1

2

R2878

1

2

R2879

1

2

R2832

1

2

U2800

D19

E20

D17

E18

D15

E16

D13

E14

G2

G4

AB5

D11

E12

D9

E10

D7

E8

D5

E6

H1

H3

U4

B9

A8

B11

A10

B13

A12

B15

A14

J2

J4

AC2

U8

T5

AA2

Y3

R8

N2 R2

P3 F3

T1

T3

W6

AB3

AD3

V1

F1

U2

L6

H5

Y7

Y1

T7

V7

M7

AD23

AC24

W16

W18

L2

L4

E22

G22

E24

G24

J22

L22

J24

L24

P1

K5

B17

A16

B19

A18

M3

J6

N8

K1

K3

N22

R22

N24

R24

U22

W22

U24

W24

D3

M1

B21

A20

B23

A22

N6

P7

M5

V3

AA10

AB13

AA16

AB19

AB9

AA12

AB15

AA18

P5

AD7

AD11

AD15

AD19

AD5

AD9

AD13

AD17

R4

W20

AD21

AB21

U20

AD1

L8

AA6

W2

U6

R6

W8

AB7

AB1

AA4

AA24

AB23

25 OF 82

28 OF 120

8.0.0

051-1573

dvt1

77

25

69

25

25 26 27 68

25 26

25 69

25 30

25 28 29

25 26 27 68

25 27

25 29 30

25 28

25 77

18 25 26 68

25 27 28

25 29

18 25 26 68

71

81

25 77

77

69

71 81

71

81

71

81

69

71

81

71

81

71

81

71

81

71 81

81

25 77

69

25 77

71 81

71

81

71

81

45

69

74

69

Apple X304 Schematic