Samsung S5T8554B01-D0B0, S5T8554B01-S0B0, S5T8554B02-L0B0, S5T8557B01-D0B0, S5T8557B01-S0B0 Datasheet

1 CHIP CODEC

S5T8554B/7B

INTRODUCTION

The S5T8554B/7B are single-chip PCM encoders and decoders (PCM CODECs) and PCM line filters. These devices provide all the functions required to interface a full-duplex voice telephone circuit with a time-division-multiplex (TDM) system.

These devices are designed to perform the transmit encoding and receive decoding as well as the transmit and receive filtering functions in PCM system. They are intended to be used at the analog termination of a PCM line or trunk.

These devices provide the bandpass filtering of the analog signals prior to encoding and after decoding. These combination devices perform the encoding and decoding of voice and call progress tones as well as the signalling and supervision information.

FEATURES

•Complete CODEC and filtering system

•Meets or exceeds AT&T D3/D4 and CCITT specifications μ-Law: S5T8554B, A-Law: S5T8557B

16-CERDIP

16-DIP-300A

8−DIP−300

•On-chip auto zero, sample and hold, and precision voltage references

•Low power dissipation: 60mW (operating), 3mW (standby)

•± 5V operation

•TTL or CMOS compatible

•Automatic power down

ORDERING INFORMATION

	Device	Package	Operating Temperature
	S5T8554B02-L0B0	16-CERDIP	−25°C to 125°C
	S5T8557B02-L0B0
	S5T8554B01-D0B0	16-DIP-300A	−25°C to +70°C
	S5T8557B01-D0B0
	S5T8554B01-S0B0	16-SOP-BD300	−25°C to +70°C
	S5T8557B01-S0B0

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S5T8554B/7B

1 CHIP CODEC

PIN CONFIGURATION

V	BB	1		16	VF	X	I+
GNDA		2		15	VFXI-
VFRO		3		14	GSX
VCC		4	KT8554/7	13	TSX
			S5T8554B/7B
FSR		5		12	FSXS
DR		6		11	DX
BCLKR/CLKSEL		7		10	BCLKX
MCLKR/PDN		8		9	MCLKX

PIN DISCRIPTION

Pin No	Symbol	Description
1	VBB	VBB = −5V ± 5%
2	GNDA	Analog ground.
3	VFRO	Analog output of the receive power Amp.
4	VCC	VCC = +5 V ± 5%
5	FSR	Receive frame sync pulse. 8kHz pulse train
6	DR	PCM data input.
7	BLCKR/	Logic input which selects either 1.536MHz/1.544MHz or 2.048MHz for master clock
	CLKSEL	in normal operation and BCLKX is used for both TX and RX directions.
		Alternately direct clock input available, vary from 60kHz to 2.048MHz.
8	MCLKR/	When MCLKR is connected continuously high, the device is powered down.
	PDN	Normally connected continuously low, MCLKX is selected for all DAC timing.
		Alternately direct 1.536MHz/1.544MHz or 2.048MHz clock input available.
9	MCLKX	Must be 1.536MHz/1.544MHz or 2.048MHz.
10	BLCKX	May be vary from 64kHz to 2.048MHz but BCLKX is externally tied with MCLKX in
		normal operation.
11	DX	PCM data output.
12	FSX	TX frame sync pulse. 8kHz pulse train.
13	TSX	Changed from high to low during the encoder timeslot. Open drain output.
14	GSX	Analog output of the TX input amplifier. Used to set gain through external resistor.
15	VFXI−	Inverting input stage of the TX analog signal.
16	VFXI+	Non-inverting input stage of the TX analog signal.

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1 CHIP CODEC S5T8554B/7B

ABSOLUTE MAXIMUM RATING

Characteristic	Symbol	Value	Unit
Positive Supply Voltage	VCC	7	V
Negative Supply Voltage	VBB	−7	V
Voltage at Any Analog Input or Output	VI (A)	VCC + 0.3 ~ VBB - 0.3	V
Voltage at Any Digital Input or Output	VI (D)	VCC + 0.3 ~ GNDA - 0.3	V
Operating Temperature Range	Ta	−25 ~ +125	°C
Storage Temperature Range	TSTG	−65 ~ +150	°C
Lead Temperature (Soldering, 10 secs)	TLEAD	300	°C

ELECTRICAL CHARACTERISTICS

(Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C;

typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA)

Characteristic	Symbol	Test Conditions	Min.	Typ.	Max.	Unit
POWER DISSIPATION
Power-Down Current	ICC (DOWN)	No Load	−	0.5	1.5	mA
Power-Down Current	IBB (DOWN)	No Load	−	0.05	0.3	mA
Active Current	ICC (A)	No Load	−	6.0	9.0	mA
Active Current	IBB (A)	No Load	−	6.0	9.0	mA
DIGITAL INTERFACE
Input Low Voltage	VIL	−	−	−	0.6	V
Input High Voltage	VIH	−	2.2	−	−	V
Input Low Current	IIL	GNDA≤ VIN ≤ VIL, all digital input	−10	−	10	μA
Input High Current	IIH	VIH ≤ VIN ≤ VCC	−10	−	10	μA
Output Low Voltage	VOL	DX, IL = 3.2mA	−	−	0.4	V
		SIGR, IL = 1.0mA			0.4	V
		TSX, IL = 3.2mA, open drain			0.4	V
Output High Voltage	IO (HZ)	DX, IH = −3.2mA	2.4	−	−	V
		SIGR, IH = −1.0mA	2.4			V
Output Current in High	IO (HZ)	DX, GNDA ≤ VO ≤ VCC	−10	−	10	μA
Impedance State (Tri -state)
ANALOG INTERFACE WITH RECEIVE FILTER
Output Resistance	RO	Pin VFRO	−	1	3	Ω

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S5T8554B/7B

1 CHIP CODEC

ELECTRICAL CHARACTERISTICS

(Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C;

typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA)

Characteristic	Symbol	Test Conditions	Min.	Typ.	Max.	Unit
Load Resistance	RL	VFRO = ± 2.5V	600	−	−	Ω
Load Capacitance	CL	−	−	−	500	pF
Output DC Offset Voltage	VOO (RX)	−	−200	−	200	mV
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER
Input Leakage Current	ILKG	-2.5V≤V≤+2.5V, VFXI+ or VFXI-	−200	−	200	nA
Input Resistance	RI	-2.5V≤V≤+2.5V, VFXI+ or VFXI-	10	−	−	MΩ
Output Resistance	RO	Closed loop, unity gain	−	1	3	Ω
Load Resistance	RL	GSX	10	−	−	kΩ
Load Capacitance	CL	GSX	−	−	50	pF
Output Dynamic Range	VOD (TX)	GSX, RL≤10KW	± 2.8	−	−	V
Voltage Gain	GV	VFXI+ to GSX	5,000	−	−	V/N
Unity Gain Bandwidth	BW	−	1	2	−	MHz
Offset Voltage	VIO (TX)	−	−20	−	20	mV
Common-Mode Voltage	VCM (TX)	CMRRXA > 60dB	−2.5	−	2.5	V
Common-Mode Rejection Ratio	CMRR	DC Test	60	−	−	dB
Power Supply Rejection Ratio	PSRR	DC Test	60	−	−	dB

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1 CHIP CODEC

S5T8554B/7B

TIMING CHARACTERISTICS

(Unless otherwise noted, VCC = 5.0V ± 5%, VBB = −5.0V ± 5%, GNDA = 0V, Ta = 0°C to 70°C;

typical characteristics specified at VCC = 5.0V, VBB = −5.0V, Ta=25°C; all signals referenced to GNDA)

Characteristic	Symbol	Test Conditions	Min.	Typ.	Max.	Unit
Frequency of Master Clock	fMCK	Depends on the device used	−	1.536	−	nS
		and the BCLKR/CLKSEL Pin.		1.544
		MCLKX and MCLKR		2.048
Rise Time of Bit Clock	tR (BCK)	tPB = 488ns	−	−	50	nS
Fall Time of Bit Clock	tF (BCK)	tPB = 488ns	−	−	50	nS
Holding Time from Bit Clock	tH (LFS)	Long frame only	0	−	−	nS
Low to Frame Sync
Holding Time from Bit Clock	tH (RFS)	Short frame only	0	−	−	nS
High to Frame Sync
Set-Up Time from Frame Sync	tSU (FBCL)	Long frame only	80	−	−	nS
to Bit Clock Low
Delay Time from BCLKX High	tD (HDV)	Load = 150pF plse 2 LSTTL	0	−	180	nS
to Data Valid		loads
Delay Time to TSX Low	tD (TSXL)	Load = 150pF plse 2 LSTTL	−	−	140	nS
		loads
Delay Time from BCLKX Low to	tD (LDD)	−	50	−	165	nS
Data Output Disabled
Delay Time to Valid Data from	tD (VD)	CL = 0pF to 150pF	20	−	165	nS
FSX or BCLKX, Whichever
Comes Later
Set-Up Time from DR Valid to	tSU (DRBL)	−	50	−	−	nS
BCLKR/X Low
Hold Time from FSR/X Low to	tH (BLDR)	−	50	−	−	nS
DR Invalid
Set-Up Time from FSR/X to	tSU (FBLS)	Short frame sync pulse (1 or 2	50	−	−	nS
BCLKR/X Low		bit clock periods long) (Note 1)
Width of Master Clock High	tW (MCKH)	MCLKX and MCLKR	160	−	−	nS
Width of Master Clock Low	tW (MCKL)	MCLKX and MCLKR	160	−	−	nS
Rise Time of Master Clock	tR (MCK)	MCLKX and MCLKR	−	−	50	nS
Fall Time of Master Clock	tF (MCK)	MCLKX and MCLKR	−	−	50	nS
Set-Up Time from BCLKX High	tSU (BHMF)	First bit clock after the leading	−	−	−	−
(and FSX In Long Frame Sync		edge FSX
Mode) to MCLKX Falling Edge

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