Samsung S3C7528, S3C7534, S3C7538, S3C7524, S3P7528 Datasheet
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S3C7524/C7528/P7528/C7534/C7538/P7538 |
PRODUCT OVERVIEW |
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1 PRODUCT OVERVIEW
The S3C7524/C7528/C7534/C7538 single-chip CMOS microcontroller has been designed for high-performance using SAM 47 (Samsung Arrangeable Microcontrollers). SAM 47, Samsung's newest 4-bit CPU core is notable for its low energy consumption and low operating voltage.
You can select from two ROM sizes: 4K or 8K bytes
Except for the difference in ROM size, the features and functions of the S3C7524 and the S3C7528, the S3C7534 and the S3C7538 are identical.
With it's DTMF generator, watchdog timer function, and versatile 8-bit timer/counters, theS3C7524/C7528 /C5304/C5308 offers an excellent design solution for a wide variety of telecommunication applications.
Up to 35 pins of the available 42-pin SDIP or 44-pin QFP package for the S3C7524/C7528, and up to 23 pins of the available 30-pin SDIP or 32-pin SOP package for the S3C7534/C7538 can be assign to I/O. Six vectored interrupts for S3C7524/C7528 and four vectored interrupts for S3C7534/C7538 provide fast response to internal and external events. In addition, the S3C7524/C7528/C7534/C7538 's advanced CMOS technology provides for low power consumption and a wide operating voltage range.
OTP
The S3C7524/C7528 microcontroller is also available in OTP (One Time Programmable) version, S3P7528. The S3C7534/C7538 microcontroller is also available in OTP (One Time Programmable) version, S3P7538. The S3P7528/P7538 microcontroller has an on-chip 8K-byte one-time-programable EPROM instead of masked ROM. The S3P7528 is comparable to S3C7524/C7528, both in function and in pin configuration. Also, the S3P7538 is comparable to the S3C7534/C7538, both in function and in pin configuration.
1-1
PRODUCT OVERVIEW |
S3C7524/C7528/P7528/C7534/C7538/P7538 |
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FEATURES SUMMARY
Memory
∙768 × 4-bit RAM
∙4,096 × 8-bit ROM (S3C7524/C7534)
8,192 × 8-bit ROM (S3C7528/C7538)
35 I/O Pins
∙Input only: 4 pins (S3C7524/C7528)
1pins (S3C7534/C7538)
∙I/O: 23 pins (S3C7524/C7528)
14 pins (S3C7534/C7538)
∙N-channel open-drain I/O: 8 pins
Memory-Mapped I/O Structure
∙Data memory bank 15
DTMF Generator
∙16 dual-tone frequencies for tone dialing
8-Bit Basic Timer
∙Programmable interval timer
∙Watchdog timer
Two 8-Bit Timer/Counters
∙Programmable 8-bit timer
∙External event counter function
∙Arbitrary clock frequency output
Watch Timer
∙Real-time and interval time measurement
∙Four frequency outputs to the BUZ pin
Bit Sequential Carrier
∙Supports 8-bit serial data transfer in arbitrary format
Interrupts
∙3 external interrupt vectors (S3C7524/C7528)
1 external interrupt vectors (S3C7534/C7538)
∙3 internal interrupt vectors
∙2 quasi-interrupts
Power-Down Modes
∙Idle: Only CPU clock stops
∙Stop: System clock stops
Oscillation Sources
∙Crystal, or ceramic for main system clock
∙Main system clock frequency: 0.4–6.0 MHz (typical)
∙CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
∙0.95, 1.91, and 15.3 μs at 4.19 MHz
∙1.12, 2.23, 17.88 μs at 3.58 MHz
∙0.67, 1.33, 10.7 μs at 6.0 MHz
Operating Temperature
∙– 40 °C to 85 °C
Operating Voltage Range
∙2.0 V to 5.5 V
Package Types
∙42 SDIP, 44 QFP (S3C7524/C7528)
∙30 SDIP, 32 SOP (S3C7534/C7538)
1-2
S3C7524/C7528/P7528/C7534/C7538/P7538 |
PRODUCT OVERVIEW |
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BLOCK DIAGRAM
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INT0, INT1, INT2, INT4 |
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RESET |
Xin |
Xout |
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BASIC |
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8-BIT |
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TIMER |
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TIMER/ |
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COUNTER 0 |
INTERRUPT |
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WATCH |
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STACK |
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CONTROL |
CLOCK |
TIMER |
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8-BIT |
POINTER |
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BLOCK |
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TIMER/ |
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WATCH-DOG |
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COUNTER 1 |
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PROGRAM |
TIMER |
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P6.0–P6.3 / |
I/O PORT 6 |
INTERNAL |
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COUNTER |
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P1.0 / INT0 |
KS0–KS3 |
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INPUT |
P1.1 / INT1 |
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INTERRUPTS |
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PORT 1 |
P1.2 / INT2 |
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P7.0–P7.3 / |
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I/O PORT 7 |
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P1.3 / INT4 |
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KS4–KS7 |
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PROGRAM |
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INSTRUCTION DECODER |
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STATUS WORD |
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P2.0 / TCLO0 |
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P2.1 / TCLO1 |
P8.0–P8.3 |
I/O PORT 8 |
ARITHMETIC |
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I/O PORT 2 |
P2.2 / CLO |
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P2.3 / BUZ |
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P9.0–P9.2 |
I/O PORT 9 |
AND |
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FLAGS |
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P3.0 / TCL0 |
LOGIC UNIT |
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I/O PORT 3 |
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P3.1 / TCL1 |
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P3.2 |
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P3.3 |
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I/O PORT 4 |
P4.0 / BTCO |
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P4.1−P4.3 |
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768 x 4-BIT |
PROGRAM MEMORY |
I/O PORT 5 |
P5.0–P5.3 |
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DATA |
S3C7524/C7534: 4 KBytes |
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MEMORY |
S3C7528/C7538: 8 KBytes |
DTMF |
DTMF |
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GENERATOR |
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NOTE: S3C7534/C7538 does not use P1.1/INT1, P1.2/INT2, P1.3/INT3, P3.2, P3.3, INT1, INT2, |
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INT4, P8.0-P8.3, and P9.0-P9.2. |
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Figure 1–1. S3C7524/C7528 Simplified Block Diagram
1-3
PRODUCT OVERVIEW |
S3C7524/C7528/P7528/C7534/C7538/P7538 |
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PIN ASSIGNMENTS
P1.0 / INT0 |
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P1.1 / INT1 |
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P1.2 / INT2 |
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P1.3 / INT4 |
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P2.0 / TCLO0 |
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P2.1 / TCLO1 |
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S3C7524/C7528 |
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P2.2 / CLO |
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7 |
600)-SDIP-(42 |
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P2.3 / BUZ |
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P3.0 / TCL0 |
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P3.1 / TCL1 |
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VDD |
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11 |
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VSS |
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XOUT |
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XIN |
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TEST |
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P4.0 / BTCO |
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P4.1 |
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RESET |
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P3.2 |
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P3.3 |
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P4.2 |
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42 
P9.2
41 
P9.1
40 
P9.0
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DTMF
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P7.3 / KS7
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P7.2 / KS6
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P7.1 / KS5
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P7.0 / KS4
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P6.3 / KS3
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P6.2 / KS2
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P6.1 / KS1
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P6.0 / KS0
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P5.3
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P5.2
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P5.1
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P5.0
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P8.3
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P8.2
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P8.1
23 
P8.0
22 
P4.3
Figure 1–2. S3C7524/C7528 Pin Assignment Diagrams (42–SDIP)
1-4
S3C7524/C7528/P7528/C7534/C7538/P7538 |
PRODUCT OVERVIEW |
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P2.1 / TCLO1 |
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P2.0 / TCLO0 |
P1.3 / INT4 |
P1.2 / INT2 P1.1 / INT1 |
P1.0 / INT0 |
NC |
P9.2 |
P9.1 |
P9.0 |
DTMF |
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44 |
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41 40 |
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P2.2 / CLO |
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33 |
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P7.3 / KS7 |
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P2.3 / BUZ |
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32 |
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P7.2 / KS6 |
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P3.0 / TCL0 |
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31 |
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P7.1 / KS5 |
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P3.1 / TCL1 |
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30 |
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P7.0 / KS4 |
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VDD |
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5 |
KS57C5204/C5208 29 |
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P6.3 / KS3 |
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VSS |
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28 |
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P6.2 / KS2 |
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XOUT |
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(44-QFP-1010B) 27 |
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P6.1 / KS1 |
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XIN |
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P6.0 / KS0 |
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TEST |
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P5.3 |
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P4.0 / BTCO |
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P5.2 |
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P4.1 |
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P5.1 |
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RESET P3.2 |
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P3.3 |
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P4.2 NC P4.3 |
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P8.0 |
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P8.1 |
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P8.2 |
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P8.3 |
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P5.0 |
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Figure 1–3. S3C7524/C7528 Pin Assignment Diagrams (44–QFP)
1-5
PRODUCT OVERVIEW |
S3C7524/C7528/P7528/C7534/C7538/P7538 |
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VSS 
1 XOUT 
2
XIN 
3
TEST 
4 P4.0 / BTCO 
5 P4.1 
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RESET 
7 P4.2 
8 P4.3 
9 P5.0 
10 P5.1 
11 P5.2 
12 P5.3 
13
P6.0 / KS0 
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P6.1 / KS1 
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400)-SDIP-(30 |
S3C7534/C7538 |
30 |
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VDD |
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29 |
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P3.1 |
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P3.0 |
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27 |
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P2.3 |
/ BUZ |
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26 |
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P2.2 |
/ CLO |
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25 |
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P2.1 |
/ TCLO1 |
|
|||
|
|||
24 |
|
P2.0 |
/ TCLO0 |
|
|||
|
|||
23 |
|
P1.0 / INT0 |
|
|
|||
|
|||
22 |
|
DTMF |
|
|
|||
|
|||
21 |
|
P7.3 |
/ KS7 |
|
|||
|
|||
20 |
|
P7.2 |
/ KS6 |
|
|||
|
|||
19 |
|
P7.1 |
/ KS5 |
|
|||
|
|||
18 |
|
P7.0 |
/ KS4 |
|
|||
|
|||
17 |
|
P6.3 |
/ KS3 |
|
|||
|
|||
16 |
|
P6.2 |
/ KS2 |
|
|||
|
|||
|
|
|
|
Figure 1–4. S3C7534/C7538 Pin Assignment Diagrams (30–SDIP)
VSS 
1 XOUT 
2
XIN 
3
TEST 
4 P4.0 / BTCO 
5 P4.1 
6
RESET 
7 P4.2 
8 NC 
9
P4.3 
10
P5.0 
11
P5.1 
12
P5.2 
13
P5.3 
14
P6.0 / KS0 
15
P6.1 / KS1 
16
405A)-SOP-(32 |
S3C7534/C7538 |
32 |
|
VDD |
|
|
|
||
|
|
||
31 |
|
P3.1 |
/ TCL1 |
|
|||
|
|||
30 |
|
P3.0 |
/ TCL0 |
|
|||
|
|||
29 |
|
P2.3 |
/ BUZ |
|
|||
28 |
|
P2.2 |
/ CLO |
|
|||
|
|||
27 |
|
P2.1 |
/ TCLO1 |
|
|||
|
|||
26 |
|
P2.0 |
/ TCLO0 |
|
|||
|
|||
25 |
|
P1.0 / INT0 |
|
|
|||
24 |
|
NC |
|
|
|
||
23 |
|
DTMF |
|
|
|||
|
|||
22 |
|
P7.3 |
/ KS7 |
|
|||
|
|||
21 |
|
P7.2 |
/ KS6 |
|
|||
20 |
|
P7.1 |
/ KS5 |
|
|||
19 |
|
P7.0 |
/ KS4 |
|
|||
|
|||
18 |
|
P6.3 |
/ KS3 |
|
|||
|
|||
17 |
|
P6.2 |
/ KS2 |
|
|||
|
|
|
|
Figure 1–5. S3C7534/C7538 Pin Assignment Diagrams (32–SOP)
1-6
S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW
PIN DESCRIPTIONS
Table 1-1. S3C7524/C7528 Pin Descriptions
Pin |
Pin |
Reset |
Description |
Pin |
Share |
Circuit |
|
Name |
Type |
Value |
|
Number |
Pin |
Type |
|
|
|
|
|
|
|
|
|
P1.0 |
I |
I |
4-bit input port. |
1 (39) |
INT0 |
A-4 |
|
P1.1 |
|
|
1-bit and 4-bit read and test is possible. |
2 (40) |
INT1 |
|
|
P1.2 |
|
|
Each pull-up resistors are assignable by software. |
3 (41) |
INT2 |
|
|
P1.3 |
|
|
|
4 (42) |
INT4 |
|
|
|
|
|
|
|
|
|
|
P2.0 |
I/O |
I |
4-bit I/O port. |
5 (43) |
TCLO0 |
D-2 |
|
P2.1 |
|
|
1-bit and 4-bit read/write and test is possible. |
6 (44) |
TCLO1 |
|
|
P2.2 |
|
|
Individual pins are software configurable as input or |
7 |
(1) |
CLO |
|
P2.3 |
|
|
output. |
8 |
(2) |
BUZ |
|
|
|
|
|
|
|
|
|
P3.0 |
|
|
4-bit pull-up resistors are software assignable to input |
9 |
(3) |
TCL0 |
D-4 |
P3.1 |
|
|
pins and are automatically disabled for output pins. |
10 (4) |
TCL1 |
|
|
P3.2 |
|
|
Ports 2 and 3 can be paired to enable 8-bit data |
19 |
(13) |
|
|
P3.3 |
|
|
transfer. |
20 |
(14) |
|
|
|
|
|
|
|
|
|
|
P4.0 |
I/O |
I |
4-bit I/O ports. |
16 |
(10) |
BTCO |
E-2 |
P4.1 |
|
|
1-bit and 4-bit read/write and test is possible. |
17 |
(11) |
|
|
P4.2 |
|
|
Individual pins are software configurable as input or |
21 |
(15) |
|
|
P4.3 |
|
|
output. |
22 |
(17) |
|
|
|
|
|
4-bit pull-up resistors are software assignable to input |
|
|
|
|
P5.0–P5.3 |
|
|
pins and are automatically disabled for output pins. |
27–30 |
|
|
|
|
|
|
N-channel open-drain or push-pull output can be |
(22–25) |
|
|
|
|
|
|
selected by software (1-bit unit) |
|
|
|
|
|
|
|
Ports 4 and 5 can be paired to support 8-bit data |
|
|
|
|
|
|
|
transfer. |
|
|
|
|
|
|
|
|
|
|
|
|
P6.0–P6.3 |
I/O |
I |
4-bit I/O ports. |
31–34 |
KS0–KS3 |
D-4 |
|
|
|
|
1-bit or 4-bit read/write and test is possible. |
(26–29) |
|
|
|
P7.0–P7.3 |
|
|
Individual pins are software configurable as input or |
35–38 |
KS4–KS7 |
|
|
|
|
|
output. |
(30–33) |
|
|
|
|
|
|
4-bit pull-up resistors are software assignable to input |
|
|
|
|
|
|
|
pins and are automatically disabled for output pins. |
|
|
|
|
|
|
|
Ports 6 and 7 can be paired to enable 8-bit data |
|
|
|
|
|
|
|
transfer. |
|
|
|
|
|
|
|
|
|
|
|
|
P8.0–P8.3 |
I/O |
I |
4-bit I/O port. |
23–26 |
– |
D-2 |
|
|
|
|
1-bit or 4-bit read/write and test is possible. |
(18–21) |
|
|
|
P9.0–P9.2 |
|
|
Individual pins are software configurable as input or |
40–42 |
|
|
|
|
|
|
output. |
(35–37) |
|
|
|
|
|
|
4-bit pull-up resistors are software assignable to input |
|
|
|
|
|
|
|
pins and are automatically disabled for output pins. |
|
|
|
|
|
|
|
Ports 8 and 9 can be paired to enable 8-bit data |
|
|
|
|
|
|
|
transfer. |
|
|
|
|
|
|
|
|
|
|
|
|
1-7
PRODUCT OVERVIEW |
S3C7524/C7528/P7528/C7534/C7538/P7538 |
|
|
Table 1-1. S3C7524/C7528 Pin Descriptions (Continued)
Pin |
Pin |
Reset |
|
Description |
Pin |
Share |
Circuit |
Name |
Type |
Value |
|
|
Number |
Pin |
Type |
|
|
|
|
|
|
|
|
DTMF |
O |
– |
DTMF output. |
39 (34) |
– |
G-6 |
|
|
|
|
|
|
|
|
|
BTCO |
I/O |
I |
Basic timer clock output |
16 (10) |
P4.0 |
E-2 |
|
|
|
|
|
|
|
|
|
INT0 |
I |
I |
External interrupts. The triggering edge for INT0 and |
1 (39) |
P1.0 |
A-3 |
|
INT1 |
|
|
INT1 is selectable. |
2 (40) |
P1.1 |
|
|
|
|
|
|
|
|
|
|
INT2 |
I |
I |
Quasi-interrupt with detection of rising edges |
3 (41) |
P1.2 |
A-3 |
|
|
|
|
|
|
|
|
|
INT4 |
I |
I |
External interrupt with detection of rising and falling |
4 (42) |
P1.3 |
A-3 |
|
|
|
|
edges. |
|
|
|
|
|
|
|
|
|
|
|
|
TCLO0 |
I/O |
I |
Timer/counter 0 clock output |
5 (43) |
P2.0 |
D-2 |
|
|
|
|
|
|
|
|
|
TCLO1 |
I/O |
I |
Timer/counter 1 clock output |
6 (44) |
P2.1 |
D-2 |
|
|
|
|
|
|
|
|
|
CLO |
I/O |
I |
Clock output |
7 (1) |
P2.2 |
D-2 |
|
|
|
|
|
|
|
|
|
BUZ |
I/O |
I |
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at |
8 (2) |
P2.3 |
D-2 |
|
|
|
|
the watch timer clock frequency of 4.19 MHz for |
|
|
|
|
|
|
|
buzzer sound |
|
|
|
|
|
|
|
|
|
|
|
|
TCL0 |
I/O |
I |
External clock input for timer/counter 0 |
9 (3) |
P3.0 |
D-4 |
|
|
|
|
|
|
|
|
|
TCL1 |
I/O |
I |
External clock input for timer/counter 1 |
10 (4) |
P3.1 |
D-4 |
|
|
|
|
|
|
|
|
|
KS0–KS3 |
I/O |
I |
Quasi-interrupt inputs with falling edge detection |
31–34 |
P6.0– |
D-4 |
|
|
|
|
|
|
(26–29) |
P6.3 |
|
KS4–KS7 |
|
|
|
|
35–38 |
P7.0– |
|
|
|
|
|
|
(30–33) |
P7.3 |
|
|
|
|
|
|
|
|
|
VDD |
– |
– |
Power supply |
11 (5) |
– |
– |
|
VSS |
– |
– |
Ground |
12 (6) |
– |
– |
|
RESET |
– |
– |
RESET signal |
18 (12) |
– |
B |
|
|
|
|
|
|
|
|
|
Xin |
– |
– |
Crystal, or ceramic oscillator signal for main system |
14 (8) |
– |
– |
|
X |
|
|
clock. (For external clock input, use Xin and input |
13 (7) |
|
|
|
out |
|
|
X |
's reverse phase to X ) |
|
|
|
|
|
|
|
|
|
||
|
|
|
in |
out |
|
|
|
TEST |
– |
– |
Test signal input |
15 (9) |
– |
– |
|
|
|
|
|
|
|
|
|
NC |
– |
– |
No connection |
(16, 38) |
– |
– |
|
|
|
|
|
|
|
|
|
NOTE: Parentheses indicate pin number for 44 QFP package.
1-8
S3C7524/C7528/P7528/C7534/C7538/P7538 PRODUCT OVERVIEW
Table 1-2. S3C7534/C7538 Pin Descriptions
Pin |
Pin |
Description |
Pin |
Share |
Circuit |
|
Name |
Type |
|
Number |
Pin |
Type |
|
|
|
|
|
|
|
|
P1.0 |
I |
1-bit input port. |
23 |
(25) |
INT0 |
A-4 |
|
|
1-bit and 4-bit read and test is possible. |
|
|
|
|
|
|
Each bit pull-up resistors are assignable. |
|
|
|
|
|
|
|
|
|
|
|
P2.0 |
I/O |
4-bit I/O port. |
24 |
(26) |
TCLO0 |
D-2 |
P2.1 |
|
1-bit and 4-bit read/write and test is possible. |
25 |
(27) |
TCLO1 |
|
P2.2 |
|
Each individual pin can be assignable as input or |
26 |
(28) |
CLO |
|
P2.3 |
|
output. 4-bit pull-up resisters are software |
27 |
(29) |
BUZ |
|
|
|
assignable to input pins and are automatically |
|
|
|
|
|
|
disabled for output pins. |
|
|
|
|
P3.0 |
|
Ports 2 and 3 can be paired to enable 8-bit data |
28 |
(30) |
TCL0 |
D-4 |
P3.1 |
|
transfer. |
29 |
(31) |
TCL1 |
|
|
|
|
|
|
|
|
P4.0 |
I/O |
4-bit I/O ports. |
5 |
(5) |
BTCO |
E-2 |
P4.1 |
|
1-bit and 4-bit read/write and test is possible. |
6 |
(6) |
|
|
P4.2 |
|
Each individual pin can be assignable as input or |
8 |
(8) |
|
|
P4.3 |
|
output. 4-bit pull-up resisters are software |
9 (10) |
|
|
|
P5.0–P5.3 |
|
assignable to input pins and are automatically |
10–13 |
|
|
|
|
|
disabled for output pins. |
(11–14) |
|
|
|
|
|
The N-channel open-drain or push-pull output |
|
|
|
|
|
|
can be selected by software (1-bit unit). |
|
|
|
|
|
|
Ports 4 and 5 can be paired to enable 8-bit data |
|
|
|
|
|
|
transfer. |
|
|
|
|
|
|
|
|
|
|
|
P6.0–P6.3 |
I/O |
4-bit I/O ports. |
14–17 |
KS0–KS3 |
D-4 |
|
|
|
1-bit and 4-bit read/write and test is possible. |
(15–18) |
|
|
|
P7.0–P7.3 |
|
Each individual pin can be assignable as input or |
18–21 |
KS4–KS7 |
|
|
|
output. 4-bit pull-up resisters are software |
(19–22) |
|
|
||
|
|
|
|
|||
|
|
assignable to input pins and are automatically |
|
|
|
|
|
|
disabled for output pins. |
|
|
|
|
|
|
Ports 6 and 7 can be paired to enable 8-bit data |
|
|
|
|
|
|
transfer. |
|
|
|
|
|
|
|
|
|
|
|
1-9
PRODUCT OVERVIEW S3C7524/C7528/P7528/C7534/C7538/P7538
Table 1-1. S3C7534/C7538 Pin Descriptions (Continued)
Pin |
I/O |
Description |
Pin |
Share |
Circuit |
|
Name |
Type |
|
Number |
Pin |
Type |
|
|
|
|
|
|
|
|
DTMF |
O |
DTMF output. |
22 |
(23) |
– |
G-6 |
|
|
|
|
|
|
|
INT0 |
I |
External interrupt input. |
23 |
(25) |
P1.0 |
A-3 |
|
|
The triggering edge for INT0 is selectable. |
|
|
|
|
|
|
|
|
|
|
|
TCLO0 |
I/O |
Timer/counter 0 clock output |
24 |
(26) |
P2.0 |
D-2 |
|
|
|
|
|
|
|
TCLO1 |
I/O |
Timer/counter 1 clock output |
25 |
(27) |
P2.1 |
D-2 |
|
|
|
|
|
|
|
CLO |
I/O |
Clock output |
26 |
(28) |
P2.2 |
D-2 |
|
|
|
|
|
|
|
BUZ |
I/O |
2 kHz, 4 kHz, 8 kHz, or 16 kHz frequency output at the |
27 |
(29) |
P2.3 |
D-2 |
|
|
watch timer clock frequency of 4.19 MHz for buzzer |
|
|
|
|
|
|
sound |
|
|
|
|
|
|
|
|
|
|
|
TCL0 |
I/O |
External clock input for timer/counter 0 |
28 |
(30) |
P3.0 |
D-4 |
|
|
|
|
|
|
|
TCL1 |
I/O |
External clock input for timer/counter 1 |
29 |
(31) |
P3.1 |
D-4 |
|
|
|
|
|
|
|
BTCO |
I/O |
Basic timer clock output |
5 |
(5) |
P4.0 |
E-2 |
|
|
|
|
|
|
|
VDD |
– |
Power supply |
30 |
(32) |
– |
– |
VSS |
– |
Ground |
1 |
(1) |
– |
– |
Xin |
– |
Crystal, or ceramic oscillator signal for main system |
3 |
(3) |
– |
– |
X |
|
clock. (For external clock input, use Xin and input Xin's |
2 |
(2) |
|
|
out |
|
reverse phase to Xout) |
|
|
|
|
|
|
|
|
|
|
|
NC |
– |
No connection |
(9, 24) |
– |
– |
|
|
|
|
|
|
|
|
TEST |
– |
Test signal input |
4 |
(4) |
– |
– |
|
|
|
|
|
|
|
RESET |
– |
RESET signal |
7 |
(7) |
– |
B |
|
|
|
|
|
|
|
KS0–KS3 |
I/O |
Quasi-interrupt inputs with falling edge detection |
14–17 |
P6.0– |
D-4 |
|
|
|
|
(15–18) |
P6.3 |
|
|
KS4–KS7 |
|
|
18–21 |
P7.0– |
|
|
|
|
|
(19–22) |
P7.3 |
|
|
|
|
|
|
|
|
|
NOTE: Parentheses indicate the pin number for 32-SOP package.
1-10
S3C7524/C7528/P7528/C7534/C7538/P7538 |
PRODUCT OVERVIEW |
|
|
PIN CIRCUIT DIAGRAMS
VDD
P-CHANNEL
IN 
N-CHANNEL
Figure 1–6. Pin Circuit Type A
VDD
PULL-UP
RESISTOR
IN
SCHMITT TRIGGER
Figure 1–7. Pin Circuit Type B
VDD
PULL-UP
RESISTOR
RESISTOR
P-CHANNEL 
ENABLE
IN
SCHMITT TRIGGER
Figure 1–8. Pin Circuit Type A-4
VDD
P-CHANNEL
DATA
OUT
N-CHANNEL
OUTPUT
DISABLE
Figure 1–9. Pin Circuit Type C
1-11
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