Samsung S3C7335, S3P7335 Datasheet

S3C7335/P7335	PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

OVERVIEW

The S3C7335 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontrollers).

With features such as LCD direct drive capability, 4-channel A/D converter, 8-bit timer/counter, watch timer and PLL frequency synthesizer, it offers you an excellent design solution for a wide variety of applications that require LCD functions and audio applications.

Up to 56 pins of the 80-pin QFP package, it can be dedicated to I/O. Eight vectored interrupts provide fast response to internal and external events. In addition, the S3C7335's advanced CMOS technology provides for low power consumption and a wide operating voltage range.

OTP

The S3C7335 microcontroller is also available in OTP (One Time Programmable) version, S3P7335. The S3P7335 microcontroller has an on-chip 16-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P7335 is comparable to S3C7335, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW	S3C7335/P7335

FEATURES

Memory

∙512-nibble RAM

∙16K-byte ROM

I/O Pins

∙Input only: 4 pins

∙Output only: 28 pins

∙I/O: 24 pins

LCD Controller/Driver

∙Maximum 14-digit LCD direct drive capability

∙28 segment x 4 common signals

∙Display modes: Static, 1/2 duty (1/2 bias) 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)

8-Bit Basic Timer

∙Programmable interval timer functions

∙Watch-dog timer function

8-Bit Timer/Counter

∙Programmable 8-bit timer

∙External event counter

∙Arbitrary clock frequency output

∙External clock signal divider

∙Serial I/O interface clock generator

Watch Timer

∙Time interval generation

: 0.5 s, 3.9 ms at 32.768 kHz

∙Frequency outputs to BUZ pin

∙Clock source generation for LCD

8-Bit Serial I/O Interface

∙8-bit transmit/receive mode

∙8-bit receive mode

∙Data direction selectable (LSB-first or MSB-first)

∙Internal or external clock source

A/D Converter

∙4-channels with 8-bit resolution

Bit Sequential Carrier Buffer

∙Support 16-bit serial data transfer in arbitrary format

PLL Frequency Synthesizer

∙Level = 300 mVp-p (min)

∙AMVCO range = 0.5 MHz to 30 MHz

∙FMVCO range = 30 MHz to 150 MHz

16-Bit Intermediate Frequency (IF) Counter

∙Level = 300 mVp-p (min)

∙AMIF range = 100 kHz to 1 MHz

∙FMIF range = 5 MHz to 15 MHz

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S3C7335/P7335	PRODUCT OVERVIEW

FEATURES (Continued)

Interrupts

∙Four internal vectored interrupts

∙Four external vectored interrupts

∙Two quasi-interrupts

Memory-Mapped I/O Structure

∙Data memory bank 15

Three Power-Down Modes

∙Idle: Only CPU clock stops

∙Stop1: Main system or subsystem clock stops

∙Stop2: Main system and subsystem clock stop

∙CE low: PLL and IFC stop

Oscillation Sources

∙Crystal or ceramic oscillator for main system clock

∙Crystal for subsystem clock

∙Main system clock frequency: 4.5 MHz (Typ)

∙Subsystem clock frequency: 32.768 kHz (Typ)

∙CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

∙0.9, 1.8, 14.2 μs at 4.5 MHz

∙122 μs at 32.768 kHz (subsystem)

Operating Temperature

∙– 40 °C to 85 °C

Operating Voltage Range

∙ 1.8 V to 5.5 V at 3MHz

∙PLL/IFC operation: 2.5V to 3.5V or 4.0V to 5.5V

Package Type

∙80-pin QFP

1-3

PRODUCT OVERVIEW	S3C7335/P7335

BLOCK DIAGRAM

P0.0/BTCO		INT0-INT4			Basic	Watch	Watchdog
P0.1/TCLO0	I/O Port 0				Timer	Timer	Timer
P0.2/TCL0		RESET	XIN	XTIN
P0.3/BUZ		CE	XOUT	XTOUT
P1.0/INT0
							Timer/
P1.1/INT1	Input Port 1
P1.2/INT2							Counter 0
P1.3/INT4		Interrupt			Instruction		IF	AMIF
P2.0		Control	Clock		Register
							Counter	FMIF
P2.1	I/O Port 2	Block
P2.2							PLL	VCOAM
P2.3
					Program			VCOFM
P3.0						Synthesizer
		Internal			Counter			EO
P3.1	I/O Port 3	Interrupts						BIAS
P3.2
						LCD Driver/
P3.3								VLC0-VLC2
							Controller
	Serial				Program			COM0-COM3
		Instruction Decoder
	I/O Port				Status Word			P13.0-P13.3
		Arithmetic				Output Port		/SEG24-SEG27
								P12.0-P12.3
P4.0/SCK			and
							11,12,13	/SEG20-SEG23
		Logic Unit			Stack
P4.1/SO	I/O Port 4							P11.0-P11.3
P4.2/SI					Pointer
								/SEG16-SEG19
P4.3/CLO								P10.0-P10.3
P5.0/ADC0
								/SEG12-SEG15
P5.1/ADC1	I/O Port 5					Output Port		P9.0-P9.3
P5.2/ADC2								/SEG8-SEG11
P5.3/ADC3							7,8,9,10	P8.0-P8.3
		512 x 4-Bit			16K-Byte			/SEG4-SEG7
								P7.0-P7.3
		Data Memory			Program Memory
	A/D						I/O Port 6	/SEG0-SEG3
	Converter							P6.0-P6.3
								KS0-KS3

Figure 1-1. S3C7335 Simplified Block Diagram

1-4

S3C7335/P7335	PRODUCT OVERVIEW

PIN ASSIGNMENTS

		SCK0/.P4			3/INT4.P1			2/INT2.P1			1/INT1.P1			0/INT0.P1			3/BUZ.P0			2/TCL0.P0			1/TCLO0.P0			0/BTCO.P0			3.P3			2.P3			1.P3			0.P3		CE			E0				1DDV
		80			79			78			77			76			75			74			73			72			71			70			69			68		67			66			65
P4.1/SO		1																																												64				FMIF
P4.2/SI		2																																												63				AMIF
P4.3/CLO		3																																												62				VSS1
P5.0/ADC0		4																																												61				VCOAM
P5.1/ADC1		5																																												60				VCOFM
P5.2/ADC2		6																																												59				P2.3
P5.3/ADC3		7																																												58				P2.2
P6.0/KS0		8																																												57				P2.1
P6.1/KS1		9																																												56				P2.0
P6.2/KS2		10																																												55				SEG27/P13.3
P6.3/KS3		11																S3C7335																												54				SEG26/P13.2
VDD0		12																																												53				SEG25/P13.1
VSS0		13												(80-QFP-Top View)																																52				SEG24/P13.0
XOUT		14																																												51				SEG23/P12.3
XIN		15																																												50				SEG22/P12.2
TEST		16																																												49				SEG21/P12.1
XTIN		17																																												48				SEG20/P12.0
XTOUT		18																																												47				SEG19/P11.3
RESET		19																																												46				SEG18/P11.2
BIAS		20																																												45				SEG17/P11.1
VLC0		21																																												44				SEG16/P11.0
VLC1		22																																												43				SEG15/P10.3
VLC2		23																																												42				SEG14/P10.2
COM0		24																																												41				SEG13/P10.1
		25			26			27			28			29			30			31			32			33			34			35			36			37		38			39			40
		COM1			COM2			COM3			0.SEG0/P7			1.SEG1/P7			2.SEG2/P7			3.SEG3/P7			0.SEG4/P8			1.SEG5/P8			2.SEG6/P8			3.SEG7/P8			0.SEG8/P9			1.SEG9/P9		2.SEG10/P9			3.SEG11/P9				.SEG12/P10
																																														0

Figure 1-2. S3C7335 80-QFP Pin Assignment

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PRODUCT OVERVIEW S3C7335/P7335

PIN DESCRIPTIONS

Table 1-1. S3C7335 Pin Descriptions

	Pin Name	Pin	Description	Number	Share	Reset	Circuit
		Type			Pin	Value	Type
	P0.0	I/O	4-bit I/O port.	72	BTCO	Input	D-2
	P0.1		1-bit or 4-bit read, write, and test are possible.	73	TCLO0		D-2
	P0.2		Pull-up resistors can be configured by software.	74	TCL0		D-4
	P0.3			75	BUZ		D-2
	P1.0	I	4-bit input port.	76	INT0	Input	A-4
	P1.1		1-bit or 4-bit read and test are possible.	77	INT1
	P1.2		Pull-up resistors can be configured by software.	78	INT2
	P1.3			79	INT4
	P2.0-P2.3	I/O	4-bit I/O ports.	56-59	–	Input	D-2
	P3.0-P3.3		1-bit, 4-bit or 8-bit read, write and test are possible.	68-71
			Pull-up resistors can be configured by software.
			Ports 2 and 3 can be paired to support 8-bit data
			transfer.
	P4.0	I/O	4-bit I/O ports.	80	SCK	Input	D-4
	P4.1		1-bit, 4-bit or 8-bit read, write and test are possible.	1	SO		D-2
	P4.2		Pull-up resistors can be configured by software.	2	SI		D-4
	P4.3			3	CLO		D-2
	P5.0	I/O	Ports 4 and 5 can be paired to support 8-bit data	4	ADC0	Input	F-10
	P5.1		transfer.	5	ADC1
	P5.2			6	ADC2
	P5.3			7	ADC3
	P6.0	I/O	4-bit I/O port.	8	KS0	Input	D-7
	P6.1		1-bit, 4-bit or 8-bit read, write and test are possible.	9	KS1
	P6.2		Pull-up resistors can be configured by software.	10	KS2
	P6.3			11	KS3
	P7.0	O	1-bit or 4-bit output port.	28	SEG0	Output	H-28
	P7.1		Alternatively used for LCD segment output.	29	SEG1
	P7.2			30	SEG2
	P7.3			31	SEG3
	P8.0	O	1-bit or 4-bit output port.	32	SEG4	Output	H-28
	P8.1		Alternatively used for LCD segment output.	33	SEG5
	P8.2			34	SEG6
	P8.3			35	SEG7
	P9.0	O	1-bit or 4-bit output port.	36	SEG8	Output	H-28
	P9.1		Alternatively used for LCD segment output.	37	SEG9
	P9.2			38	SEG10
	P9.3			39	SEG11
	P10.0	O	1-bit or 4-bit output port.	40	SEG12	Output	H-28
	P10.1		Alternatively used for LCD segment output.	41	SEG13
	P10.2			42	SEG14
	P10.3			43	SEG15

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S3C7335/P7335 PRODUCT OVERVIEW

Table 1-1. S3C7335 Pin Descriptions (Continued)

	Pin Name	Pin	Description	Number	Share	Reset	Circuit
		Type			Pin	Value	Type
	P11.0	O	1-bit or 4-bit output port.	44	SEG16	Output	H-28
	P11.1		Alternatively used for LCD segment output.	45	SEG17
	P11.2			46	SEG18
	P11.3			47	SEG19
	P12.0	O	1-bit or 4-bit output port.	48	SEG20	Output	H-28
	P12.1		Alternatively used for LCD segment output.	49	SEG21
	P12.2			50	SEG22
	P12.3			51	SEG23
	P13.0	O	1-bit or 4-bit output port.	52	SEG24	Output	H-28
	P13.1		Alternatively used for LCD segment output.	53	SEG25
	P13.2			54	SEG26
	P13.3			55	SEG27
	COM0-	O	Common signal output for LCD display	24-27	–	Output	H
	COM3
	BIAS	I	LCD power control	20	–	Input	–
	VLC0	I	LCD power supply.	21	–	Input	–
	VLC1		Voltage dividing resistors are assignable by	22
			software	23
	VLC2
	VDD0	–	Main power supply	12	–	–	–
	VSS0	–	Main Ground	13	–	–	–
	RESET	I	System reset pin	19	–	Input	B
	XOUT	–	Crystal, or ceramic oscillator pin for main system	14	–	–	–
	XIN		clock. (For external clock input, use XIN and input	15
			XIN’s reverse phase to XOUT)
	XTOUT	–	Crystal oscillator pin for subsystem clock. (For	18	–	–	–
	XTIN		external clock input, use XTIN and input XTIN’s	17
			reverse phase to XTOUT)
	TEST	I	Test signal input (must be connected to VSS for	16	–	–	–
			normal operation)
	CE	I	Input pin for checking device power.	67	–	Input	B-5
			Normal operation is high level and PLL/IFC
			operation is stopped at low level.
	VCOFM	I	External VCOFM/AM signal inputs.	60	–	Input	B-4
	VCOAM			61
	EO	O	PLL’s phase error output	66	–	Output	A-2
	FMIF	I	FM/AM intermediate frequency signal inputs.	64	Input	–	B-4
	AMIF			63
	VDD1	–	PLL/IFC power supply	65	–	–	–
	VSS1	–	PLL/IFC ground	62	–	–	–

1-7

PRODUCT OVERVIEW S3C7335/P7335

Table 1-1. S3C7335 Pin Descriptions (Concluded)

Pin Name	Pin	Description	Number	Share	Reset	Circuit
	Type			Pin	Value	Type
BTCO	I/O	Basic timer overflow output signal	72	P0.0	Input	D-2
TCLO0	I/O	Timer/counter 0 clock output signal	73	P0.1	Input	D-2
TCL0	I/O	External clock input for timer/counter 0	74	P0.2	Input	D-4
BUZ	I/O	2,4,8 or 16 kHz frequency output for buzzer sound	75	P0.3	Input	D-2
		for 4.19 MHz main system clock or 32.768 kHz
		subsystem clock
INT0	I	External interrupt. The triggering edges	76	P1.0	Input	A-4
INT1		(rising/falling) are selectable. Only INT0 is	77	P1.1
		synchronized with system clock.
INT2	I	Quasi-interrupt with detection of rising edge signal.	78	P1.2
INT4	I	External interrupt input with detection of rising or	79	P1.3
		falling edges.
SCK	I/O	SIO interface clock signal	80	P4.0	Input	D-4
SI	I/O	SIO interface data input signal	1	P4.2
SO	I/O	SIO interface data output signal	2	P4.1
CLO	I/O	CPU clock output	3	P4.3
KS0-KS3	I/O	Quasi-interrupt input with falling edge detection	8-11	P6.0-	Input	D-7
				P6.3
ADC0-	I/O	ADC input ports.	4-7	P5.0-	Input	F-10
ADC3				P5.3
SEG0-	O	LCD segment signal output.	28-31	P7.0-	Output	H-28
SEG3				P7.3
SEG4-	O	LCD segment signal output.	32-55	P8-P13	Output	H-28
SEG27

1-8

S3C7335/P7335	PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

VDD

P-Channel

In

N-Channel

Figure 1-3. Pin Circuit Type A

VDD

Up P-Channel

Out

Down N-Channel

Figure 1-4. Pin Circuit Type A-2(EO)

VDD

Pull-Up

Enable

In

Figure 1-5. Pin Circuit Type A-4 (P1)

VDD

Pull-Up

Resistor

In

Schmitt Trigger

Figure 1-6. Pin Circuit Type B (RESET)

In

Type A

Feedback

Enable

N-CH Pull-Down

Enable

Figure 1-7. Pin Circuit Type B-4

In

Figure 1-8. Pin Circuit Type B-5(CE)

1-9

PRODUCT OVERVIEW	S3C7335/P7335

	VDD
Data	P-Channel
	Out
Output	N-Channel
Disable

Figure 1-9. Pin Circuit Type C

VDD

	Pull-up		P-Channel
	Enable
	Data	Circuit
			I/O
	Output	Type C
	Disable

Figure 1-10. Pin Circuit Type D-2

VDD

	Pull-up		P-Channel
	Enable
	Data	Circuit
			I/O
	Output	Type C
	Disable
		Schmitt Trigger

Figure 1-11. Pin Circuit Type D-4

VDD

Pull-up		P-Channel
Enable
Data	Circuit	I/O
Output	Type C
Disable
		Port
		Enable
	Schmitt Trigger

Figure 1-12. Pin Circuit Type D-7 (P6)

1-10

S3C7335/P7335	PRODUCT OVERVIEW

		VDD
	Pull-up
	Enable
	Data	Circuit
	Output
		Type C
	Disable	I/O
	ADCEN

ADC Select

Data

TO ADC

Figure1-13. Pin Circuit Type F-10 (P5)

VLC0
VLC1
SEG	Out
Output
Disable
VLC2

Figure 1-15. Pin Circuit Type H-4

VLC0
		PNE	VDD
VLC1
			P-CH
LCD	Data		Output
	Out
COM			N-CH
	Output
	DIsable

VLC2	Circuit
SEG	Type H-4

Figure 1-14. Pin Circuit Type H (COM0-COM3)

Figure 1-16. Pin Circuit Type H-28 (P7-P13)

1-11

S3C7335/P7335	ELECTRICAL DATA

17 ELECTRICAL DATA

OVERVIEW

In this section, information on S3C7335 electrical characteristics is presented as tables and graphics. The information is arranged in the following order:

Standard Electrical Characteristics

—Absolute maximum ratings

—D.C. electrical characteristics

—System clock oscillator characteristics

—I/O capacitance

—A.C. electrical characteristics

—Operating voltage range

Miscellaneous Timing Waveforms

—A.C timing measurement point

—Clock timing measurement at XIN

—Clock timing measurement at XTIN

—Input timing for RESET

—Input timing for external interrupts and Quasi-Interrupts

Stop Mode Characteristics and Timing Waveforms

—RAM data retention supply voltage in stop mode

—Stop mode release timing when initiated by RESET

—Stop mode release timing when initiated by an interrupt request

17-1

ELECTRICAL DATA S3C7335/P7335

			Table 17-1. Absolute Maximum Ratings
(T	A	= 25 °C)
		Parameter	Symbol	Conditions		Rating			Units
Supply voltage			VDD	–	- 0.3		to	+ 6.5	V
Input voltage			VIN	Applies to all I/O ports	- 0.3	to	VDD + 0.3
Output voltage			VO	–	- 0.3	to	VDD + 0.3
Output current high			IOH	One I/O port active		- 15			mA
				All I/O ports active			-30
Output current low			IOL	One I/O port active	+ 30 (peak value)
						+ 15 (note)
				Total value for output ports	+ 100 (peak value)
						+ 60 *
Operating temperature			TA		- 40		to	+ 85	°C
Storage temperature			TSTG		- 65 to			+ 150
NOTE: The values for output current low ( IOL ) are calculated as Peak Value ×					Duty .

17-2