Samsung S3C80E5, S3C80E7, S3P80E5, S3P80E7 Datasheet

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)	PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLERS

Samsung'sS3C8-series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals and various mask-programmable ROM sizes. Important CPU features include:

—Efficient register-oriented architecture

—Selectable CPU clock sources

—Idle and Stop power-down mode release by interrupt

—Built-in basic timer with watchdog function

A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels.

S3C80E5/C80E7 MICROCONTROLLER

The S3C80E5/C80E7 single-chip CMOS microcontroller is fabricated using a highly advanced CMOS process, based on Samsung’s newest CPU architecture.

The S3C80E5/C80E7 is the microcontroller which has 16/24-Kbyte mask-programmable ROM. The S3P80E5/P80E7 is the microcontroller which has 16/24-Kbyte one-time-programmable EPROM.

Using a proven modular design approach, Samsung engineers developed the S3C80E5/C80E7 by integrating the following peripheral modules with the powerful SAM87 core:

—Four programmable I/O ports, including three 8-bit ports and one 2-bit port, for a total of 26 pins.

—Internal LVD circuit and twelve bitprogrammable pins for external interrupts.

—One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset).

—One 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes.

—One 8-bit counter with auto-reload function and one-shot or repeat control.

The S3C80E5/C80E7 is a versatile general-purpose microcontroller which is especially suitable for use as unified remote transmitter controller. It is currently available in a 32-pin SOP and SDIP package for S3C80E5 and S3C80E7. And available in 40 DIP package only for S3C80E7.

OTP

The S3P80E5/P80E7 is an OTP (One Time Programmable) version of the S3C80E5/C80E7 microcontroller. The S3P80E5/P80E7 microcontroller has an on-chip 16/24-Kbyte one-time-programmable EPROM instead of a masked ROM. The S3P80E5/P80E7 is comparable to the S3C80E5/C80E7, both in function and in pin configuration.

1-1

PRODUCT OVERVIEW	S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

FEATURES

CPU

•SAM87 CPU core

Memory

•16-Kbyte internal program memory (ROM): S3C80E5

•24-Kbyte internal program memory (ROM): S3C80E7

•256-byte internal (RAM): 8000–80FFH

•Data memory: 317-byte internal register file

Instruction Set

•78 instructions

•IDLE and STOP instructions added for powerdown modes

Instruction Execution Time

•750 ns at 8 MHz fOSC (minimum)

Interrupts

•Six interrupt levels and 18 interrupt sources

•15 vectors (14 sources have a dedicated vector address and four sources share a single vector)

•Fast interrupt processing feature (for one selected interrupt level)

I/O Ports

•Three 8-bit I/O ports (P0–P2) and one 2-bit port (P3) for a total of 26 bit-programmable pins

•Twelve input pins for external interrupts

Timers and Timer/Counters

•One programmable 8-bit basic timer (BT) for oscillation stabilization control or watchdog timer (software reset) function

•One 8-bit timer/counter (Timer 0) with three operating modes; Interval, Capture, and PWM

•One 16-bit timer/counter (Timer 1) with two operating modes; Interval and Capture

Carrier Frequency Generator

•One 8-bit counter with auto-reload function and one-shot or repeat control (Counter A)

Back-up mode

•When reset pin is low level or when VDD is lower than VLVD, the chip enters back-up mode to reduce current consumption.

Low Voltage Detect Circuit

•Low voltage detect for reset or back-up mode input.

•Low level detect voltage :

2.2 V (Typ) –100 mV/+ 200 mV

Operating Temperature Range

•– 40°C to + 85 °C

Operating Voltage Range

• 2.0 V to 5.5 V at 4 MHz fOSC

•2.1 V to 5.5 V at 8 MHz fOSC

Package Type

•32-pin SOP

•32-pin SDIP

•40-pin DIP

1-2

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)	PRODUCT OVERVIEW

BLOCK DIAGRAM

		P0.0–P0.7
		(INT0–INT4)	P1.0–P1.7
				RESET
		PORT 0	PORT 1	TEST
VDD	LVD	INTERNAL BUS			P2.0–P2.3
				PORT2	(INT5–INT8)
					P2.4–P2.7
XIN	MAIN	I/O PORT and INTERRUPT
		CONTROL
XOUT	OSC
					P3.0/T0PWM/
	8-BIT				T0CAP/T1CAP
		SAM87		PORT 3
	BASIC
					P3.1/REM/T0CK
	TIMER	CPU
	8-BIT
	TIMER/	PROGRAM
	COUNTER	MEMORY	317-BYTE	CARRIER
		REGISTER
		(16/24-Kbyte Program	FILE	GENERATOR
		Memory and 256-Byte		(COUNTER A)
		Program RAM)
	16-BIT
	TIMER/
	COUNTER

Figure 1-1. Block Diagram

1-3

PRODUCT OVERVIEW	S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

PIN ASSIGNMENTS

VSS						VDD
		1		32
XIN
		2		31		RESET/BACK-UP MODE
XOUT
		3		30		P3.1/REM/T0CK
TEST
		4		29		P3.0/T0PWM/T0CAP/T1CAP
P2.0/INT5
		5		28		P2.7
P2.1/INT6
		6		27		P2.6
P2.2/INT7			S3C80E5
		7		26		P2.5
P2.3/INT8			S3C80E7
		8		25		P2.4
P0.0/INT0			32-SOP/SDIP
		9		24		P1.7
P0.1/INT1
		10	(Top View)	23		P1.6
P0.2/INT2
		11		22		P1.5
P0.3/INT3
		12		21		P1.4
P0.4/INT4
		13		20		P1.3
P0.5/INT4
		14		19		P1.2
P0.6/INT4
		15		18		P1.1
P0.7/INT4
		16		17		P1.0

Figure 1-2. Pin Assignment (32-Pin SOP/SDIP Package)

VSS						VDD
		1		40
XIN		2		39		RESET/BACK-UP MODE
XOUT		3		38		P3.1/REM/T0CK
TEST		4		37		P3.0/T0PWM/T0CAP/T1CAP
NC		5		36		NC
NC		6		35		NC
P2.0/INT5		7		34		P2.7
P2.1/INT6		8	S3C80E5	33		P2.6
P2.2/INT7		9		32		P2.5
P2.3/INT8		10	S3C80E7	31		P2.4
P0.0/INT0		11	40-DIP	30		P1.7
P0.1/INT1		12	(Top View)	29		P1.6
P0.2/INT2		13		28		P1.5
P0.3/INT3		14		27		P1.4
NC		15		26		NC
NC		16		25		NC
P0.4/INT4		17		24		P1.3
P0.5/INT4		18		23		P1.2
P0.6/INT4		19		22		P1.1
P0.7/INT4		20		21		P1.0

Figure 1-3. Pin Assignment (40-Pin DIP Package)

1-4

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec) PRODUCT OVERVIEW

Table 1-1. Pin Descriptions

	Pin	Pin	Pin	Circuit	Pin No.	Pin No.	Shared
	Names	Type	Description	Type	(32-pin)	(40-pin)	Functions
	P0.0–P0.7	I/O	I/O port with bit-programmable pins.	1	9–16	11–14,	INT0–INT4
						17–20
			Configurable to input or push-pull output
			mode. Pull-up resistors are assignable by
			software. Pins can be assigned individually
			as external interrupt inputs with noise filters,
			interrupt enable/disable, and interrupt
			pending control.
	P1.0–P1.7	I/O	I/O port with bit-programmable pins.	2	17–24	21–24,	–
						27–30
			Configurable to C-MOS input mode or
			output mode. Pin circuits are either push-
			pull or n-channel open-drain type. Pull-up
			resistors are assignable by software.
	P2.0–P2.3	I/O	General-purpose I/O port with bit-	3	5–8,	7–10,	INT5–INT8
						31–34
	P2.4–P2.7		programmable pins. Configurable to C-	4	25–28		–
			MOS input mode, push-pull output mode, or
			n-channel open-drain output mode. Pull-up
			resistors are assignable by software. Lower
			nibble pins, P2.3–P2.0, can be assigned as
			external interrupt inputs with noise filters,
			interrupt enable/disable, and interrupt
			pending control.
	P3.0	I/O	2-bit I/O port with bit-programmable pins.	5	29	37	T0PWM/
	P3.1		Configurable to C-MOS input mode, push-		30	38	T0CAP/
			pull output mode, or n-channel open-drain				T1CAP/
			output mode. Pull-up resistors are				REM/T0CK
			assignable by software. The two port 3 pins
			have high current drive capability.
	XIN, XOUT	–	System clock input and output pins	–	2, 3	2, 3	–
	RESET/	I	System reset signal input pin and back-up	6	31	39	–
	BACK-UP		mode input pin. The pin circuit is a C-MOS
	MODE		input.
	TEST	I	Test signal input pin (for factory use only;	–	4	4	–
			must be connected to VSS).
	VDD	–	Power supply input pin	–	32	40	–
	VSS	–	Ground pin	–	1	1	–

1-5

PRODUCT OVERVIEW	S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

PIN CIRCUITS

PULL-UP

ENABLE

DATA

OUTPUT

DISABLE

INTERRUPT INPUT IRQ6,7 (INT0-4)

	VDD
PULL-UP RESISTOR
	(Typical 21 KΩ)
	VDD
	I/O
NOISE	VSS
FILTER
NORMAL
INPUT

STOP	Oscillator Release (SED and R circuit)

NOTE: To prevent and recover from abnormal stop status caused by battery bouncing, the S3P80E5 has a special logic_ SED and R circuit −related to P0 and P1. This is a specific function for key input/output of universal remote controller. When these ports (P0, P1) are used as a normal input pin, unexpected stop mode recovery can occur by input level switching. Hence, the user should be aware of input level switching, if P0 and P1 are to be used as normal input ports.

Figure 1-4. Pin Circuit Type 1 (Port 0)

1-6

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)	PRODUCT OVERVIEW

		VDD
	PULL-UP RESISTOR
	(Typical 21	KΩ)
PULL-UP
ENABLE
	VDD
DATA
		I/O
OUTPUT
DISABLE
	VSS
NORMAL INPUT	NOISE
	FILTER

STOP	Oscillator Release (SED and R circuit)

NOTE: To prevent and recover from abnormal stop status caused by battery bouncing, the S3P80E5 has a special logic −SED and R circuit −related to P0 and P1. This is a specific function for key input/output of universal remote controller. When these ports (P0, P1) are used as a normal input pin, unexpected stop mode releasing can occur by input level switching. Hence, the user should be aware of input level switching, if P0 and P1 are to be used as normal input ports.

Figure 1-5. Pin Circuit Type 2 (Port 1)

1-7

PRODUCT OVERVIEW	S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

		VDD
		PULL-UP RESISTOR
		(Typical 21 KΩ)
	PULL-UP
	ENABLE
		VDD
	DATA
		I/O
	OPEN-DRAIN
	OUTPUT
	DISABLE
		VSS
	EXTERNAL	NOISE
	INTERRUPT
		FILTER
	IRQ5 (INT5-8)
		NORMAL INPUT

Figure 1-6. Pin Circuit Type 3 (Ports 2.0–2.3)

1-8

S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)	PRODUCT OVERVIEW

VDD

PULL-UP RESISTOR

(Typical 21 KΩ)

PULL-UP

ENABLE

VDD

DATA

I/O

OPEN-DRAIN

OUTPUT

DISABLE

VSS

NORMAL INPUT

Figure 1-7. Pin Circuit Type 4 (P2.4−P2.7)

1-9

PRODUCT OVERVIEW	S3C80E5/P80E5/C80E7/P80E7 (Preliminary Spec)

		VDD
		PULL-UP RESISTOR
		(Typical 21 KΩ)
PULL-UP
ENABLE	SELECT
	M	VDD
PORT 3 DATA		DATA
	U
ALTERNATIVE	X
OUTPUT
		I/O
OPEN-DRAIN
OUTPUT
DISABLE
		VSS
NORMAL INPUT
ALTERNATIVE		NOISE
		FILTER
INPUT

Figure 1-8. Pin Circuit Type 5 (P 3)

			BACK-UP MODE
	RESET/	NOISE	SYSTEM RESET
	BACK-UP
		FILTER
	MODE

Figure 1-9. Pin Circuit Type 6 (RESET/BACK-UP MODE)

1-10