Samsung S3C7414, S3C7424, S3C7434, S3P7414, S3P7424 Datasheet
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S3C7414/P7414/C7424/P7424/C7434/P7434 |
PRODUCT OVERVIEW |
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1 PRODUCT OVERVIEW
OVERVIEW
The S3C7414/C7424/C7434 single-chip CMOS microcontroller has been designed for very high performance using Samsung's newest 4-bit CPU core, SAM47 (Samsung Arrangeable Microcontroller).
With an A/D converter, LED direct drive pins, an 8-bit serial I/O interface, and an 8-bit timer/counter, the S3C7414/C7424/C7434 offers you an excellent design solution for a wide variety of home appliance applications
— electric fans, cookers, boilers, and air conditioners, for example.
Up to 35 pins of the 42-pin SDIP or 44-pin QFP package can be dedicated to I/O. Seven vectored interrupts provide fast response to internal and external events.
In addition, the S3C7414/C7424/C7434's advanced CMOS technology provides for low power consumption and a wide operating voltage range.
OTP
The S3C7414/C7424/C7434 microcontroller is also available in OTP (One Time Programmable) version, S3P7414/P7424/P7434. S3P7414/P7424/P7434 microcontroller has an on-chip 4-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P7414/P7424/P7434 is comparable to S3C7414/C7424/C7434, in function, in D.C. electrical characteristics and in pin configuration.
DEVELOPMENT SUPPORT
The Samsung Microcontroller Development System, SMDS, provides you with a complete PC-based development environment for S3C7-series microcontrollers that is powerful, reliable, and portable. In addition to its window-based program development structure, the SMDS toolset includes versatile debugging, trace, instruction timing, and performance measurement applications.
The Samsung Generalized Assembler (SAMA) has been designed specifically for the SMDS environment and accepts assembly language sources in a variety of microprocessor formats. SAMA generates industry-standard hex files that also contain program control data for SMDS compatibility.
1-1
PRODUCT OVERVIEW |
S3C7414/P7414/C7424/P7424/C7434/P7434 |
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FEATURES SUMMARY
Memory
•256 × 4-bit RAM
•4,096 × 8-bit ROM
35 I/O Pins
•I/O: 31 pins including 8 LED direct drive pins (S3C7414/C7434)
18 pins including 8 LED direct drive pins (S3C7424)
•Input only: 4 pins
A/D Converter
•6-channel with 8-bit resolution
•22.89 µs conversion speed at 4.19 MHz
Basic Timer
•One 8-bit basic timer
•Watchdog timer functions
•Four interval clock selection
Timer/Counters
•Two 8-bit timer/counter (TC0, TC1)
•Programmable 8-bit timer
•External event counter
•Arbitrary clock frequency output
•PWM output mode (TC1)
Watch Timer
•One watch timer 8-bit
•Time interval generation: 0.5 s, 3.9 ms at 4.19 MHz
•Four frequency outputs to BUZ pin
8-bit Serial I/O Interface
•8-bit transmit/receive mode
•8-bit receive mode
•LSB-first or MSB-first transmission selectable
•Internal or external clock source
Built-in reset circuit (S3C7434 only)
•Built-in power-on reset circuit
Interrupts
•Five internal vectored interrupts (INTB, INTT0, INTT1, INTS, INTAD)
•Three external vectored interrupts (INT0, INT1, INT4)
•Two quasi-interrupts (INT2, INTW)
Bit Sequential Carrier
•Supports 16-bit serial data transfer in arbitrary format
Memory-Mapped I/O Structure
•Data memory bank 15
Two Power-Down Modes
•Idle mode (only CPU clock stops)
•Stop mode (system oscillation stops)
Oscillation Sources
•Crystal, Ceramic, or RC for system clock
•Crystal, Ceramic: 0.4–6.0 MHz
•RC: 4 MHz (typ)
•CPU clock divider circuit (by 4, 8, or 64)
Instruction Execution Times
•0.95, 1.91, 15.3 µs at 4.19 MHz
•0.67, 1.33, 10.7 µs at 6.0 MHz
Operating Temperature
•– 40 °C to 85 °C
Operating Voltage Range
• 1.8 V to 5.5 V (S3C7414/C7424)
•2.5 V to 5.5 V (S3C7434)
Package Type
•42-pin SDIP, 44-pin QFP (S3C7414/C7434)
30-pin SDIP, 28-pin SOP (S3C7424)
1-2
S3C7414/P7414/C7424/P7424/C7434/P7434 PRODUCT OVERVIEW
Table 1-1. Comparision Table
Feature |
S3C7414 |
S3C7424 |
S3C7434 |
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Core |
SAM47 |
SAM47 |
SAM47 |
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ROM |
4 K bytes |
Same |
Same |
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RAM |
256 nibbles |
Same |
Same |
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I/O |
35 (4 input only) |
21 (3 input only) |
35 (4 input only) |
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POR (1) |
None |
None |
Built in/ Typ: 2.0 V |
SIO |
8-bit SIO x 1 |
Same |
Same |
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Timer0 |
8-bit timer/counter |
Same |
Same |
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Timer1(PWM) |
8-bit timer/counter |
Same |
Same |
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(8-bit PWM x 1) |
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Watchdog timer |
Watch-dog |
Same |
Same |
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4 selectable interval |
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ADC |
8-bit x 6 |
8-bit x 4 |
8-bit x 6 |
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AVSS |
None (2) |
Same |
Same |
Interrupt |
External x 3 |
External x 2 |
External x 3 |
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Internal x 5 |
Internal x 5 |
Internal x 5 |
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Quasi x 2 (KS0–KS3) |
Quasi x 1 ( – ) |
Quasi x 2 (KS0–KS3) |
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Power down |
Stop/Idle |
Same |
Same |
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Oscillator |
Crystal, Ceramic, RC |
Same |
Same |
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Operating frequency |
0.4–6 MHz |
Same |
Same |
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Operating voltage |
1.8–5.5 V |
1.8–5.5 V |
2.5–5.5 V |
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OTP/MTP |
OTP |
Same |
Same |
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Package |
42SDIP/44QFP |
30SDIP/28SOP |
42SDIP/44QFP |
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NOTES
1.POR (power on reset)/Typ 2.0 V low voltage detector.
2.Internal A/D converter ground (bonded to VSS internally)
1-3
PRODUCT OVERVIEW |
S3C7414/P7414/C7424/P7424/C7434/P7434 |
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BLOCK DIAGRAM
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BASIC |
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WATCH |
INT0, INT1, INT2,INT4 |
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TIMER |
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TIMER |
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8-BIT |
RESET |
XIN |
XOUT |
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TIMER/ |
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P0.0/SCK |
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COUNTER 0 |
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INTERRUPT |
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I/O PORT 02 |
P0.1/SO |
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INSTRUCTION |
P0.2/SI |
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8-BIT |
CONTROL |
CLOCK |
REGISTER |
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P0.3/BUZ |
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BLOCK |
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TIMER/ |
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SERIAL |
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COUNTER 1 |
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PROGRAM |
I/O |
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INTERNAL |
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COUNTER |
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P4.0-4.3 |
I/O PORT 4 |
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P1.0/INT0 |
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INTERRUPTS |
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INPUT |
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P1.1/INT1 |
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P5.0-5.3 |
I/O PORT 5 |
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PROGRAM |
PORT 1 |
P1.2/INT2 |
INSTRUCTION DECODER |
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P1.3/INT4 |
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STATUS WORD |
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P6.0/KS0 |
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ARITHMETIC |
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I/O PORT 2 |
P2.0-P2.3/ |
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P6.1/KS1 |
I/O PORT 6 |
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AD0-AD3 |
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P6.2/KS2 |
AND |
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STACK |
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P6.3/KS3 |
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LOGIC UNIT |
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POINTER |
A/D |
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AVREF |
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P7.0-7.3 |
I/O PORT 7 |
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CONVERTER |
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P8.0/TCL0 |
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P3.0/AD4 |
I/O PORT 8 |
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I/O PORT 3 |
P3.1/AD5 |
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P8.1/TCLO0 |
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256 x 4-BIT |
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4 K BYTE |
P3.2/CLO/TCL1 |
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P8.2 |
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DATA |
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PROGRAM |
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P3.3/PWM / TCLO1 |
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MEMORY |
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MEMORY |
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Figure 1-1. S3C7414/C7424/C7434Simplified Block Diagram
1-4
S3C7414/P7414/C7424/P7424/C7434/P7434 |
PRODUCT OVERVIEW |
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PIN ASSIGNMENTS
P2.0/AD0 
1
P2.1/AD1 
2
P2.2/AD2 
3
P2.3/AD3 
4
P3.0/AD4 
5
P3.1/AD5 
6 AVREF 
7 P3.2/CLO/TCL1 
8 P3.3/PWM/TCLO1 
9
P4.0 
10
VDD 
11
VSS 
12
XOUT 
13
XIN 
14 TEST 
15 P4.1 
16 P4.2 
17
RESET 
18 P4.3 
19 P5.0 
20 P5.1 
21
S3C7414 (42-SDIP)
42 
P8.2
41 
P8.1/TCLO0
40 
P8.0/TCL0
39 
P7.3
38 
P7.2
37 
P7.1
36 
P7.0
35 
P6.3/KS3
34 
P6.2/KS2
33 
P6.1/KS1
32 
P6.0/KS0
31 
P1.3/INT4
30 
P1.2/INT2
29 
P1.1/INT1
28 
P1.0/INT0
27 
P0.3/BUZ
26 
P0.2/SI
25 
P0.1/SO
24 
P0.0/SCK
23 
P5.3
22 
P5.2
Figure 1-2. S3C7414 Pin Assignment (42-SDIP)
1-5
PRODUCT OVERVIEW |
S3C7414/P7414/C7424/P7424/C7434/P7434 |
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NC |
P3.1/AD5 |
P3.0/AD4 |
P2.3/AD3 |
P2.2/AD2 |
P2.1/AD1 |
P2.0/AD0 |
P8.2 |
P8.1/TCLO0 |
P8.0/TCL0 |
P7.3 |
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44 |
43 |
42 |
41 |
40 |
39 |
38 |
37 |
36 |
35 |
34 |
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P7.2 |
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AVREF |
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1 |
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33 |
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P3.2/CLO/TCL1 |
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2 |
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32 |
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P7.1 |
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P3.3/PWM/TCLO1 |
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3 |
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31 |
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P7.0 |
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P4.0 |
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4 |
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S3C7414 |
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30 |
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P6.3/KS3 |
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VDD |
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5 |
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29 |
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P6.2/KS2 |
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VSS |
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6 |
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28 |
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P6.1/KS1 |
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XOUT |
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7 |
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(44-QFP) |
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27 |
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P6.0/KS0 |
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XIN |
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8 |
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26 |
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P1.3/INT4 |
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TEST |
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9 |
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25 |
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P1.2/INT2 |
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P4.1 |
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10 |
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24 |
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P1.1/INT1 |
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P4.2 |
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11 |
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23 |
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P1.0/INT0 |
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12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
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RESET |
P4.3 |
P5.0 |
P5.1 |
P5.2 |
P5.3 |
P0.0/SCK |
P0.1/SO |
P0.2/SI |
P0.3/BUZ |
NC |
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Figure 1-3. S3C7414 Pin Assignment (44-QFP)
1-6
S3C7414/P7414/C7424/P7424/C7434/P7434 |
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PRODUCT OVERVIEW |
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VSS 
1
XOUT 
2
XIN 
3 TEST 
4 P4.1 
5 P4.2 
6
RESET 
7 NC 
8 P4.3 
9
P5.0 
10
P5.1 
11
P5.2 
12
P5.3 
13 P0.0/SCK 
14 P0.1/SO 
15
S3C7424 (30-SDIP)
30 |
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VDD |
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29 |
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P4.0 |
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28 |
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P3.3/PWM/TCLO1 |
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27 |
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P3.2/CLO/TCL1 |
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26 |
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AVREF |
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25 |
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NC |
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24 |
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P2.3/AD3 |
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23 |
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P2.2/AD2 |
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22 |
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P2.1/AD1 |
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21 |
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P2.0/AD0 |
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20 |
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P1.2/INT2 |
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19 |
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P1.1/INT1 |
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18 |
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P1.0/INT0 |
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17 |
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P0.3/BUZ |
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16 |
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P0.2/SI |
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Figure 1-4. S3C7424 Pin Assignment (30-SDIP)
VSS 
1
XOUT 
2
XIN 
3 TEST 
4 P4.1 
5 P4.2 
6
RESET 
7 P4.3 
8 P5.0 
9 P5.1 
10 P5.2 
11 P5.3 
12
P0.0/SCK 
13 P0.1/SO 
14
S3C7424 (28-SOP)
28 |
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VDD |
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27 |
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P4.0 |
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26 |
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P3.3/PWM/TCLO1 |
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25 |
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P3.2/CLO/TCL1 |
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24 |
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AVREF |
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23 |
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P2.3/AD3 |
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22 |
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P2.2/AD2 |
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21 |
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P2.1/AD1 |
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20 |
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P2.0/AD0 |
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19 |
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P1.2/INT2 |
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18 |
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P1.1/INT1 |
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17 |
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P1.0/INT0 |
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16 |
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P0.3/BUZ |
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15 |
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P0.2/SI |
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Figure 1-5. S3C7424 Pin Assignment (28-SOP)
1-7
PRODUCT OVERVIEW |
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S3C7414/P7414/C7424/P7424/C7434/P7434 |
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P2.0/AD0 
1
P2.1/AD1 
2
P2.2/AD2 
3
P2.3/AD3 
4
P3.0/AD4 
5
P3.1/AD5 
6 AVREF 
7 P3.2/CLO/TCL1 
8 P3.3/PWM/TCLO1 
9
P4.0 
10
VDD 
11
VSS 
12
XOUT 
13
XIN 
14 TEST 
15 P4.1 
16 P4.2 
17
RESET 
18 P4.3 
19 P5.0 
20 P5.1 
21
S3C7434 (42-SDIP)
42 
P8.2
41 
P8.1/TCLO0
40 
P8.0/TCL0
39 
P7.3
38 
P7.2
37 
P7.1
36 
P7.0
35 
P6.3/KS3
34 
P6.2/KS2
33 
P6.1/KS1
32 
P6.0/KS0
31 
P1.3/INT4
30 
P1.2/INT2
29 
P1.1/INT1
28 
P1.0/INT0
27 
P0.3/BUZ
26 
P0.2/SI
25 
P0.1/SO
24 
P0.0/SCK
23 
P5.3
22 
P5.2
Figure 1-6. S3C7434 Pin Assignment (42-SDIP)
1-8
S3C7414/P7414/C7424/P7424/C7434/P7434 |
PRODUCT OVERVIEW |
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NC |
P3.1/AD5 |
P3.0/AD4 |
P2.3/AD3 |
P2.2/AD2 |
P2.1/AD1 |
P2.0/AD0 |
P8.2 |
P8.1/TCLO0 |
P8.0/TCL0 |
P7.3 |
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44 |
43 |
42 |
41 |
40 |
39 |
38 |
37 |
36 |
35 |
34 |
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P7.2 |
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AVREF |
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1 |
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33 |
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P3.2/CLO/TCL1 |
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2 |
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32 |
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P7.1 |
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P3.3/PWM/TCLO1 |
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3 |
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31 |
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P7.0 |
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P4.0 |
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4 |
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S3C7434 |
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30 |
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P6.3/KS3 |
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VDD |
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5 |
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29 |
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P6.2/KS2 |
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VSS |
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6 |
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28 |
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P6.1/KS1 |
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XOUT |
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7 |
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(44-QFP) |
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27 |
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P6.0/KS0 |
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XIN |
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8 |
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26 |
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P1.3/INT4 |
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TEST |
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9 |
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25 |
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P1.2/INT2 |
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P4.1 |
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10 |
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24 |
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P1.1/INT1 |
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P4.2 |
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11 |
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23 |
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P1.0/INT0 |
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12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
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RESET |
P4.3 |
P5.0 |
P5.1 |
P5.2 |
P5.3 |
P0.0/SCK |
P0.1/SO |
P0.2/SI |
P0.3/BUZ |
NC |
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Figure 1-7. S3C7434 Pin Assignment (44-QFP)
1-9
PRODUCT OVERVIEW |
S3C7414/P7414/C7424/P7424/C7434/P7434 |
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PIN DESCRIPTIONS
Table 1-2. S3C7414/C7434 Pin Descriptions
Pin Name |
Pin Type |
Description |
Number |
Share Pin |
|
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|
P0.0 |
I/O |
4-bit I/O port. |
24 |
(18) |
SCK |
P0.1 |
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1-bit or 4-bit read/write and test is possible. |
25 |
(19) |
SO |
P0.2 |
|
Individual pins are software configurable as input or |
26 |
(20) |
SI |
P0.3 |
|
output. |
27 |
(21) |
BUZ |
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4-bit pull-up resistors are software assignable; pull-up |
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resistors are automatically disabled for output pins. |
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P1.0 |
I |
4-bit input port. |
28 |
(23) |
INT0 |
P1.1 |
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1-bit and 4-bit read and test is possible. |
29 |
(24) |
INT1 |
P1.2 |
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3-bit pull-up resistors are individually assignable by |
30 |
(25) |
INT2 |
P1.3 |
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software to pins P1.0, P1.1, and P1.2. |
31 |
(26) |
INT4 |
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P2.0 |
I/O |
4-bit I/O port. |
1 (38) |
AD0 |
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P2.1 |
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N-channel open-drain output. |
2 (39) |
AD1 |
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P2.2 |
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1-bit or 4-bit write and test is possible. |
3 (40) |
AD2 |
|
P2.3 |
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Individual pins are software configurable as AD input |
4 (41) |
AD3 |
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or output. |
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4-bit pull-up resistors are software assignable; pull-up |
|
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resistors are automatically disabled for output pins. |
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P3.0 |
I/O |
Same as Port 0 (P0.0–P0.3) |
5 (42) |
AD4 |
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P3.1 |
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6 (43) |
AD5 |
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P3.2 |
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8 |
(2) |
CLO/TCL1 |
P3.3 |
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9 |
(3) |
PWM/TCLO1 |
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P4.0 |
I/O |
4-bit I/O ports. |
10 (4) |
– |
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P4.1 |
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Ports 4 and 5 can be configured individually as n- |
16 |
(10) |
|
P4.2 |
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channel open-drain or as CMOS push-pull output by |
17 |
(11) |
|
P4.3 |
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software. |
19 |
(13) |
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P5.0–P5.3 |
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1-bit and 4-bit read/write and test is possible. |
20–23 |
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Ports 4 and 5 can be paired to enable 8-bit data |
(14–17) |
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transfer. |
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4-bit pull-up resistors are software assignable; pull-up |
|
|
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resistors are automatically disabled for output pins. |
|
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P6.0–P6.3 |
I/O |
Same as Port 0 except port 8 is a 3-bit I/O port |
32–35 |
KS0–KS3 |
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(27–30) |
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P7.0–P7.3 |
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36–39 |
– |
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(31–34) |
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P8.0 |
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40 |
(35) |
TCL0 |
P8.1 |
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41 |
(36) |
TCLO0 |
P8.2 |
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42 |
(37) |
– |
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1-10
S3C7414/P7414/C7424/P7424/C7434/P7434 PRODUCT OVERVIEW
Table 1-2. S3C7414/C7434 Pin Descriptions (Continued)
Pin Name |
Pin Type |
Description |
Number |
Share Pin |
|
|
|
|
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|
SCK |
I/O |
Serial I/O interface clock signal |
24 |
(18) |
P0.0 |
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|
SO |
I/O |
Serial data output |
25 |
(19) |
P0.1 |
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SI |
I/O |
Serial data input |
26 |
(20) |
P0.2 |
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BUZ |
I/O |
2 kHz, 4kHz, 8kHz, or 16 kHz frequency output at the |
27 |
(21) |
P0.3 |
|
|
watch timer clock frequency of 32.768 kHz |
|
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|
INT0, INT1 |
I |
External interrupts. The triggering edge for INT0 and |
28–29 |
P1.0, P1.1 |
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|
INT1 is selectable. Only INT0 is synchronized with the |
(23–24) |
|
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system clock. |
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INT2 |
I |
Quasi-interrupt input with rising edge detection |
30 |
(25) |
P1.2 |
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INT4 |
I |
External interrupts with detection of rising and falling |
31 |
(26) |
P1.3 |
|
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edges |
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AD0–AD3 |
I/O |
A/D converter analog inputs |
1–4 |
P2.0–P2.3 |
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(38–41) |
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AD4–AD5 |
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5–6 |
P3.0–P3.1 |
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(42–43) |
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TCL0 |
I/O |
External clock input for timer/counter0 |
40 |
(35) |
P8.0 |
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TCLO0 |
I/O |
Timer/counter clock output |
41 |
(36) |
P8.1 |
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CLO |
I/O |
Clock output |
8 |
(2) |
P3.2 |
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TCL1 |
I/O |
External clock input for timer/counter1 |
8 |
(2) |
P3.2 |
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PWM |
I/O |
PWM output |
9 |
(3) |
P3.3 |
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TCLO1 |
I/O |
Timer/counter clock output1 |
9 |
(3) |
P3.3 |
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KS0–KS3 |
I/O |
Quasi-interrupt input with falling edge detection |
32–35 |
P6.0–P6.3 |
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(27–30) |
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VDD |
– |
Main power supply |
11 (5) |
– |
|
VSS |
– |
Ground |
12 (6) |
– |
|
RESET |
I |
Reset signal |
18 |
(12) |
– |
|
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|
XIN, Xout |
– |
Crystal, ceramic, or RC oscillator signal for system |
14, 13 |
– |
|
|
|
clock. |
(8, 7) |
|
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AVREF |
– |
A/D converter analog reference voltage |
7 |
(1) |
– |
TEST |
I |
Test signal input (must be connected to VSS) |
15 (9) |
– |
|
NC |
– |
No connection (no bonding pin) |
(22, 44) |
– |
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|
NOTE: Parentheses indicate 44-QFP pin number.
1-11
PRODUCT OVERVIEW |
S3C7414/P7414/C7424/P7424/C7434/P7434 |
|
|
Table 1-3. S3C7424 Pin Descriptions
Pin Name |
Pin Type |
Description |
Number |
Share Pin |
|
|
|
|
|
|
|
P0.0 |
I/O |
4-bit I/O port. |
14 |
(13) |
SCK |
P0.1 |
|
1-bit or 4-bit read/write and test is possible. |
15 |
(14) |
SO |
P0.2 |
|
Individual pins are software configurable as input or |
16 |
(15) |
SI |
P0.3 |
|
output. |
17 |
(16) |
BUZ |
|
|
4-bit pull-up resistors are software assignable; pull-up |
|
|
|
|
|
resistors are automatically disabled for output pins. |
|
|
|
|
|
|
|
|
|
P1.0 |
I |
4-bit input port. |
18 |
(17) |
INT0 |
P1.1 |
|
1-bit and 4-bit read and test is possible. |
19 |
(18) |
INT1 |
P1.2 |
|
3-bit pull-up resistors are individually assignable by |
20 |
(19) |
INT2 |
|
|
software to pins P1.0, P1.1, and P1.2. |
|
|
|
|
|
|
|
|
|
P2.0 |
I/O |
4-bit I/O port. |
21 |
(20) |
AD0 |
P2.1 |
|
N-channel open-drain output. |
22 |
(21) |
AD1 |
P2.2 |
|
1-bit or 4-bit write and test is possible. |
23 |
(22) |
AD2 |
P2.3 |
|
Individual pins are software configurable as AD input |
24 |
(23) |
AD3 |
|
|
or output. |
|
|
|
|
|
4-bit pull-up resistors are software assignable; pull-up |
|
|
|
|
|
resistors are automatically disabled for output pins. |
|
|
|
|
|
|
|
|
|
P3.2 |
I/O |
Same as Port 0 (P0.0–P0.3) |
27 |
(25) |
CLO/TCL1 |
P3.3 |
|
|
28 |
(26) |
PWM/TCLO1 |
|
|
|
|
|
|
P4.0 |
I/O |
4-bit I/O ports. |
29 |
(27) |
– |
P4.1 |
|
Ports 4 and 5 can be configured individually as n- |
5 |
(5) |
|
P4.2 |
|
channel open-drain or as CMOS push-pull output by |
6 |
(6) |
|
P4.3 |
|
software. |
9 |
(8) |
|
|
|
1-bit and 4-bit read/write and test is possible. |
|
|
|
P5.0–P5.3 |
|
Ports 4 and 5 can be paired to enable 8-bit data |
10–13 |
|
|
|
|
transfer. |
(9–12) |
|
|
|
|
4-bit pull-up resistors are software assignable; pull-up |
|
|
|
|
|
resistors are automatically disabled for output pins. |
|
|
|
|
|
|
|
|
|
1-12
S3C7414/P7414/C7424/P7424/C7434/P7434 PRODUCT OVERVIEW
Table 1-3. S3C7424 Pin Descriptions (Continued)
Pin Name |
Pin Type |
Description |
Number |
Share Pin |
|
|
|
|
|
|
|
SCK |
I/O |
Serial I/O interface clock signal |
14 |
(13) |
P0.0 |
|
|
|
|
|
|
SO |
I/O |
Serial data output |
15 |
(14) |
P0.1 |
|
|
|
|
|
|
SI |
I/O |
Serial data input |
16 |
(15) |
P0.2 |
|
|
|
|
|
|
BUZ |
I/O |
2 kHz, 4kHz, 8kHz, or 16 kHz frequency output at the |
17 |
(16) |
P0.3 |
|
|
watch timer clock frequency of 32.768 kHz |
|
|
|
|
|
|
|
|
|
INT0, INT1 |
I |
External interrupts. The triggering edge for INT0 and |
18, 19 |
P1.0, P1.1 |
|
|
|
INT1 is selectable. Only INT0 is synchronized with the |
(17, 18) |
|
|
|
|
system clock. |
|
|
|
|
|
|
|
|
|
INT2 |
I |
Quasi-interrupt input with rising edge detection |
20 |
(19) |
P1.2 |
|
|
|
|
|
|
AD0–AD3 |
I/O |
A/D converter analog inputs |
21–24 |
P2.0–P2.3 |
|
|
|
|
(20–23) |
|
|
|
|
|
|
|
|
CLO |
I/O |
Clock output |
27 |
(25) |
P3.2 |
|
|
|
|
|
|
TCL1 |
I/O |
External clock input for timer/counter1 |
27 |
(25) |
P3.2 |
|
|
|
|
|
|
PWM |
I/O |
PWM output |
28 |
(26) |
P3.3 |
|
|
|
|
|
|
TCLO1 |
I/O |
Timer/counter clock output1 |
28 |
(26) |
P3.3 |
|
|
|
|
|
|
VDD |
– |
Main power supply |
30 |
(28) |
– |
VSS |
– |
Ground |
1 |
(1) |
– |
RESET |
I |
Reset signal |
7 |
(7) |
– |
|
|
|
|
|
|
XIN, XOUT |
– |
Crystal, ceramic, or RC oscillator signal for system |
3, 2 |
– |
|
|
|
clock. |
(3, 2) |
|
|
|
|
|
|
|
|
AVREF |
– |
Internal A/D converter analog reference voltage |
26 |
(24) |
– |
TEST |
I |
Test signal input (must be connected to VSS) |
4 |
(4) |
– |
NC |
– |
No connection (no bonding pin) |
8, 25 |
– |
|
|
|
|
|
|
|
NOTE: Parentheses indicate 28-SOP pin number.
1-13
PRODUCT OVERVIEW |
S3C7414/P7414/C7424/P7424/C7434/P7434 |
|
|
Table 1-4. Overview of S3C7414/C7424/C7434Pin Data
Pin Names |
Share Pins |
I/O Type |
Reset Value |
Circuit Type |
|
|
|
|
|
P0.0–P0.3 |
SCK, SO, SI, BUZ |
I/O |
Input |
Type D |
|
|
|
|
|
P1.0 |
INT0 (note) |
I |
Input |
Type A-1 |
P1.1 |
INT1 (note) |
|
|
|
P1.2 |
INT2 (note) |
|
|
|
P1.3 |
INT4 |
I |
Input |
Type A |
|
|
|
|
|
P2.0–P2.3 |
AD0–AD3 |
I/O |
AD input |
Type F-3 |
|
|
|
|
|
P3.0 |
AD4 |
I/O |
Input |
Type F |
P3.1 |
AD5 |
|
|
Type F |
P3.2 |
CLO/TCL1 |
|
|
Type D |
P3.3 |
TCLO1/PWM |
|
|
Type D |
|
|
|
|
|
P4.0–P4.3 |
– |
I/O |
Input |
Type E |
P5.0–P5.3 |
|
|
|
|
|
|
|
|
|
P6.0 |
KS0 (note) |
I/O |
Input |
Type D |
P6.1 |
KS1 (note) |
|
|
|
P6.2 |
KS2 (note) |
|
|
|
P6.3 |
KS3 (note) |
|
|
|
P7.0–P7.3 |
– |
I/O |
Input |
Type D |
|
|
|
|
|
P8.0 |
TCL0 (note) |
I/O |
Input |
Type D |
P8.1 |
TCLO0 |
|
|
|
P8.2 |
– |
|
|
|
|
|
|
|
|
VDD, VSS |
– |
– |
– |
– |
XIN, XOUT |
– |
– |
– |
– |
RESET |
– |
I |
– |
Type B-2 (note) |
AVREF |
– |
– |
– |
– |
TEST |
– |
I |
– |
– |
|
|
|
|
|
NC |
– |
– |
– |
– |
|
|
|
|
|
NOTE: A noise filter circuit is built-in.
1-14
S3C7414/P7414/C7424/P7424/C7434/P7434 |
PRODUCT OVERVIEW |
|
|
PIN CIRCUIT DIAGRAMS
VDD
P-CHANNEL
IN
N-CHANNEL
Figure 1-8. Pin Circuit Type A
VDD
PULL-UP
RESISTOR
ENABLE
IN
CIRCUIT TYPE A
Figure 1-9. Pin Circuit Type A-1
VDD
1MΩ
RESET 
7pF
Figure 1-10. Pin Circuit Type B-2
VDD
P-CHANNEL
DATA
OUT
N-CHANNEL
OUTPUT
DISABLE
Figure 1-11. Pin Circuit Type C
1-15
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