Samsung S3C7235, S3C7238, S3P7235, S3P7238 Datasheet

S3C7238/P7238/C7235/P7235	PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

OVERVIEW

The S3C7238/C7235 single-chip CMOS microcontroller has been designed for high performance using Samsung's newest 4bitCPU core, SAM47 (Samsung Arrangeable Microcontrollers).

With features such as LCD direct drive capability, 8-bit timer/counter, and serial I/O, the S3C7238/C7235 offer an excellent design solution for a wide variety of applications that require LCD functions.

Up to 40 pins of the 80-pin QFP package can be dedicated to I/O. Six vectored interrupts provide fast response to internal and external events. In addition, the S3C7238/C7235's advanced CMOS technology provides for low power consumption and a wide operating voltage range.

OTP

The S3C7238/C7235 microcontroller is also available in OTP (One Time Programmable) version, S3P7238/P7235. S3P7238/P7235 microcontroller has an on-chip 8/16-Kbyte one-time-programmable EPROM instead of masked ROM. The S3P7238/P7235 is comparable to S3C7238/C7235, both in function and in pin configuration.

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PRODUCT OVERVIEW	S3C7238/P7238/C7235/P7235

FEATURES

Memory

–512 × 4-bit RAM

–8 K × 8-bit ROM (S3C7238/P7238)

–16 K × 8-bit ROM (S3C7235/P7235)

I/O Pins

–Input only: 8 pins

–I/O: 24 pins

–Output: 8 pins sharing with segment driver outputs

LCD Controller/Driver

–Maximum 16-digit LCD direct drive capability

–32 segment, 4 common pins

–Display modes: Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 or 1/3 bias), 1/4 duty (1/3 bias)

8-Bit Basic Timer

–Programmable interval timer

–Watchdog timer

8-Bit Timer/Counter 0

–Programmable 8-bit timer

–External event counter

–Arbitrary clock frequency output

–Serial I/O interface clock generator

Watch Timer

–Real-time and interval time measurement

–Four frequency outputs to BUZ pin

–Clock source generation for LCD

8-Bit Serial I/O Interface

–8-bit transmit/receive mode

–8-bit receive only mode

–LSB-first or MSB-first transmission selectable

–Internal or external clock source

Bit Sequential Carrier

–Support 16-bit serial data transfer in arbitrary format

Interrupts

–Three internal vectored interrupts

–Three external vectored interrupts

–Two quasi-interrupts

Memory-Mapped I/O Structure

–Data memory bank 15

Two Power-Down Modes

–Idle mode (only CPU clock stops)

–Stop mode (main or sub system oscillation stops)

Oscillation Sources

–Crystal, ceramic, or RC for main system clock

–Crystal or external oscillator for subsystem clock

–Main system clock frequency: 4.19 MHz (typical)

–Subsystem clock frequency: 32.768 kHz

–CPU clock divider circuit (by 4, 8, or 64)

Instruction Execution Times

–0.95, 1.91, 15.3 µs at 4.19 MHz (main)

–122 µs at 32.768 kHz (subsystem)

Operating Temperature

–– 40 °C to 85 °C

Operating Voltage Range

–1.8 V to 5.5 V

Package Type

–80-pin QFP

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S3C7238/P7238/C7235/P7235	PRODUCT OVERVIEW

BLOCK DIAGRAM

P1.3/TCL0

P2.0/TCLO0

P4.0-P4.3

P5.0-P5.3

P6.0-P6.3/

KS0-KS3

P7.0-P7.3/

KS4-KS7

P8.0-P8.7/

SEG24-SEG31

	Watch-Dog		Basic	Watch	P2.3/BUZ
	Timer		Timer	Timer
	XIN	XOUT					BIAS
INT0, INT1,INT2							VLC0-VLC2
RESET	XTIN	XTOUT					LCDCK/P3.0
8-Bit Timer/					LCD Drive/		LCDSY/P3.1
							COM0-COM3
Counter 0					Controller
			Instruction				SEG0-SEG23
Interrupt
			Register
Control	Clock
Block							P8.0-P8.7/
			4-Bit				SEG24-SEG31
I/O Port 3			Accumulator				P0.0/INT4
							P0.1/SCK
Internal					I/O Port	0
Interrupts							P0.2/SO
			Program
I/O Port 4							P0.3/SI
			Counter
							P1.0/INT0
			Program		Input Port 1		P1.1/INT1
							P1.2/INT2
Instruction Decoder			Status Word
							P1.3/TCL0
I/O Port 6
I/O Port 7							P2.0/TCLO0
			FLAGS		I/O Port 2		P2.1
							P2.2/CLO
Arithmetic and Logic Unit
							P2.3/BUZ
			Stack
							P3.0/LCDCK
			Pointer
I/O Port 8					I/O Port 3		P3.1/LCDSY
							P3.2
							P3.3
512 x 4-Bit		8/16-Kbyte			Serial I/O
					Port
Data		Program
Memory		Memory
				P0.1 P0.2		P0.3
				/SCK /SO		/SI

Figure 1-1. S3C7238/C7235 Simplified Block Diagram

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PRODUCT OVERVIEW	S3C7238/P7238/C7235/P7235

PIN ASSIGNMENTS

			SEG3		SEG4		SEG5		SEG6		SEG7		SEG8		SEG9			SEG10			SEG11		SEG12			SEG13			SEG14				SEG15		SEG16			SEG17				SEG18
		80			79		78		77		76		75		74		73			72			71			70			69			68			67			66			65
SEG2		1																																							64				SEG19
SEG1		2																																							63				SEG20
SEG0		3																																							62				SEG21
COM0		4																																							61				SEG22
COM1		5																																							60				SEG23
COM2		6																																							59				P8.0/SEG24
COM3		7																																							58				P8.1/SEG25
BIAS		8																																							57				P8.2/SEG26
VLC0		9																																							56				P8.3/SEG27
SDAT / VLC1		10																																							55				P8.4/SEG28
SCLK / VLC2		11												S3C7238																											54				P8.5/SEG29
VDD / VDD		12																																							53				P8.6/SEG30
														S3C7235
VSS / VSS		13																																							52				P8.7/SEG31
Xout		14													(TOP VIEW)																										51				P7.3/KS7
Xin		15																																							50				P7.2/KS6
TEST / TEST		16																																							49				P7.1/KS5
XTin		17																																							48				P7.0/KS4
XTout		18																																							47				P6.3/KS3
RESET / RESET		19																																							46				P6.2/KS2
P0.0/INT4		20																																							45				P6.1/KS1
P0.1/SCK		21																																							44				P6.0/KS0
P0.2/SO		22																																							43				P5.3
P0.3/SI		23																																							42				P5.2
P1.0/INT0		24																																							41				P5.1
		25			26		27		28		29		30		31		32			33			34			35			36			37			38			39			40
			P1.1/INT1		P1.2/INT2		P1.3/TCL0		P2.0/TCLO0		P2.1		P2.2/CLO		P2.3/BUZ			P3.0/LCDCK			P3.1/SCDSY			P3.2			P3.3			P4.0			P4.1			P4.2			P4.3			P5.0

Figure 1-2. S3C7238/C7235 80-QFP Pin Assignment Diagram

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S3C7238/P7238/C7235/P7235 PRODUCT OVERVIEW

PIN DESCRIPTIONS

Table 1-1. S3C7238/C7235 Pin Descriptions

	Pin Name	Pin	Description	Number	Share	Reset	Circuit
		Type			Pin	Value	Type
	P0.0	I	4-bit input port.	20	INT4	Input	A-1
	P0.1	I/O	1-bit and 4-bit read and test are possible.	21	SCK		D *
	P0.2	I/O	4-bit pull-up resistors are software assignable.	22	SO		D *
	P0.3	I		23	SI		A-1
	P1.0	I	4-bit input port.	24	INT0	Input	A-1
	P1.1		1-bit and 4-bit read and test are possible.	25	INT1
	P1.2		4-bit pull-up resistors are software assignable.	26	INT2
	P1.3			27	TCL0
	P2.0	I/O	4-bit I/O port.	28	TCLO0	Input	D
	P2.1		1-bit and 4-bit read/write and test are possible.	29	–
	P2.2		4-bit pull-up resistors are software assignable.	30	CLO
	P2.3			31	BUZ
	P3.0	I/O	4-bit I/O port.	32	LCDCK	Input	D
	P3.1		1-bit and 4-bit read/write and test are possible.	33	LCDSY
	P3.2		Each individual pin can be specified as input	34
	P3.3		or output. 4-bit pull-up resistors are software	35
			assignable.
	P4.0–	I/O	4-bit I/O ports. N-channel open-drain output up	36–43	–	Input	E
	P4.3		to 5 V. 1-, 4-, and 8-bit read/write and test are
	P5.0–		possible. Ports 4 and 5 can be paired to
	P5.3		support 8-bit data transfer. 4-bit pull-up
			resistors are software assignable.
	P6.0–	I/O	4-bit I/O ports. Port 6 pins are individually	44–51	KS0–KS3	Input	D *
	P6.3		software configurable as input or output. 1-bit		KS4–KS7
	P7.0–		and 4-bit read/write and test are possible. 4-bit
	P7.3		pull-up resistors are software assignable. Ports
			6 and 7 can be paired to enable 8-bit data
			transfer.
	P8.0–	O	Output port for 1-bit data (for use as CMOS	59–52	SEG24–	Output	H-16
	P8.7		driver only)		SEG31
	SEG0–	O	LCD segment signal output	3–1,	–	Output	H-15
	SEG23			80–60
	SEG24–	O	LCD segment signal output	59–52	P8.0–P8.7	Output	H-16
	SEG31
	COM0–	O	LCD common signal output	4–7	–	Output	H-15
	COM3
	VLC0–VLC2	–	LCD power supply. Voltage dividing resistors	9–11	SCLK	–	–
			are assignable by mask option		SDAT
	BIAS	–	LCD power control	8	–	–	–
	LCDCK	I/O	LCD clock output for display expansion	32	P3.0	Input	D

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PRODUCT OVERVIEW S3C7238/P7238/C7235/P7235

Table 1-1. S3C7238/C7235 Pin Descriptions (Continued)

Pin Name	Pin		Description	Number	Share	Reset	Circuit
	Type				Pin	Value	Type
LCDSY	I/O	LCD synchronization clock output for LCD		33	P3.1	Input	D
		display expansion
TCL0	I/O	External clock input for timer/counter 0		27	P1.3	Input	A-1
TCLO0	I/O	Timer/counter 0 clock output		28	P2.0	Input	D
SI	I	Serial interface data input		23	P0.3	Input	A-1
SO	I/O	Serial interface data output		22	P0.2	Input	D *
SCK	I/O	Serial I/O interface clock signal		21	P0.1	Input	D *
INT0	I	External interrupts. The triggering edge for		24	P1.0	Input	A-1
INT1		INT0 and INT1 is selectable. Only INT0 is		25	P1.1
		synchronized with the system clock.
INT2	I	Quasi-interrupt with detection of rising edge		26	P1.2	Input	A-1
		signals.
INT4	I	External interrupt input with detection of rising		20	P0.0	Input	A-1
		or falling edge
KS0–KS7	I/O	Quasi-interrupt inputs with falling edge		44–51	P6.0–P7.3	Input	D *
		detection.
CLO	I/O	CPU clock output		30	P2.2	Input	D
BUZ	I/O	2, 4, 8 or 16 kHz frequency output for buzzer		31	P2.3	Input	D
		sound with 4.19 MHz main system clock or
		32.768 kHz subsystem clock.
XIN,	–	Crystal, ceramic or RC oscillator pins for main		15,14	–	–	–
XOUT		system clock. (For external clock input, use
		XIN and input XIN‘s reverse phase to XOUT)
XTIN,	–	Crystal oscillator pins for subsystem clock.		17,18	–	–	–
XTOUT		(For external clock input, use XTIN and input
		XT	's reverse phase to XT )
		IN	OUT
VDD	–	Main power supply		12	–	–	–
VSS	–	Ground		13	–	–	–
RESET	–	Reset signal		19	–	Input	B
TEST	–	Test signal input (must be connected to VSS)		16	–	–	–

NOTES:

1.Pull-up resistors for all I/O ports are automatically disabled if they are configured to output mode.

2.D * Type has a schmitt trigger circuit at input.

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S3C7238/P7238/C7235/P7235	PRODUCT OVERVIEW

PIN CIRCUIT DIAGRAMS

VDD

P-CHANNEL

IN

N-CHNNEL

Figure 1-3. Pin Circuit Type A

VDD

PULL-UP

RESISTOR

RESISTOR P-CHANNEL ENABLE

IN

SCHMITT TRIGGER

Figure 1-4. Pin Circuit Type A-1 (P1, P0.0, P0.3)

VDD

P-CHANNEL

DATA

OUT

N-CHANNEL

OUTPUT

DISABLE

Figure 1-5. Pin Circuit Type C

VDD

PULL-UP

RESISTOR

RESISTOR

P-CHANNEL

ENABLE

DATA

CIRCUIT

I/O

OUTPUT TYPE C DISABLE

CIRCUIT TYPE A

Figure 1-6. Pin Circuit Type D (P0.1, P0.2, P2, P3, P6, P7)

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PRODUCT OVERVIEW	S3C7238/P7238/C7235/P7235

					VDD
							PULL-UP
PNE				VDD			RESISTOR

	RESISTOR
DATA	ENABLE
	P-CH
	I/O
OUTPUT	N-CH
ENABLE
	CIRCUIT TYPE A

Figure 1-7. Pin Circuit Type E (P4, P5)

VLC0

VLC1

LCD SEGMENT/

OUT

COMMON DATA

VLC2

Figure 1-8. Pin Circuit Type H-15 (SEG/COM)

VDD

VLC0

VLC1

LCD SEGMENT/

OUT

& PORT 8 DATA

VLC2

Figure 1-9. Pin Circuit Type H-16 (P8)

VDD

IN

SCHMITT TRIGGER

Figure 1-10. Pin Circuit Type B (RESET)

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S3C7238/P7238/C7235/P7235	ELECTRICAL DATA

14 ELECTRICAL DATA

OVERVIEW

In this section, information on S3C7238/C7235 electrical characteristics is presented as tables and graphics. The information is arranged in the following order:

Standard Electrical Characteristics

—Absolute maximum ratings

—D.C. electrical characteristics

—Main system clock oscillator characteristics

—Subsystem clock oscillator characteristics

—I/O capacitance

—A.C. electrical characteristics

—Operating voltage range

Miscellaneous Timing Waveforms

—A.C timing measurement point

—Clock timing measurement at XIN

—Clock timing measurement at XTIN

—TCL timing

—Input timing for RESET

—Input timing for external interrupts

—Serial data transfer timing

Stop Mode Characteristics and Timing Waveforms

—RAM data retention supply voltage in stop mode

—Stop mode release timing when initiated by RESET

—Stop mode release timing when initiated by an interrupt request

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ELECTRICAL DATA S3C7238/P7238/C7235/P7235

Table 14-1. Absolute Maximum Ratings

(TA = 25 °C)

	Parameter	Symbol	Conditions	Rating	Units
	Supply Voltage	VDD	–	– 0.3 to + 6.5	V
	Input Voltage	VI1	All I/O ports	– 0.3 to VDD + 0.3
	Output Voltage	VO	–	– 0.3 to VDD + 0.3
	Output Current High	IOH	One I/O pin active	– 15	mA
			All I/O ports active	– 35
	Output Current Low	IOL	One I/O pin active	+ 30 (Peak value)
				+ 15 (note)
			Total value for ports 0, 2, 3, and 5	+ 100 (Peak value)
				+ 60 (note)
			Total value for ports 4, 6, and 7	+ 100
				+ 60 (note)
	Operating Temperature	TA	–	– 40 to + 85	°C
	Storage Temperature	Tstg	–	– 65 to + 150
NOTE: The values for Output Current Low (IOL) are calculated as Peak Value ×				Duty .

Table 14-2. D.C. Electrical Characteristics

(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

	Parameter	Symbol	Conditions	Min	Typ	Max	Units
	Input high	VIH1	All input pins except those	0.7 VDD	–	VDD	V
	voltage		specified below for VIH2, VIH3
		VIH2	Ports 0, 1, 6, 7 and RESET	0.8 VDD	–	VDD
		VIH3	XIN, XOUT, XTIN and XTOUT	VDD – 0.1	–	VDD
	Input low	VIL1	Ports 2, 3, 4 and 5	–	–	0.3 VDD	V
	voltage	VIL2	Ports 0, 1, 6, 7 and RESET	–	–	0.2 VDD
		VIL3	XIN, XOUT, XTIN and XTOUT	–	–	0.1
	Output high	VOH1	VDD = 4.5 V to 5.5 V	VDD – 1.0	–	–	V
	voltage		Ports 0, 2, 3, 4, 5, 6, 7 and BIAS
			IOH = – 1 mA
		VOH2	VDD = 4.5 V to 5.5 V	VDD – 2.0	–	–
			Port 8 ONLY
			IOH = – 100 µA

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S3C7238/P7238/C7235/P7235 ELECTRICAL DATA

Table 14-2. D.C. Electrical Characteristics (Continued)

(TA = – 40 °C to + 85 °C, VDD = 1.8 V to 5.5 V)

	Parameter	Symbol	Conditions			Min	Typ	Max	Units
	Output low	VOL1	VDD = 4.5 V	to	5.5 V, Ports 0, 2–7	–	0.4	2	V
	voltage		IOL = 15 mA
		VOL2	VDD = 4.5 V	to	5.5 V, Port 8 only	–	–	1
			IOL = 100 µA
	Input high	ILIH1	VIN = VDD			–	–	3	µA
	leakage		All input pins except those specified
	current		below for ILIH2
		ILIH2	VIN = VDD			–	–	20
			XIN, XOUT, XTIN and XTOUT
	Input low	ILIL1	VIN = 0 V			–	–	– 3
	leakage		All input pins except XIN, XOUT,
	current		XTIN and XTOUT
		ILIL2	VIN = 0 V					– 20
			XIN, XOUT, XTIN and XTOUT
	Output high	ILOH1	VOUT = VDD			–	–	3	µA
	leakage		All output pins
	current
	Output low	ILOL	VOUT = 0 V					– 3
	leakage		All output pins
	current
	Pull-up	RL1	Ports 0–7			25	47	100	KΩ
	resistor		VIN = 0 V; VDD = 5 V
			VDD = 3 V			50
							95	200
		RL2	VIN = 0 V; VDD = 5 V, RESET			100	220	400
			VDD = 3 V			200
							450	800
	LCD voltage	RLCD	TA = 25 °C			50	93	140
	dividing
	resistor
	COM output	RCOM	VDD = 5 V			–	3	6
	impedance		VDD = 3 V				5	15
	SEG output	RSEG	VDD = 5 V				3	6
	impedance		VDD = 3 V				5	15
	COM output	VDC	VDD = 5 V (VLC0 – COMi)			–	± 45	± 90	mV
	voltage		Io = ± 15uA (I = 0–3)
	deviation
	SEG output	VDS	VDD = 5 V (VLC0-SEGi)			–	ñ 45	ñ 90	mV
	voltage		Io = ± 15μA (I = 0–31)
	deviation

14-3