NXP 74AHC2G125DC, 74AHC2G125DP, 74AHC2G125GD, 74AHCT2G125DC, 74AHCT2G125DP Schematic [ru]

74AHC2G125; 74AHCT2G125

Dual buffer/line driver; 3-state

Rev. 3 — 6 May 2013 Product data sheet

1. General description

The 74AHC2G125 and 74AHCT2G125 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A HIGH at nOE causes the output to assume a high-impedance OFF-state.

The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.

The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.

2.Features and benefits

Symmetrical output impedance

High noise immunity

Low power dissipation

Balanced propagation delays

Multiple package options

ESD protection:

HBM JESD22-A114E: exceeds 2000 V

MM JESD22-A115-A: exceeds 200 V

CDM JESD22-C101C: exceeds 1000 V

Specified from 40 C to +125 C

3.Ordering information

Table 1. Ordering information

Type number	Package
	Temperature range	Name	Description	Version
74AHC2G125DP	40 C to +125 C	TSSOP8	plastic thin shrink small outline package; 8 leads;	SOT505-2
			body width 3 mm; lead length 0.5 mm
74AHCT2G125DP
74AHC2G125DC	40 C to +125 C	VSSOP8	plastic very thin shrink small outline package;	SOT765-1
			8 leads; body width 2.3 mm
74AHCT2G125DC
74AHC2G125GD	40 C to +125 C	XSON8	plastic extremely thin small outline package; no	SOT996-2
			leads; 8 terminals; body 3 2 0.5 mm
74AHCT2G125GD

NXP Semiconductors	74AHC2G125; 74AHCT2G125
	Dual buffer/line driver; 3-state
4. Marking
Table 2. Marking codes
Type number	Marking
74AHC2G125DP	A25
74AHCT2G125DP	C25
74AHC2G125DC	A25
74AHCT2G125DC	C25
74AHC2G125GD	A25
74AHCT2G125GD	C25

5. Functional diagram

2	1A	1Y	6
				2
1	1OE				6
				1	1
					EN1
5	2A	2Y	3	5	nA	nY
					3
7	2OE			7	2
					EN2
					nOE

mce185	mce186	mna227
Fig 1. Logic symbol	Fig 2. IEC logic symbol	Fig 3. Logic diagram (one buffer)

6.Pinning information

6.1Pinning

74AHC2G125

74AHCT2G125

		1	8
1OE				VCC
	1A	2	7
				2OE
	2Y	3	6	1Y
GND		4	5	2A

001aaj260

Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)

74AHC2G125

74AHCT2G125

1OE			1			8	VCC
	1A			2		7
							2OE
	2Y			3		6	1Y
GND				4		5	2A
						001aaj261
					Transparent top view

Fig 5. Pin configuration SOT996-2 (XSON8)

74AHC_AHCT2G125

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 3 — 6 May 2013

2 of 16

NXP Semiconductors							74AHC2G125; 74AHCT2G125
								Dual buffer/line driver; 3-state
					6.2 Pin description
Table 3.					Pin description
Symbol					Pin		Description
					1, 7		output enable input (active LOW)
	1OE,		2OE
1A, 2A					2, 5		data input
GND					4		ground (0 V)
1Y, 2Y					6, 3		data output
VCC					8		supply voltage
7. Functional description
Table 4.					Function table[1]
Control						Input		Output
						nA		nY
nOE
L						L		L
L						H		H
H						X		Z

[1]H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

8. Limiting values

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol	Parameter	Conditions		Min	Max	Unit
VCC	supply voltage			0.5	+7.0	V
VI	input voltage			0.5	+7.0	V
IIK	input clamping current	VI < 0.5 V	[1]	20	-	mA
IOK	output clamping current	VO < 0.5 V or VO > VCC + 0.5 V	[1]	-	20	mA
IO	output current	0.5 V < VO < VCC + 0.5 V		-	25	mA
ICC	supply current			-	75	mA
IGND	ground current			75	-	mA
Tstg	storage temperature			65	+150	C
Ptot	total power dissipation	Tamb = 40 C to +125 C	[2]	-	250	mW

[1]The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2]For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K. For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K. For XSON8 package: above 45 C the value of Ptot derates linearly with 2.4 mW/K.

74AHC_AHCT2G125

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 3 — 6 May 2013

3 of 16

NXP Semiconductors	74AHC2G125; 74AHCT2G125
	Dual buffer/line driver; 3-state

9. Recommended operating conditions

Table 6. Recommended operating conditions

Voltages are referenced to GND (ground = 0 V).

Symbol	Parameter		Conditions				74AHC2G125					74AHCT2G125				Unit
						Min		Typ		Max		Min	Typ		Max
VCC	supply voltage					2.0		5.0	5.5		4.5		5.0	5.5		V
VI	input voltage					0		-	5.5		0		-	5.5		V
VO	output voltage					0		-		VCC	0		-		VCC	V
Tamb	ambient temperature					40		+25	+125			40	+25	+125		C
t/ V	input transition rise		VCC = 3.3 V 0.3 V			-		-	100		-		-	-		ns/V
	and fall rate
			VCC = 5.0 V 0.5 V			-		-	20		-		-	20		ns/V
10. Static characteristics
Table 7.	Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol	Parameter	Conditions					25 C		40 C to +85 C				40 C to +125 C				Unit
				Min			Typ	Max		Min		Max	Min		Max
74AHC2G125
VIH	HIGH-level	VCC = 2.0 V		1.5		-		-	1.5		-		1.5	-			V
	input voltage
		VCC = 3.0 V		2.1		-		-	2.1		-		2.1	-			V
		VCC = 5.5 V		3.85		-		-	3.85		-		3.85	-			V
VIL	LOW-level	VCC = 2.0 V		-		-		0.5	-		0.5		-	0.5			V
	input voltage
		VCC = 3.0 V		-		-		0.9	-		0.9		-	0.9			V
		VCC = 5.5 V		-		-		1.65	-		1.65		-	1.65			V
VOH	HIGH-level	VI = VIH or VIL
	output voltage
		IO = 50 A; VCC = 2.0 V		1.9		2.0		-	1.9		-		1.9	-			V
		IO = 50 A; VCC = 3.0 V		2.9		3.0		-	2.9		-		2.9	-			V
		IO = 50 A; VCC = 4.5 V		4.4		4.5		-	4.4		-		4.4	-			V
		IO = 4.0 mA; VCC = 3.0 V		2.58		-		-	2.48		-		2.40	-			V
		IO = 8.0 mA; VCC = 4.5 V		3.94		-		-	3.8		-		3.70	-			V
VOL	LOW-level	VI = VIH or VIL
	output voltage
		IO = 50 A; VCC = 2.0 V		-		0		0.1	-		0.1		-	0.1			V
		IO = 50 A; VCC = 3.0 V		-		0		0.1	-		0.1		-	0.1			V
		IO = 50 A; VCC = 4.5 V		-		0		0.1	-		0.1		-	0.1			V
		IO = 4.0 mA; VCC = 3.0 V		-		-		0.36	-		0.44		-	0.55			V
		IO = 8.0 mA; VCC = 4.5 V		-		-		0.36	-		0.44		-	0.55			V
IOZ	OFF-state	VI = VCC or GND;		-		-		0.25	-		2.5		-	10			A
	output current	VCC = 5.5 V
II	input leakage	VI = 5.5 V or GND;		-		-		0.1	-		1.0		-	2.0			A
	current	VCC = 0 V to 5.5 V
ICC	supply current	VI = VCC or GND; IO = 0 A;		-		-		1.0	-		10		-	40			A
		VCC = 5.5 V
74AHC_AHCT2G125			All information provided in this document is subject to legal disclaimers.											© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 3 — 6 May 2013

4 of 16

NXP Semiconductors				74AHC2G125; 74AHCT2G125
									Dual buffer/line driver; 3-state
Table 7.	Static characteristics …continued
Voltages are referenced to GND (ground = 0 V).
Symbol	Parameter		Conditions			25 C		40 C to +85 C		40 C to +125 C		Unit
					Min	Typ	Max	Min	Max	Min	Max
CI	input			-		1.5	10	-	10	-	10	pF
	capacitance
74AHCT2G125
VIH	HIGH-level		VCC = 4.5 V to 5.5 V	2.0		-	-	2.0	-	2.0	-	V
	input voltage
VIL	LOW-level		VCC = 4.5 V to 5.5 V	-		-	0.8	-	0.8	-	0.8	V
	input voltage
VOH	HIGH-level		VI = VIH or VIL; VCC = 4.5 V
	output voltage
			IO = 50 A	4.4		4.5	-	4.4	-	4.4	-	V
			IO = 8.0 mA	3.94		-	-	3.8	-	3.70	-	V
VOL	LOW-level		VI = VIH or VIL; VCC = 4.5 V
	output voltage
			IO = 50 A	-		0	0.1	-	0.1	-	0.1	V
			IO = 8.0 mA	-		-	0.36	-	0.44	-	0.55	V
IOZ	OFF-state		VI = VCC or GND;	-		-	0.25	-	2.5	-	10	A
	output current		VCC = 5.5 V
II	input leakage		VI = 5.5 V or GND;	-		-	0.1	-	1.0	-	2.0	A
	current		VCC = 0 V to 5.5 V
ICC	supply current		VI = VCC or GND; IO = 0 A;	-		-	1.0	-	10	-	40	A
			VCC = 5.5 V
ICC	additional		per input pin; VI = 3.4 V;	-		-	1.35	-	1.5	-	1.5	mA
	supply current		other inputs at VCC or GND;
			IO = 0 A; VCC = 5.5 V
CI	input			-		1.5	10	-	10	-	10	pF
	capacitance
11. Dynamic characteristics
Table 8.	Dynamic characteristics
GND = 0 V; for test circuit see Figure 8.
Symbol	Parameter	Conditions				25 C		40 C to +85 C		40 C to +125 C		Unit
					Min	Typ	Max	Min	Max	Min	Max
74AHC2G125
tpd	propagation	nA to nY; see Figure 6		[1]
	delay
			VCC = 3.0 V to 3.6 V	[2]
			CL = 15 pF	-		4.7	8.0	1.0	9.5	1.0	11.5	ns
			CL = 50 pF	-		6.6	11.5	1.0	13.0	1.0	14.5	ns
			VCC = 4.5 V to 5.5 V	[3]
			CL = 15 pF	-		3.4	5.5	1.0	6.5	1.0	7.0	ns
			CL = 50 pF	-		4.8	7.5	1.0	8.5	1.0	9.5	ns

74AHC_AHCT2G125

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 3 — 6 May 2013

5 of 16

NXP Semiconductors					74AHC2G125; 74AHCT2G125
										Dual buffer/line driver; 3-state
Table 8.	Dynamic characteristics …continued
GND = 0 V; for test circuit see Figure 8.
Symbol	Parameter	Conditions					25 C		40 C to +85 C		40 C to +125 C		Unit
						Min	Typ	Max	Min	Max	Min	Max
ten	enable time				[1]
		nOE		to nY; see Figure 7
			VCC = 3.0 V to 3.6 V		[2]
				CL = 15 pF	-		5.0	8.0	1.0	9.5	1.0	11.5	ns
				CL = 50 pF	-		6.9	11.5	1.0	13.0	1.0	14.5	ns
			VCC = 4.5 V to 5.5 V		[3]
				CL = 15 pF	-		3.6	5.1	1.0	6.0	1.0	6.5	ns
				CL = 50 pF	-		4.9	7.5	1.0	8.5	1.0	9.5	ns
tdis	disable time				[1]
		nOE		to nY; see Figure 7
			VCC = 3.0 V to 3.6 V		[2]
				CL = 15 pF	-		6.0	9.7	1.0	11.5	1.0	12.5	ns
				CL = 50 pF	-		8.3	13.2	1.0	15.0	1.0	16.5	ns
			VCC = 4.5 V to 5.5 V		[3]
				CL = 15 pF	-		4.1	6.8	1.0	8.0	1.0	8.5	ns
				CL = 50 pF	-		5.7	8.8	1.0	10.0	1.0	11.0	ns
CPD	power	per buffer;			[4] -		9	-	-	-	-	-	pF
	dissipation	CL = 50 pF; fi = 1 MHz;
	capacitance	VI = GND to VCC
74AHCT2G125
tpd	propagation	nA to nY; see Figure 6			[1]
	delay
			VCC = 4.5 V to 5.5 V		[3]
				CL = 15 pF	-		3.4	5.5	1.0	6.5	1.0	6.5	ns
				CL = 50 pF	-		4.8	7.5	1.0	8.5	1.0	8.5	ns
ten	enable time				[1]
		nOE		to nY; see Figure 7
			VCC = 4.5 V to 5.5 V		[3]
				CL = 15 pF	-		3.9	5.1	1.0	6.0	1.0	6.0	ns
				CL = 50 pF	-		5.1	7.5	1.0	8.5	1.0	8.5	ns
tdis	disable time				[1]
		nOE		to nY; see Figure 7
			VCC = 4.5 V to 5.5 V		[3]
				CL = 15 pF	-		4.5	6.8	1.0	8.0	1.0	8.0	ns
				CL = 50 pF	-		6.1	8.8	1.0	10.0	1.0	10.0	ns

74AHC_AHCT2G125

All information provided in this document is subject to legal disclaimers.

© NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 3 — 6 May 2013

6 of 16