Motorola MC14029BCL, MC14029BCP, MC14029BD Datasheet

MOTOROLA CMOS LOGIC DATAMC14029B

120

  

The MC14029B Binary/Decade up/down counter is constructed with MOS P–channel and N–channel enhancement mode d evices in a single monolithic structure. The counter consists of type D flip–flop stages with a gating structure to provide toggle flip–flop capability. The counter can be used in either Binary or BCD operation. This complementary MOS counter finds primary use in up/down and difference counting and f requency synthesizer applications where low power dissipation and/or high noise immunity is desired. It is also useful in A/D and D/A conversion and for magnitude and sign generation.

• Diode Protection on All Inputs

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Internally Synchronous for High Speed

• Logic Edge–Clocked Design — Count Occurs on Positive Going Edge

of Clock

• Asynchronous Preset Enable Operation

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range

• Pin for Pin Replacement for CD4029B

MAXIMUM RATINGS* (Voltages Referenced to V

)

Symbol

Parameter

Value

Unit

DC Supply Voltage

– 0.5 to + 18.0

Vin, V

out

Input or Output Voltage (DC or Transient)

– 0.5 to VDD + 0.5

lin, l

out

Input or Output Current (DC or Transient), per Pin

± 10

Power Dissipation, per Package†

500

stg

Storage Temperature

– 65 to + 150

Lead Temperature (8–Second Soldering)

260

*Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C

TRUTH TABLE

Carry In Up/Down

Preset

Enable

Action

1 X 0 No Count 0 1 0 Count Up 0 0 0 Count Down X X 1 Preset

X = Don’t Care



SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3 1/94



L SUFFIX

CERAMIC CASE 620

ORDERING INFORMATION

MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBD SOIC

TA = – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 648

D SUFFIX

SOIC

CASE 751B

125

CLK

B/D

U/D

out

PIN ASSIGNMENT

MOTOROLA CMOS LOGIC DATA

121

MC14029B

ELECTRICAL CHARACTERISTICS (Voltages Referenced to V

)

– 55_C

25_C

125_C

Characteristic

Symbol

Vdc

Min

Max

Min

Typ #

Max

Min

ÎÎÎ

Max

Unit

“0” Level

Vin = VDD or 0

5.0 10 15

— — —

0.05

— — —

0 0 0

0.05

— — —

ÎÎÎ

0.05

Vdc

“1” Level

Vin = 0 or V

5.0 10 15

4.95

9.95

14.95

— — —

4.95

9.95

14.95

5.0 10 15

— — —

4.95

9.95

14.95

ÎÎÎ

— — —

Vdc

“0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)

5.0 10 15

— — —

1.5

3.0

4.0

— — —

2.25

4.50

6.75

1.5

3.0

4.0

— — —

ÎÎÎ

1.5

3.0

4.0

Vdc

“1” Level (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)

5.0 10 15

3.5

7.0 11

— — —

3.5

7.0 11

2.75

5.50

8.25

— — —

3.5

7.0 11

ÎÎÎ

— — —

Vdc

5.0

5.0 10 15

– 3.0

– 0.64

– 1.6 – 4.2

— — — —

– 2.4

– 0.51

– 1.3 – 3.4

– 4.2 – 0.88 – 2.25

– 8.8

— — — —

– 1.7

– 0.36

– 0.9 – 2.4

ÎÎÎ

— — — —

mAdc

5.0 10 15

0.64

1.6

4.2

— — —

0.51

1.3

3.4

0.88

2.25

8.8

— — —

0.36

0.9

2.4

ÎÎÎ

— — —

mAdc

Input Current

—

± 0.1

—

±0.00001

± 0.1

—

ÎÎÎ

± 1.0

µAdc

Input Capacitance

(Vin = 0)

—

5.0

7.5

—

ÎÎÎ

—

Quiescent Current

(Per Package)

5.0 10 15

— — —

5.0 10 20

— — —

0.005

0.010

0.015

5.0 10 20

— — —

ÎÎÎ

150 300 600

µAdc

Total Supply Current**†

(Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching)

5.0 10 15

IT = (0.58 µA/kHz) f + I

IT = (1.20 µA/kHz) f + I

IT = (1.70 µA/kHz) f + I

µAdc

#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. **The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.

This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and V

out

should be constrained to the range VSS ≤ (Vin or V

out

) ≤ VDD.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.

Output Voltage

Input Voltage

Output Drive Current

(VOH = 2.5 Vdc) Source (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink (VOL = 0.5 Vdc) (VOL = 1.5 Vdc)

MOTOROLA CMOS LOGIC DATAMC14029B

122

SWITCHING CHARACTERISTICS* (C

= 50 pF, TA = 25_C)

ÎÎÎÎ

ОООООООООО

All Types

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎÎ

Min

Typ #

Max

Unit

Output Rise and Fall Time

TLH

, t

THL

= (1.5 ns/pF) CL + 25 ns

TLH

, t

THL

= (0.75 ns/pF) CL + 12.5 ns

TLH

, t

THL

= (0.55 ns/pF) CL + 9.5 ns

ÎÎÎÎ

TLH

THL

5.0 10 15

ÎÎÎÎ

— — —

100

50 40

200 100

ÎÎÎÎ

PLH

PHL

5.0 10 15

ÎÎÎÎ

— — —

200 100

400 200 180

out

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

ÎÎÎÎ

PLH

PHL

5.0 10 15

ÎÎÎÎ

— — —

250 130

500 260 190

out

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

to C

out

PLH

, t

PHL

= (1.7 ns/pF) CL + 95 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 47 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 35 ns

ÎÎÎÎ

PLH

PHL

5.0 10 15

ÎÎÎÎ

— — —

175

50 50

360 120 100

out

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

to C

out

PLH

, t

PHL

= (1.7 ns/pF) CL + 95 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 47 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 35 ns

PE to Q

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

ÎÎÎÎ

PLH

PHL

5.0 10 15

ÎÎÎÎ

— — —

235 100

470 200 160

out

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

to C

out

PLH

, t

PHL

= (1.7 ns/pF) CL + 95 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 47 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 35 ns

PE to Q

PLH

, t

PHL

= (1.7 ns/pF) CL + 230 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 97 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 75 ns

PE to C

out

PLH

, t

PHL

= (1. 7 ns/pF) CL + 465 ns

PLH

, t

PHL

= (0.66 ns/pF) CL + 192 ns

PLH

, t

PHL

= (0.5 ns/pF) CL + 125 ns

ÎÎÎÎ

PLH

PHL

5.0 10 15

ÎÎÎÎ

— — —

320 145 105

640 290 210

Clock Pulse Width

ÎÎÎÎ

W(cl)

5.0 10 15

ÎÎÎÎ

180

80 60

90 40 30

— — —

Clock Pulse Frequency

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

— — —

4.0

8.0 10

2.0

4.0

5.0

MHz

Preset Removal Time The Preset Signal must be low prior to a positive–going transition of the clock.

ÎÎÎÎ

rem

5.0 10 15

ÎÎÎÎ

160

80 60

80 40 30

— — —

Clock Rise and Fall Time

ÎÎÎÎ

r(cl)

f(cl)

5.0 10

1 5

ÎÎÎÎ

— — —

5 4

µs

Carry In Setup Time

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

150

60 40

75 30 20

— — —

Up/Down Setup Time

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

340 140 100

170

70 50

— — —

Binary/Decade Setup Time

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

320 140 100

160

70 50

— — —

Preset Enable Pulse Width

ÎÎÎÎ

5.0 10 15

ÎÎÎÎ

130

70 50

65 35 25

— — —

*The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

Propagation Delay Time

Clk to Q

Clk to C

, t

PLH

= (1.7 ns/pF) CL + 230 ns

PHL

, t

= (0.66 ns/pF) CL + 97 ns

PHL

, t

= (0.5 ns/pF) CL + 75 ns

PHL

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