MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The 3886 group is the 8-bit microcomputer based on the 740 family core technology.
The 3886 group is designed for controlling systems that require analog signal processing and include two serial I/O functions, A-D converters, D-A converters, system data bus interface function, watchdog timer, and comparator circuit.
The multi-master I2C bus interface can be added by option.
<Microcomputer mode> |
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●Basic machine-language instructions |
...................................... 71 |
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●Minimum instruction execution time .................................. |
0.4 μs |
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(at 10 MHz oscillation frequency) |
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●Memory size |
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ROM ................................................................. |
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32K to 60K bytes |
RAM ............................................................... |
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1024 to 2048 bytes |
●Programmable input/output ports ............................................ |
72 |
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●Software pull-up resistors ................................................. |
Built-in |
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●Interrupts ................................................. |
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21 sources, 16 vectors |
(Included key input interrupt) |
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●Timers ............................................................................. |
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8 - bit 4 |
●Serial I/O1 .................... |
8-bit 1(UART or Clock-synchronized) |
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●Serial I/O2 ................................... |
8-bit 1(Clock-synchronized) |
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●PWM output circuit ....................................................... |
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14 - bit 2 |
●Bus interface .................................................................... |
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2 bytes |
●I2C bus interface (option) ............................................. |
1 channel |
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●A-D converter ............................................... |
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10 - bit 8 channels |
●D-A converter ................................................. |
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8 - bit 2 channels |
●Comparator circuit ...................................................... |
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8 channels |
●Watchdog timer ............................................................ |
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16 - bit 1 |
●Clock generating circuit ..................................... |
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Built - in 2 circuits |
(connect to external ceramic resonator or quartz-crystal oscillator)
●Power source voltage |
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In high-speed mode .................................................. |
4.0 to 5.5 V |
(at 10 MHz oscillation frequency) |
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In middle-speed mode ........................................... |
2.7 to 5.5 V(*) |
(at 10 MHz oscillation frequency) |
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In low-speed mode ............................................... |
2.7 to 5.5 V (*) |
(at 32 kHz oscillation frequency) |
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(*: 4.0 to 5.5 V for Flash memory version)
●Power dissipation |
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In high-speed mode .......................................................... |
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40 mW |
(at 10 MHz oscillation frequency, at 5 V power source voltage) |
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In low-speed mode ............................................................ |
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60 μW |
(at 32 kHz oscillation frequency, at 3 V power source voltage) |
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●Memory expansion possible (only for M38867M8A/E8A) |
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●Operating temperature range .................................... |
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–20 to 85°C |
<Flash memory mode> |
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●Supply voltage ................................................. |
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VCC = 5 V ± 10 % |
●Program/Erase voltage ............................... |
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VPP = 11.7 to 12.6 V |
●Programming method ...................... |
Programming in unit of byte |
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●Erasing method |
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Batch erasing ........................................ |
Parallel/Serial I/O mode |
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Block erasing .................................... |
CPU reprogramming mode |
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●Program/Erase control by software command |
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●Number of times for programming/erasing |
............................ 100 |
●Operating temperature range (at programming/erasing)
..................................................................... Normal temperature
■Notes
1.The flash memory version cannot be used for application embedded in the MCU card.
2.Power source voltage Vcc of the flash memory version is 4.0 to 5.5 V.
Household product, consumer electronics, communications, note book PC, etc.
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
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2/ONW |
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3/RESETOUT |
4/φ |
5/SYNC |
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6/WR |
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7/RD |
0/P3REF/AD0 |
1/AD1 |
2/AD2 |
3/AD3 |
4/AD4 |
5/AD5 |
6/AD6 |
7/AD7 |
0/AD8 |
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1/AD9 |
2/AD10 |
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3/AD11 |
4/AD12 |
5/AD13 |
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P3 |
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P3 |
P3 |
P3 |
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P3 |
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P3 |
P0 |
P0 |
P0 |
P0 |
P0 |
P0 |
P0 |
P0 |
P1 |
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P1 |
P1 |
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P1 |
P1 |
P1 |
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60 |
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55 |
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46 |
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45 |
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44 |
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42 |
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41 |
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P31/PWM10 |
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61 |
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40 |
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P16/AD14 |
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P30/PWM00 |
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P17/AD15 |
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62 |
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39 |
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P87/DQ7 |
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P20/DB0 |
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63 |
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38 |
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P86/DQ6 |
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P21/DB1 |
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64 |
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37 |
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P85/DQ5 |
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P22/DB2 |
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65 |
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36 |
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P84/DQ4 |
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P23/DB3 |
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66 |
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35 |
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P83/DQ3 |
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67 |
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34 |
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P24/DB4 |
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P82/DQ2 |
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68 |
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M38867M8A-XXXHP |
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33 |
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P25/DB5 |
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P80/DQ0 |
70 |
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31 |
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P27/DB7 |
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P81/DQ1 |
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69 |
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M38867E8AHP |
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32 |
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P26/DB6 |
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VSS |
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VCC |
71 |
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30 |
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VREF |
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72 |
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29 |
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XOUT |
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AVSS |
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73 |
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28 |
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XIN |
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P67/AN7 |
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74 |
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27 |
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P40/XCOUT |
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P66/AN6 |
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75 |
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26 |
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P41/XCIN |
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P65/AN5 |
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76 |
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25 |
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RESET |
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VPP |
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P64/AN4 |
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77 |
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24 |
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CNVSS |
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P42/INT0/OBF00 |
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P63/AN3 |
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78 |
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23 |
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P62/AN2 |
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79 |
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22 |
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P43/INT1/OBF01 |
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P61/AN1 |
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80 |
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21 |
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P44/RXD |
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1 |
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P60/AN0 |
P77/SCL |
P76/SDA |
P75/INT41 |
P74/INT31 |
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/SP73 RDY2/INT21 |
P72/SCLK2 |
P71/SOUT2 |
P70/SIN2 |
/DAP57 2/PWM11 |
6/DAP51/PWM01 |
P55/CNTR1 |
P54/CNTR0 |
P53/INT40/W |
P52/INT30/R |
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P51/INT20/S0 |
P50/A0 |
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P47/SRDY1/S1 |
/SP46CLK1/OBF10 |
P45/TXD |
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: PROM version |
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Note: The pin number and the position of the |
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Package type : 80P6Q-A |
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function pin may change by the kind of |
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package. |
Fig. 1 M38867M8A-XXXHP, M38867E8AHP pin configuration
PIN CONFIGURATION (TOP VIEW)
P87/DQ7 |
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65 |
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P86/DQ6 |
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66 |
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P85/DQ5 |
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67 |
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P84/DQ4 |
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68 |
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P83/DQ3 |
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69 |
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P82/DQ2 |
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70 |
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P81/DQ1 |
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71 |
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P80/DQ0 |
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72 |
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VCC |
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VREF |
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AVSS |
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P67/AN7 |
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P66/AN6 |
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P65/AN5 |
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78 |
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P64/AN4 |
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P63/AN3 |
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80 |
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P30/PWM00 |
P31/PWM10 |
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P32/ONW |
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P33/RESETOUT |
P34/φ |
P35/SYNC |
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P36/WR |
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P37/RD |
P00/P3REF/AD0 |
P01/AD1 |
P02/AD2 |
P03/AD3 |
P04/AD4 |
P05/AD5 |
P06/AD6 |
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P07/AD7 |
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P10/AD8 |
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P11/AD9 |
P12/AD10 |
P13/AD11 |
P14/AD12 |
P15/AD13 |
P16/AD14 |
P17/AD15 |
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64 |
63 |
62 |
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59 |
58 |
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57 |
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56 |
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53 |
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49 |
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48 |
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47 |
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46 |
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M38867E8AFS |
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1 |
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P75/INT41 |
P74/INT31 |
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P71/SOUT2 |
P70/SIN2 |
P57/DA2/PWM11 |
P56/DA1/PWM01 |
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P47/SRDY1/S1 |
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P45/TXD |
P44/RXD |
P43/INT1/OBF01 |
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P62/AN2 |
P61/AN1 |
P60/AN0 |
P77/SCL |
P76/SDA |
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P73/SRDY2/INT21 |
P72/SCLK2 |
P55/CNTR1 |
P54/CNTR0 |
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P53/INT40/W |
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P52/INT30/R |
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P51/INT20/S0 |
P50/A0 |
P46/SCLK1/OBF10 |
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40 |
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P20/DB0 |
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39 |
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P21/DB1 |
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38 |
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P22/DB2 |
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37 |
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P23/DB3 |
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36 |
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P24/DB4 |
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35 |
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P25/DB5 |
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34 |
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P26/DB6 |
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33 |
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P27/DB7 |
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32 |
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VSS |
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31 |
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XOUT |
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30 |
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XIN |
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29 |
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P40/XCOUT |
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28 |
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P41/XCIN |
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27 |
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RESET |
VPP |
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26 |
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CNVSS |
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25 |
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P42/INT0/OBF00 |
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Package type : 80D0
Note: The pin number and the position of the function pin may change by the kind of package.
Fig. 2 M38867E8AFS pin configuration
2
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
PIN CONFIGURATION (TOP VIEW)
|
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P32 |
P33 |
P34 |
P35 |
P36 |
P37 |
P0/P30REF |
P01 |
P02 |
P03 |
P04 |
P05 |
P06 |
P07 |
P10 |
P11 |
P12 |
P13 |
P14 |
P15 |
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60 |
59 |
58 |
57 |
56 |
55 |
54 |
53 |
52 |
51 |
50 |
49 |
48 |
47 |
46 |
45 |
44 |
43 |
42 |
41 |
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P31/PWM10 |
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61 |
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40 |
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P16 |
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P30/PWM00 |
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39 |
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P17 |
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P87/DQ7 |
63 |
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38 |
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P20 |
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P86/DQ6 |
64 |
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37 |
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P21 |
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P85/DQ5 |
65 |
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36 |
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P22 |
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P84/DQ4 |
66 |
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35 |
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P23 |
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P83/DQ3 |
67 |
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34 |
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P24 |
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P82/DQ2 |
68 |
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33 |
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P25 |
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P80/DQ0 |
70 |
M38869MFA-XXXGP/HP 31 |
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P27 |
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P81/DQ1 |
69 |
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32 |
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P26 |
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VCC |
71 |
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M38869FFAGP/HP |
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30 |
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VSS |
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VREF |
72 |
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29 |
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XOUT |
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AVSS |
73 |
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28 |
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XIN |
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P67/AN7 |
74 |
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27 |
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P40/XCOUT |
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P66/AN6 |
75 |
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26 |
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P41/XCIN |
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P65/AN5 |
76 |
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25 |
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RESET |
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P64/AN4 |
77 |
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24 |
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CNVSS |
VPP |
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P63/AN3 |
78 |
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23 |
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P42/INT0/OBF00 |
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P62/AN2 |
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79 |
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22 |
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P43/INT1/OBF01 |
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P61/AN1 |
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80 |
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21 |
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P44/RXD |
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1 |
2 |
3 |
4 |
5 |
6 |
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8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
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P6/AN00 |
P7/S7CL |
P7/S6DA |
P7/INT541 |
P7/INT431 |
P7/S/INT3RDY221 |
P7/S2CLK2 |
P7/S1OUT2 |
P7/S0IN2 |
P5/DA/PWM7211 |
P5/DA/PWM6101 |
P5/CNTR51 |
P5/CNTR40 |
P5/INT/W340 |
P5/INT/R230 |
P5/INT/S1200 |
P5/A00 |
P4/S/S7RDY11 |
P4/S/OBF6CLK110 |
P4/TD5X |
Package type : 80P6S-A/80P6Q-A
Fig. 3 M38869MFA-XXXGP/HP, M38869FFAGP/HP pin configuration
: Flash memory version
Note: The pin number and the position of the function pin may change by the kind of package.
3
4 |
diagramblockFunctional4.Fig |
FUNCTIONAL BLOCK DIAGRAM (Package : 80P6Q-A, 80P6S-A) |
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BLOCKFUNCTIONAL |
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Main-clock |
Main-clock |
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Reset input |
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input |
output |
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CNVSS |
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XIN |
XOUT |
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VSS |
VCC |
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RESET |
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28 |
29 |
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30 |
71 |
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25 |
24 |
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Sub-clock Sub-clock |
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input |
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output |
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XCIN |
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XCOUT |
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Clock generating circuit |
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Timer |
1( 8 ) |
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Prescaler |
12(8) |
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Timer |
2( 8 ) |
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Prescaler |
X(8) |
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Timer |
X( 8 ) |
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Watchdog |
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Prescaler |
Y(8) |
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Timer |
Y( 8 ) |
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Reset |
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timer |
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2 |
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SI/O2(8) |
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INT20, |
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PWM01 |
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PWM11 |
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-SINGLE |
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I |
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C |
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converter |
D-A |
D-A |
SI/O1(8) |
Comparator |
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PWM0(14) |
PWM1(14) |
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(10) |
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converter 2 |
converter |
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SCL SDA |
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(8) |
1(8) |
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PWM00, |
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PWM10, |
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Bus interface |
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INT21, |
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INT30, |
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XCOUT |
Key-on |
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MICROCOMPUTERCMOSBIT-8CHIP |
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MICROCOMPUTERSMITSUBISHI |
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DQ0 |
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XCIN |
wake-up |
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Group3886 |
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INT31, |
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INT40 |
INT0, |
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to |
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INT41 |
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INT1 |
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DQ7 |
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P8(8) |
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P7(8) |
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P6(8) |
P5(8) |
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P4(8) |
P3(8) |
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P2(8) |
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P1(8) |
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P0(8) |
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P3REF |
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63 64 65 66 67 68 69 70 |
2 |
3 |
4 |
5 |
6 |
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8 |
9 |
72 73 |
74 75 76 77 78 79 80 1 |
10 11 12 13 14 15 16 17 |
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18 19 20 21 22 23 26 27 |
55 56 57 58 59 60 61 62 |
31 32 33 34 35 36 37 38 |
39 40 41 42 43 44 45 46 |
47 48 49 50 51 52 53 54 |
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I/O port P8 |
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I/O port P7 |
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I/O port P6 |
I/O port P5 |
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I/O port P4 |
I/O port P3 |
I/O port P2 |
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I/O port P1 |
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I/O port P0 |
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VREF |
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AVSS |
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MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 1 Pin description (1)
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Pin |
Name |
Functions |
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Function except a port function |
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VCC, VSS |
Power source |
•Apply voltage of 2.7 V – 5.5 V to Vcc, and 0 V to Vss. |
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•In the flash memory version, apply voltage of 4.0 V – 5.5 V to Vcc, and 0 V to Vss |
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•This pin controls the operation mode of the chip. |
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•Normally connected to VSS. |
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CNVSS |
CNVSS input |
•If this pin is connected to Vcc, the internal ROM is inhibited and an external memory is accessed. |
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•In the flash memory version, connected to VSS. |
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•In the EPROM version or the flash memory version, this pin functions as the VPP power source input pin. |
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VREF |
Reference voltage |
•Reference voltage input pin for A-D and D-A converters. |
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AVSS |
Analog power source |
•Analog power source input pin for A-D and D-A converters. |
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•Connect to VSS. |
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Reset input |
•Reset input pin for active “L”. |
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RESET |
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XIN |
Clock input |
•Input and output pins for the clock generating circuit. |
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•Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set |
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the oscillation frequency. |
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XOUT |
Clock output |
•When an external clock is used, connect the clock source to the XIN pin and leave the XOUT |
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pin open. |
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P00/P3REF |
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•8-bit CMOS I/O port. |
•Comparator reference power source |
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•I/O direction register allows each pin to be individually |
input pin |
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I/O port P0 |
programmed as either input or output. |
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•When the external memory is used, these pins are used as the address bus. |
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P01–P07 |
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•CMOS compatible input level. |
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•CMOS 3-state output structure or N-channel open-drain output structure. |
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•8-bit CMOS I/O port. |
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•I/O direction register allows each pin to be individually programmed as either input or output. |
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P10–P17 |
I/O port P1 |
•When the external memory is used, these pins are used as the address bus. |
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•CMOS compatible input level. |
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•CMOS 3-state output structure or N-channel open-drain output structure. |
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•8-bit CMOS I/O port. |
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•I/O direction register allows each pin to be individually programmed as either input or output. |
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P20–P27 |
I/O port P2 |
•When the external memory is used, these pins are used as the data bus. |
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•CMOS compatible input level. |
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•CMOS 3-state output structure. |
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•P24 to P27 (4 bits) are enabled to output large current for LED drive (only in single-chip mode). |
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•8-bit CMOS I/O port. |
•Key-on wake-up input pin |
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P30/PWM00 |
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•I/O direction register allows each pin to be individually |
•Comparator input pin |
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programmed as either input or output. |
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•PWM output pin |
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P31/PWM10 |
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•When the external memory is used, these pins are |
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I/O port P3 |
used as the control bus. |
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•CMOS compatible input level. |
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•Key-on wake-up input pin |
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•CMOS 3-state output structure. |
•Comparator input pin |
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P32–P37 |
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•These pins function as key-on wake-up and compara- |
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tor input. |
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•These pins are enabled to control pull-up. |
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5
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 2 Pin description (2)
Pin |
Name |
Functions |
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Function except a port function |
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P40/XCOUT |
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•8-bit I/O port with the same function as port P0. |
•Sub-clock generating circuit I/O |
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<Input level> |
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pins |
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P41/XCIN |
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P40, P41 : CMOS input level |
(Connect a resonator.) |
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P42–P46 : CMOS compatible input level or TTL in- |
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P42/INT0 |
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put level |
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P47 : CMOS compatible input level or TTL input |
•Interrupt input pins |
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/OBF00 |
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P43/INT1 |
I/O port P4 |
level in the bus interface function |
•Bus interface function pins |
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<Output structure> |
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/OBF01 |
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P40, P41, P47 : CMOS 3-state output structure |
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P44/RxD |
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P42–P46 : CMOS 3-state output structure or N- |
|
||||
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channel open-drain output structure |
•Serial I/O1 function pins |
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P45/TxD |
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•Regardless of input or output port, P42 to P46 can |
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be input every pin level. |
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P46/SCLK1 |
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•When P42 and P43 are used as output port, the |
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/OBF10 |
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•Serial I/O1 function pins |
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function which makes P42 and P43 clear to “0” |
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P47/SRDY1 |
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when the host CPU reads the output data bus |
•Bus interface function pins |
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/S1 |
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buffer 0 can be added. |
|
||||
P50/A0 |
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•8-bit I/O port with the same function as port P0. |
•Bus interface function pins |
||||
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•CMOS compatible input level. |
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P51/INT20 |
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|||||
/S0 |
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•CMOS 3-state output structure. |
•Interrupt input pins |
||||
P52/INT30 |
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•P50 to P53 can be switched between CMOS com- |
|||||
/R |
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patible input level or TTL input level in the bus |
•Bus interface function pins |
||||
P53/INT40 |
I/O port P5 |
interface function. |
|
||||
/W |
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|||||
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P54/CNTR0 |
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•Timer X, timer Y function pins |
||||
P55/CNTR1 |
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P56/DA1 |
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•D-A converter output pin |
||||
/PWM01 |
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|||||
P57/DA2 |
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•PWM output pin |
||||
/PWM11 |
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||||
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•8-bit I/O port with the same function as port P0. |
|
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P60/AN0– |
I/O port P6 |
•CMOS compatible input level. |
•A-D converter output pin |
||||
P67/AN7 |
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•CMOS 3-state output structure. |
|
||||
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||
P70/SIN2 |
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•8-bit I/O port with the same function as port P0. |
|
||||
P71/SOUT2 |
|
P70–P75 : CMOS compatible input level or TTL in- |
•Serial I/O2 function pin |
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P72/SCLK2 |
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P76, P77 : CMOS compatible input level or |
•Serial I/O2 function pin |
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P73/SRDY2 |
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/INT21 |
I/O port P7 |
SMBUS input level in the I2C-BUS inter- |
•Interrupt input pin |
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P74/INT31 |
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face function, N-channel open-drain |
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output structure |
•Interrupt input pin |
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P76/SDA |
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P77/SCL |
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P80/DQ0– |
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I/O port P8 |
•CMOS 3-state output structure. |
•Bus interface function pin |
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P87/DQ7 |
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the bus interface function. |
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6
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Product name |
M3886 7 M 8 A- XXX HP |
Package type
HP : 80P6Q-A
GP : 80P6S-A
FS : 80D0
ROM number
Omitted in the one time PROM version shipped in blank, the EPROM version and the flash memory version.
A– : High-speed version
– is omitted in the One Time PROM version shipped in blank, the EPROM version and the flash memory version.
ROM/PROM size 1: 4096 bytes
2: 8192 bytes 3: 12288 bytes 4: 16384 bytes 5: 20480 bytes 6: 24576 bytes 7: 28672 bytes 8: 32768 bytes
The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used.
However, they can be programmed or erased in the EPROM version and the flash memory version, so that the users can use them.
Memory type
M : Mask ROM version
E: EPROM or One Time PROM version
F: Flash memory version
RAM size |
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0 : 192 bytes |
5 |
: 768 bytes |
1 : 256 bytes |
6 |
: 896 bytes |
2 : 384 bytes |
7 |
: 1024 bytes |
3 : 512 bytes |
8 |
: 1536 bytes |
4 : 640 bytes |
9 |
: 2048 bytes |
Fig. 5 Part numbering
7
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Mitsubishi plans to expand the 3886 group as follows.
Memory Type
Support for mask ROM, One Time PROM, EPROM and flash memory version.
Packages
80P6Q-A |
.................................. 0.5 mm-pitch plastic molded LQFP |
80P6S-A |
................................... 0.65mm pitch plastic molded QFP |
80D0 ....................... |
0.8 mm - pitch ceramic LCC (EPROM version) |
The pin number and the position of the function pin may change by the kind of package.
Memory Size
ROM size ........................................................... 32 K to 60 K bytes
RAM size .......................................................... 1024 to 2048 bytes
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Memory Expansion |
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ROM size (bytes) |
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: Mass production |
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ROM |
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external |
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60K |
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M38869FFA/MFA |
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48K |
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M38869MCA |
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32K |
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M38867E8A/M8A |
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M38869M8A |
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28K |
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24K |
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20K |
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16K |
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12K |
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8K |
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384 |
512 |
640 |
768 |
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896 |
1024 |
1152 |
1280 |
1408 |
1536 |
2048 |
3072 |
4032 |
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RAM size (bytes) |
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Fig. 6 Memory expansion plan |
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Currently products are listed below. |
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Table 3 Support products |
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As of Jan. 2000 |
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Product name |
(P) ROM size (bytes) |
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RAM size (bytes) |
Package |
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Remarks |
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ROM size for User in ( |
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M38867M8A-XXXHP |
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Mask ROM version |
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M38867E8A-XXXHP |
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1024 |
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80P6Q-A |
One Time PROM version |
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M38867E8AHP |
32768 (32638) |
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One Time PROM version (blank) |
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M38867E8AFS |
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80D0 |
EPROM version |
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M38869M8A-XXXHP |
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80P6Q-A |
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M38869M8A-XXXGP |
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80P6S-A |
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M38869MCA-XXXHP |
49152 (19022) |
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80P6Q-A |
Mask ROM version |
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M38869MCA-XXXGP |
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2048 |
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80P6S-A |
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M38869MFA-XXXHP |
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80P6Q-A |
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M38869MFA-XXXGP |
61440 (61310) |
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80P6S-A |
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M38869FFAHP |
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80P6Q-A |
Flash memory version |
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M38869FFAGP |
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80P6S-A |
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8
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The 3886 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit, the processor mode bits specifying the chip operation mode, etc.
The CPU mode register is allocated at address 003B16.
b7 |
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b0 |
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CPU mode register |
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(CPUM : address 003B16) |
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Processor mode bits |
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b1 b0 |
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0 |
0 |
: Single-chip mode |
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0 |
1 |
: Memory expansion mode (Note) |
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1 |
0 |
: Microprocessor mode (Note) |
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1 |
1 |
: Not available |
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Stack page selection bit |
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0 |
: 0 page |
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1 |
: 1 page |
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Reserved |
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(Do not write “0” to this bit when using |
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XCIN–XCOUT oscillation function.) |
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Port XC switch bit |
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0 : I/O port function (stop oscillating) |
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1 : XCIN–XCOUT oscillating function |
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Main clock (XIN–XOUT) stop bit |
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0 : Oscillating |
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1 : Stopped |
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Main clock division ratio selection bits |
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b7 b6 |
: φ = f(XIN)/2 (high-speed mode) |
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0 |
0 |
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0 |
1 |
: φ = f(XIN)/8 (middle-speed mode) |
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1 |
0 |
: φ = f(XCIN)/2 (low-speed mode) |
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1 |
1 |
: Not available |
Note: This mode is not available for M38869M8A/MCA/MFA and the flash memory version.
Fig. 7 Structure of CPU mode register
9
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The Special Function Register area in the zero page contains control registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Program/Erase of the reserved ROM area is possible in the EPROM version and the flash memory version
The interrupt vector area contains reset and interrupt vectors.
Access to this area with only 2 bytes is possible in the zero page addressing mode.
Access to this area with only 2 bytes is possible in the special page addressing mode.
RAM area
RAM size |
Address |
(bytes) |
XXXX16 |
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192 |
00FF16 |
256 |
013F16 |
384 |
01BF16 |
512 |
023F16 |
640 |
02BF16 |
768 |
033F16 |
896 |
03BF16 |
1024 |
043F16 |
1536 |
063F16 |
2048 |
083F16 |
ROM area
ROM size |
Address |
Address |
(bytes) |
YYYY16 |
ZZZZ16 |
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4096 |
F00016 |
F08016 |
8192 |
E00016 |
E08016 |
12288 |
D00016 |
D08016 |
16384 |
C00016 |
C08016 |
20480 |
B00016 |
B08016 |
24576 |
A00016 |
A08016 |
28672 |
900016 |
908016 |
32768 |
800016 |
808016 |
36864 |
700016 |
708016 |
40960 |
600016 |
608016 |
45056 |
500016 |
508016 |
49152 |
400016 |
408016 |
53248 |
300016 |
308016 |
57344 |
200016 |
208016 |
61440 |
100016 |
108016 |
000016 |
SFR area |
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Zero page |
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004016 |
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RAM |
010016 |
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XXXX16 |
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Not used |
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0FFE16 |
SFR area (Note 1) |
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0FFF16 |
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YYYY16 |
Reserved ROM area |
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(Note 2) (128 bytes) |
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ZZZZ16 |
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ROM
FF0016 |
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FFDC16 |
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Special page |
Interrupt vector area |
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FFFE16 |
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Reserved ROM area |
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FFFF16 |
(Note 2) |
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This area is SFR in M38869FFA.
This area is Reserved in M38869MFA/MCA/M8A. This area is not used in M38867M8A/E8A.
2: This area is usable in EPROM version and flash memory version.
Fig. 8 Memory map diagram
10
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)/Port P4 input register (P4I)
Port P8 direction register (P8D)/Port P7 input register (P7I)
I2C data shift register (S0)
I2C address register (S0D)
I2C status register (S1)
I2C control register (S1D)
I2C clock control register (S2)
I2C start/stop condition control register (S2D)
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Serial I/O2 control register (SIO2CON)
Watchdog timer control register (WDTCON)
Serial I/O2 register (SIO2)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
0FFE16
0FFF16
Prescaler 12 (PRE12)
Timer 1 (T1)
Timer 2 (T2)
Timer XY mode register (TM)
Prescaler X (PREX)
Timer X (TX)
Prescaler Y (PREY)
Timer Y (TY)
Data bas buffer register 0 (DBB0)
Data bas buffer status register 0 (DBBSTS0)
Data bas buffer control register (DBBCON)
Data bas buffer register 1 (DBB1)
Data bas buffer status register 1 (DBBSTS1)
Comparator data register (CMPD)
Port control register 1 (PCTL1)
Port control register 2 (PCTL2)
PWM0H register (PWM0H)
PWM0L register (PWM0L)
PWM1H register (PWM1H)
PWM1L register (PWM1L)
AD/DA control register (ADCON)
A-D conversion register 1 (AD1)
D-A1 conversion register (DA1)
D-A2 conversion register (DA2)
A-D conversion register 2 (AD2)
Interrupt source selection register (INTSEL)
Interrupt edge selection register (INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt request register 2 (IREQ2)
Interrupt control register 1 (ICON1)
Interrupt control register 2 (ICON2)
Flash memory control register (FCON)
Flash command register (FCMD)
(Note)
(Note)
Note: Flash memory version only
Fig. 9 Memory map of special function register (SFR)
11
|
MITSUBISHI MICROCOMPUTERS |
|
3886 Group |
|
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
|
|
I/O PORTS |
output latch is written to and the pin remains floating. |
The I/O ports have direction registers which determine the input/ |
When the P8 function select bit of the port control register 2 (ad- |
output direction of each individual pin. Each bit in a direction reg- |
dress 002F16) is set to “1”, read from address 001016 becomes |
ister corresponds to one pin, and each pin can be set to be input |
the port P4 input register, and read from address 001116 becomes |
port or output port. |
the port P7 input register. |
When “0” is written to the bit corresponding to a pin, that pin be- |
As the particular function, value of P42 to P46 pins and P70 to P75 |
comes an input pin. When “1” is written to that bit, that pin |
pins can be read regardless of setting direction registers, by read- |
becomes an output pin. |
ing the port P4 input register (address 001016) or the port P7 input |
If data is read from a pin which is set to output, the value of the |
register (address 001116) respectively. |
port output latch is read, not the value of the pin itself. Pins set to |
|
input are floating. If a pin set to input is written to, only the port |
|
Table 4 I/O port function (1)
|
Pin |
Name |
Input/Output |
I/O Structure |
Non-Port Function |
Related SFRs |
Ref.No. |
||
|
|
|
|
|
|
|
Address low-order byte |
CPU mode register |
|
P00/P3REF |
|
|
CMOS compatible |
output |
Port control register 1 |
(1) |
|||
|
|
Analog comparator |
Serial I/O2 control |
||||||
|
|
|
Port P0 |
|
input level |
|
|||
|
|
|
|
power source input pin |
register |
|
|||
|
|
|
|
|
CMOS 3-state output |
|
|
|
|
|
|
|
|
|
or N-channel open- |
|
|
|
|
P01–P07 |
|
|
Address low-order byte |
|
|
||||
|
|
drain output |
|
|
|||||
|
|
output |
CPU mode register |
|
|||||
|
|
|
|
|
|
|
(2) |
||
P10–P17 |
Port P1 |
|
|
|
Address high-order |
Port control register 1 |
|||
|
|
|
|
||||||
|
|
|
|
|
|||||
|
|
|
byte output |
|
|
||||
|
|
|
|
|
|
|
|
|
|
P20–P27 |
Port P2 |
|
|
|
Data bus I/O |
CPU mode register |
(3) |
||
P30/PWM00 |
|
|
|
|
Control signal I/O |
CPU mode register |
(4) |
||
|
|
|
|
PWM output |
|||||
|
|
|
|
Port control register 1 |
|||||
P31/PWM10 |
|
|
CMOS compatible |
Key-on wake up input |
(5) |
||||
|
|
AD/DA control register |
|||||||
|
|
|
Port P3 |
|
Comparator input |
|
|||
|
|
|
|
input level |
|
|
|||
|
|
|
|
Control signal I/O |
|
|
|||
|
|
|
|
|
CMOS 3-state output |
CPU mode register |
|
||
P32–P37 |
|
|
|
|
Key-on wake up input |
(6) |
|||
|
|
|
|
Port control register 1 |
|||||
|
|
|
|
|
|
|
Comparator input |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
P40/XCOUT |
|
|
|
|
Sub-clock generating |
CPU mode register |
(7) |
||
P41/XCIN |
|
|
|
|
circuit |
(8) |
|||
|
|
|
|
|
|||||
P42/INT0/ |
|
|
|
|
External interrupt input |
Interrupt edge selection |
(9) |
||
OBF00 |
|
Input/output, |
|
|
|||||
|
|
|
Bus interface function |
register |
|||||
P43/INT1/ |
|
individual bits |
|
|
(10) |
||||
|
|
|
I/O |
Port control register 2 |
|||||
OBF01 |
|
|
|
|
|
||||
|
|
CMOS compatible |
|
|
|
||||
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
Serial I/O1 control |
|
||
|
|
|
|
|
input level or TTL |
Serial I/O1 function in- |
(11) |
||
P44/RXD |
|
|
register |
||||||
|
|
input level |
put |
||||||
|
|
|
|
|
Port control register 2 |
|
|||
|
|
|
|
|
CMOS 3-state output |
|
|
||
|
|
|
|
|
|
|
|
||
|
|
|
|
|
or N-channel open- |
|
Serial I/O1 control |
|
|
P45/TXD |
|
|
drain output |
Serial I/O1 function out- |
register |
(12) |
|||
Port P4 |
|
|
|
put |
UART control register |
||||
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
Port control register 2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Serial I/O1 control |
|
P46/SCLK1 |
|
|
|
|
Serial I/O1 function I/O |
register |
(13) |
||
|
|
|
|
Bus interface function |
Data bus buffer control |
||||
/OBF10 |
|
|
|
|
|||||
|
|
|
|
output |
register |
|
|||
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
Port control register 2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CMOS compatible |
|
|
|
|
|
|
|
|
|
input level |
Serial I/O1 function out- |
Serial I/O1 control |
|
|
|
|
|
|
|
CMOS 3-state output |
|
|||
P47/SRDY1 |
|
|
|
||||||
|
|
(when selecting bus |
put |
register |
(14) |
||||
/S1 |
|
|
interface function) |
Bus interface function |
Data bus buffer control |
||||
|
|
|
|||||||
|
|
|
|
|
CMOS compatible |
input |
register |
|
|
|
|
|
|
|
input level or TTL |
|
|
|
|
|
|
|
|
|
input level |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
12
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 5 I/O port function (2)
|
Pin |
Name |
Input/Output |
I/O Format |
|
|
Non-Port Function |
Related SFRs |
Ref.No. |
|
P50/A0 |
|
|
CMOS compatible |
|
Bus interface function |
Data bus buffer control |
(15) |
|||
|
|
|
input |
register |
||||||
|
|
|
|
|
input level |
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
P51/INT20 |
|
|
CMOS 3-state output |
|
|
|
||||
/S0 |
|
|
(when selecting bus |
External interrupt input |
Interrupt edge selection |
|
||||
P52/INT30 |
|
|
interface function) |
|
register |
(16) |
||||
|
|
|
Bus interface function |
|||||||
|
|
CMOS compatible |
|
Data bus buffer control |
||||||
/R |
|
|
|
input |
|
|||||
Port P5 |
|
input level or TTL |
|
register |
|
|||||
P53/INT40 |
|
|
|
|
||||||
|
input level |
|
|
|
|
|
||||
|
|
|
|
|
|
|
||||
/W |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
P54/CNTR0 |
|
|
|
|
|
Timer X, timer Y func- |
Timer XY mode register |
(17) |
||
P55/CNTR1 |
|
|
|
|
|
tion I/O |
||||
|
|
|
|
|
|
|
||||
P56/DA1/ |
|
|
CMOS compatible |
|
|
|
||||
PWM01 |
|
|
input level |
|
|
D-A converter output |
AD/DA control register |
(18) |
||
P57/DA2/ |
|
|
CMOS 3-state output |
PWM output |
UART control register |
(19) |
||||
PWM11 |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
P60/AN0– |
Port P6 |
|
|
|
|
A-D converter input |
AD/DA control register |
(20) |
||
P67/AN7 |
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|||
P70/SIN2 |
|
|
|
|
|
|
Serial I/O2 control |
(21) |
||
P71/SOUT2 |
|
Input/output, |
|
|
|
Serial I/O2 function I/O |
register |
(22) |
||
|
|
|
|
|
|
|
|
Port control register 2 |
(23) |
|
P72/SCLK2 |
|
individual bits |
CMOS compatible |
|
||||||
|
|
|
|
|||||||
|
|
|
|
|
input level or TTL |
|
Serial I/O2 function out- |
Serial I/O2 control |
|
|
P73/SRDY2/ |
|
|
input level |
|
|
put |
|
|||
|
|
|
|
register |
(24) |
|||||
INT21 |
|
|
N-channel open-drain |
Bus interface function |
||||||
|
|
Port control register 2 |
|
|||||||
|
|
|
|
|
output |
|
|
input |
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
P74/INT31 |
|
|
|
|
|
|
Interrupt edge selection |
|
||
Port P7 |
|
|
|
|
External interrupt input |
register |
(25) |
|||
P75/INT41 |
|
|
|
|
||||||
|
|
|
|
|
|
Port control register 2 |
|
|||
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
CMOS compatible |
|
|
|
||
|
|
|
|
|
input level |
|
|
|
|
|
|
|
|
|
|
N-channel open-drain |
|
|
|
||
P76/SDA |
|
|
output |
2 |
|
I2C-BUS interface func- |
|
(26) |
||
|
|
(when selecting I |
C- |
I2C control register |
||||||
P77/SCL |
|
|
|
tion I/O |
(27) |
|||||
|
|
BUS interface |
|
|
|
|||||
|
|
|
|
|
function) |
|
|
|
|
|
|
|
|
|
|
CMOS compatible |
|
|
|
||
|
|
|
|
|
input level or SMBUS |
|
|
|
||
|
|
|
|
|
input level |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
CMOS compatible |
|
|
|
||
|
|
|
|
|
input level |
|
|
|
|
|
|
|
|
|
|
CMOS 3-state output |
|
|
|
||
P80/DQ0– |
Port P8 |
|
(when selecting bus |
Bus interface function |
Data bus buffer control |
(28) |
||||
P87/DQ7 |
|
interface function) |
|
I/O |
register |
|||||
|
|
|
|
|
CMOS compatible |
|
|
|
||
|
|
|
|
|
input level or TTL |
|
|
|
|
|
|
|
|
|
|
input level |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Notes1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
13
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(1) Port P00
P00–P03 output structure selection bit
|
Direction |
|
register |
Data bus |
Port latch |
Comparator reference power source input |
|
|
Comparator reference input |
|
pin select bit |
(3) Port P2 |
|
|
Direction |
|
register |
Data bus |
Port latch |
(2) Ports P01–P07,P1
P00–P03,
P04–P07,
P10–P13,
P14–P17 output structure selection bits
|
Direction |
|
register |
Data bus |
Port latch |
(4) Port P30 |
P30–P33 pull-up control bit |
||
PWM0 output pin selection bit |
|||
|
|||
|
PWM0 enable bit |
|
|
|
Direction |
|
|
|
register |
|
|
Data bus |
Port latch |
|
|
|
PWM00 output |
Comparator |
|
|
|
Key-on wake-up input |
(5) Port P31 |
P30–P33 pull-up control bit |
||
PWM1 output pin selection bit |
|||
|
|||
|
PWM1 enable bit |
|
|
|
Direction |
|
|
|
register |
|
|
Data bus |
Port latch |
|
PWM10 output |
|
Comparator |
|
|
Key-on wake-up input |
(6) Ports P32–P37 |
|
|
|
P30–P33, |
pull-up control bit |
|
P34–P37 |
|
|
Direction |
|
|
register |
|
Data bus |
Port latch |
|
Comparator Key-on wake-up input
(7) Port P40 |
|
Port XC switch bit |
|
|
Direction |
|
register |
Data bus |
Port latch |
(8) Port P41 |
|
Port XC switch bit |
|
|
Direction |
|
register |
Data bus |
Port latch |
Oscillator |
|
|||||
Port P41 |
|
|
|
|
Sub-clock generating circuit input |
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Port XC switch bit |
|
Fig. 10 Port block diagram (1)
14
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(9) Port P42 |
|
|
|
(10) Port P43 |
|
|
P4 output structure selection bit |
|
|
|
P4 output structure selection bit |
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
OBF00 output enable bit
OBF01 output enable bit
Direction |
Direction |
|
register |
||
register |
||
|
Data bus |
Port latch |
Data bus |
Port latch |
|
|
|
|||
|
1 |
|
1 |
|
|
|
|
||
|
2 |
|
2 |
|
|
|
|
||
|
OBF00 output |
|
OBF01 output |
|
|
INT0 interrupt input |
|
INT1 interrupt input |
|
|
|
|
||
(11) Port P44 |
(12) Port P45 |
|||
|
P4 output structure selection bit |
P45/TXD P-channel output disable bit |
||
Serial I/O1 enable bit |
||||
Serial I/O1 enable bit |
||||
Receive enable bit |
||||
|
|
|
Transmit enable bit |
|
Direction |
Direction |
|
register |
|
|
register |
|
|
Data bus |
Port latch |
Data bus |
Port latch |
|
|
|
1 |
|
1 |
2 |
|
|
|
|
2 |
Serial I/O1 output |
|
|
|
|
Serial I/O1 input |
|
(13) Port P46
Serial I/O1 P4 output structure selection bit synchronous clock selection bit
Serial I/O1 enable bit
Serial I/O1 mode selection bit
Serial I/O1 enable bit
OBF10 output enable bit
|
Direction |
|
register |
Data bus |
Port latch |
|
1 |
|
2 |
Serial I/O1 clock output
OBF10 output
Serial I/O1 external clock input
(14) Port P47
Serial I/O1 mode selection bit
Serial I/O1 enable bit
SRDY1 output enable bit
Data bus buffer function selection bit
|
Direction |
|
register |
Data bus |
Port latch |
Serial I/O1 ready output |
3 |
S1 input |
Data bus buffer function |
|
selection bit |
(15) Port P50 |
|
|
|
(16) Ports P51,P52,P53 |
|
|
Data bus buffer enable bit |
|
|
|
Data bus buffer enable bit |
|
|
|
|
|
|
Direction |
Direction |
register |
register |
Data bus |
Port latch |
Data bus |
Port latch |
|
A0 input |
3 |
INT20, INT30, INT40 interrupt input |
|
|
Data bus buffer |
3 |
|
enable bit |
||
S0,R,W input |
||
|
||
|
Data bus buffer |
|
|
enable bit |
1. The input level can be switched between CMOS compatible input level and TTL level by the P4 input level selection bit of the port control register 2 (address 002F16).
2. The input level can be switched between CMOS compatible input level and TTL level by the P4 input level selection bit of the port control register 2 (address 002F16).
The port P8 and port P4 input register can be switched by the P8 function selection bit of the port control register 2 (address 002F16).3. The input level can be switched between CMOS compatible input level and TTL level by the input level selection bit of the data bus buffer
control register (address 002A16).
Fig. 11 Port block diagram (2)
15
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(17) Ports P54,P55 |
|
|
Direction |
|
register |
Data bus |
Port latch |
Pulse output mode
Timer output
CNTR0,CNTR1 interrupt input
(19) Port P57
PWM1 output pin selection bit
PWM1 enable bit
|
Direction |
|
register |
Data bus |
Port latch |
|
PWM11 output |
D-A converter output
D-A2 output enable bit
(18) Port P56
PWM0 output pin selection bit
PWM0 enable bit
|
Direction |
|
register |
Data bus |
Port latch |
|
PWM01 output |
D-A converter output
D-A1 output enable bit
(20) Port P6
Direction register
Data bus Port latch
A-D converter input
Analog input pin selection bit
(21) Port P70
Direction register
Data bus |
Port latch |
4
5
Serial I/O2 input
(23) Port P72
Serial I/O2 synchronization clock selection bit Serial I/O2 port selection bit
|
Direction |
|
register |
Data bus |
Port latch |
|
4 |
|
5 |
|
Serial I/O2 clock output |
|
Serial I/O2 |
|
external clock input |
(22) Port P71 |
|
Serial IO/2 transmit completion signal |
|
Serial I/O2 port selection bit |
|
|
Direction |
|
register |
Data bus |
Port latch |
|
4 |
|
5 |
|
Serial I/O2 output |
(24) Port P73 |
|
|
SRDY2 output enable bit |
|
Direction |
|
register |
Data bus |
Port latch |
|
4 |
|
5 |
|
Serial I/O2 ready output |
|
INT21 interrupt input |
4. The input level can be switched between CMOS compatible input level and TTL level by the P7 input level selection bit of the port control register 2 (address 002F16).
5. The input level can be switched between CMOS compatible input level and TTL level by the P7 input level selection bit of the port control register 2 (address 002F16).
The port P8 direction register and port P7 input register can be switched by the P8 function selection bit of the port control register 2 (address 002F16).
Fig. 12 Port block diagram (3)
16
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(25) Ports P74,P75
Direction register
Data bus |
Port latch |
4
5
INT31,INT41 interrupt input
(27) Port P77
I2C-BUS interface enable bit
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Direction |
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register |
Data bus |
Port latch |
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SCL output |
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6 |
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SCL input |
(26) Port P76
I2C-BUS interface enable bit
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Direction |
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register |
Data bus |
Port latch |
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SDA output |
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6 |
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SDA input |
(28) Port P8 |
S0 |
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S1 |
R |
Data bus buffer enable bit |
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Direction |
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register |
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Data bus |
Port latch |
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Output buffer 0
Status register 0
Output buffer 1
Status register 1
3
Input buffer 0
3
Input buffer 1
6. The input level can be switched between CMOS compatible input level and SMBUS level by the I2C-BUS interface pin input selection bit of the I2C control register (address 001516).
Fig. 13 Port block diagram (4)
17
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7 |
b0 |
Port control register 1 (PCTL1: address 002E16)
P00–P03 output structure selection bit
0:CMOS
1:N-channel open-drain
P04–P07 output structure selection bit
0:CMOS
1:N-channel open-drain
P10–P13 output structure selection bit
0:CMOS
1:N-channel open-drain
P14–P17 output structure selection bit
0:CMOS
1:N-channel open-drain P30–P33 pull-up control bit
0:No pull-up
1:Pull-up
P34–P37 pull-up control bit
0:No pull-up
1:Pull-up PWM0 enable bit
0:PWM0 output disabled
1:PWM0 output enabled PWM1 enable bit
0:PWM1 output disabled
1:PWM1 output enabled
b7 |
b0 |
Port control register 2 (PCTL2: address 002F16)
P4 input level selection bit (P42–P46)
0:CMOS level input
1:TTL level input
P7 input level selection bit (P70–P75)
0:CMOS level input
1:TTL level input
P4 output structure selection bit (P42, P43, P44, P46)
0:CMOS
1:N-channel open-drain P8 function selection bit
0:Port P8/Port P8 direction register
1:Port P4 input register/Port P7 input register INT2, INT3, INT4 interrupt switch bit
0:INT20, INT30, INT40 interrupt
1:INT21, INT31, INT41 interrupt Timer Y count source selection bit
0:f(XIN)/16 (f(XCIN)/16 in low-speed mode)
1:f(XCIN)
Oscillation stabilizing time set after STP instruction released bit
0:Automatic set “0116” to timer 1 and “FF16” to prescaler 12
1:No automatic set
Port output P42/P43 clear function selection bit
0:Only software clear
1:Software clear and output data bus buffer 0 reading (system bus side)
Fig. 14 Structure of port I/O related register
18
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupts occur by 16 sources among 21 sources: nine external, eleven internal, and one software.
Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software interrupt set by the BRK instruction. An interrupt occurs if the corresponding interrupt request and enable bits are “1” and the interrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK instruction interrupt.
When several interrupts occur at the same time, the interrupts are received according to priority.
Any of the following interrupt sources can be selected by the interrupt source selection register (address 003916).
1.INT0 or Input buffer full
2.INT1 or Output buffer empty
3.Serial I/O1 transmission or SCLSDA
4.CNTR0 or SCLSDA
5.Serial I/O2 or I2C
6.INT2 or I2C
7.CNTR1 or Key-on wake-up
8.A-D conversion or Key-on wake-up
The occurrence sources of the external interrupt INT2, INT3, and
INT4 can be selected from either input from INT20, INT30, INT40 pin, or input from INT21, INT31, INT41 pin by the INT2, INT3, INT4 interrupt switch bit (bit 4 of address 002F16).
By acceptance of an interrupt, the following operations are automatically performed:
1.The contents of the program counter and the processor status register are automatically pushed onto the stack.
2.The interrupt disable flag is set and the corresponding interrupt request bit is cleared.
3.The interrupt jump destination address is read from the vector table into the program counter.
When setting of the following register or bit is changed, the interrupt request bit may be set to “1.”
•Interrupt edge selection register (address 003A16)
•Interrupt source selection register (address 003916)
•INT2, INT3, INT4 interrupt switch bit of Port control register 2 (bit
4 of address 002F16)
Accept the interrupt after clearing the interrupt request bit to “0” after interrupt is disabled and the above register or bit is set.
19
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Table 6 Interrupt vector addresses and priority
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Interrupt Source |
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Priority |
Vector Addresses (Note 1) |
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Interrupt Request |
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Remarks |
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High |
Low |
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Generating Conditions |
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Reset (Note 2) |
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1 |
FFFD16 |
FFFC16 |
At reset |
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Non-maskable |
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INT0 |
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At detection of either rising or |
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External interrupt |
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2 |
FFFB16 |
FFFA16 |
falling edge of INT0 input |
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Input buffer full |
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At input data bus buffer writing |
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(IBF) |
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INT1 |
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At detection of either rising or |
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External interrupt |
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falling edge of INT1 input |
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3 |
FFF916 |
FFF816 |
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Output buffer |
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At output data bus buffer read- |
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empty (OBE) |
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Serial I/O1 |
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4 |
FFF716 |
FFF616 |
At completion of serial I/O1 data |
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Valid when serial I/O1 is selected |
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reception |
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reception |
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Serial I/O1 |
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At completion of serial I/O1 |
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transfer shift or when transmis- |
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Valid when serial I/O1 is selected |
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transmission |
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5 |
FFF516 |
FFF416 |
sion buffer is empty |
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SCL, SDA |
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At detection of either rising or |
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External interrupt |
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falling edge of SCL or SDA |
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Timer X |
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6 |
FFF316 |
FFF216 |
At timer X underflow |
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Timer Y |
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7 |
FFF116 |
FFF016 |
At timer Y underflow |
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Timer 1 |
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8 |
FFEF16 |
FFEE16 |
At timer 1 underflow |
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STP release timer underflow |
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Timer 2 |
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9 |
FFED16 |
FFEC16 |
At timer 2 underflow |
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CNTR0 |
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At detection of either rising or |
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External interrupt |
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falling edge of CNTR0 input |
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(active edge selectable) |
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10 |
FFEB16 |
FFEA16 |
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SCL, SDA |
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At detection of either rising or |
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External interrupt |
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falling edge of SCL or SDA |
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(active edge selectable) |
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CNTR1 |
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At detection of either rising or |
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External interrupt |
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falling edge of CNTR1 input |
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11 |
FFE916 |
FFE816 |
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Key-on wake-up |
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At falling of port P3 (at input) in- |
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External interrupt (falling valid) |
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put logical level AND |
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Serial I/O2 |
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At completion of serial I/O2 data |
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Valid when serial I/O2 is selected |
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12 |
FFE716 |
FFE616 |
transfer |
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I2C |
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At completion of data transfer |
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INT2 |
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At detection of either rising or |
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External interrupt |
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13 |
FFE516 |
FFE416 |
falling edge of INT2 input |
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(active edge selectable) |
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I2C |
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At completion of data transfer |
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INT3 |
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14 |
FFE316 |
FFE216 |
At detection of either rising or |
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External interrupt |
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falling edge of INT3 input |
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(active edge selectable) |
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INT4 |
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15 |
FFE116 |
FFE016 |
At detection of either rising or |
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External interrupt |
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falling edge of INT4 input |
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(active edge selectable) |
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A-D converter |
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At completion of A-D conversion |
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16 |
FFDF16 |
FFDE16 |
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Key-on wake-up |
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At falling of port P3 (at input) in- |
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External interrupt (falling valid) |
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put logical level AND |
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BRK instruction |
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17 |
FFDD16 |
FFDC16 |
At BRK instruction execution |
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Non-maskable software interrupt |
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
20
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction |
Interrupt request |
Reset |
|
Fig. 15 Interrupt control
b7
b7
b7
b0 Interrupt edge selection register (INTEDGE : address 003A16)
INT0 active edge selection bit INT1 active edge selection bit Not used (returns “0” when read) INT2 active edge selection bit INT3 active edge selection bit
INT4 active edge selection bit
Not used (returns “0” when read) 0 : Falling edge active 1 : Rising edge active
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b0 |
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Interrupt request register 1 |
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b7 |
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b0 |
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Interrupt request register 2 |
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(IREQ1 : address 003C16) |
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(IREQ2 : address 003D16) |
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INT0/input buffer full interrupt request |
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CNTR0/SCL, SDA interrupt request bit |
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bit |
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CNTR1/key-on wake-up interrupt |
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INT1/output buffer empty interrupt |
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request bit |
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request bit |
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Serial I/O2/I2C interrupt request bit |
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Serial I/O1 receive interrupt request bit |
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INT2/I2C interrupt request bit |
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Serial I/O1 transmit/SCL, SDA interrupt |
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INT3 interrupt request bit |
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request bit |
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INT4 interrupt request bit |
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Timer X interrupt request bit |
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AD converter/key-on wake-up interrupt |
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Timer Y interrupt request bit |
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request bit |
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Timer 1 interrupt request bit |
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Not used (returns “0” when read) |
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Timer 2 interrupt request bit |
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0 : No interrupt request issued |
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1 : Interrupt request issued |
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b0 |
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b7 |
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Interrupt control register 1 |
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(ICON1 : address 003E16) |
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INT0/input buffer full interrupt enable bit |
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INT1/output buffer empty interrupt |
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enable bit |
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Serial I/O1 receive interrupt enable bit |
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Serial I/O1 transmit/SCL, SDA interrupt |
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enable bit |
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Timer X interrupt enable bit |
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Timer Y interrupt enable bit |
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Timer 1 interrupt enable bit |
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Timer 2 interrupt enable bit |
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b0 Interrupt control register 2 (ICON2 : address 003F16)
CNTR0/SCL, SDA interrupt enable bit CNTR1/key-on wake-up interrupt enable bit
Serial I/O2/I2C interrupt enable bit
INT2/I2C interrupt enable bit INT3 interrupt enable bit INT4 interrupt enable bit
AD converter/key-on wake-up interrupt enable bit
Not used (returns “0” when read) (Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
Fig. 16 Structure of interrupt-related registers (1)
21
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
|
b7 |
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b0 |
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Interrupt source selection register |
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(INTSEL: address 003916) |
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INT0/input buffer full interrupt source selection bit |
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0 |
: INT0 interrupt |
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1 |
: Input buffer full interrupt |
INT1/output buffer empty interrupt source selection bit 0 : INT1 interrupt
1 : Output buffer empty interrupt
Serial I/O1 transmit/SCL,SDA interrupt source selection bit 0 : Serial I/O1 transmit interrupt
1 : SCL,SDA interrupt
(Do not write “1” to these bits simultaneously.)
CNTR0/SCL,SDA interrupt source selection bit 0 : CNTR0 interrupt
1 : SCL,SDA interrupt
Serial I/O2/I2C interrupt source selection bit 0 : Serial I/O2 interrupt
1 : I2C interrupt
(Do not write “1” to these bits simultaneously.)
INT2/I2C interrupt source selection bit 0 : INT2 interrupt
1 : I2C interrupt
CNTR1/key-on wake-up interrupt source selection bit 0 : CNTR1 interrupt
1 : Key-on wake-up interrupt
(Do not write “1” to these bits simultaneously.)
AD converter/key-on wake-up interrupt source selection bit 0 : A-D converter interrupt
1 : Key-on wake-up interrupt
Fig. 17 Structure of interrupt-related registers (2)
22
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
A Key input interrupt request is generated by applying “L” level to any pin of port P3 that have been set to input mode. In other words, it is generated when AND of input level goes from “1” to
“0”. An example of using a key input interrupt is shown in Figure 18, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports
P30–P33.
Port PXx |
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“L” level output |
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Port control register 1 |
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Bit 5 = “1” |
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Port P37 |
Key input interrupt request |
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direction register = “1” |
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Port P37 |
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latch |
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P37 output |
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Port P36 |
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direction register = “1” |
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Port P36 |
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latch |
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P36 output |
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Port P35 |
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direction register = “1” |
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Port P35 |
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latch |
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P35 output |
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Port P34 |
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direction register = “1” |
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Port P34 |
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latch |
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P34 output |
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Port control register 1 |
Port P33 |
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Bit 4 = “1” |
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direction register = “0” |
Port P3 |
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Port P33 |
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Input reading circuit |
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P33 input |
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latch |
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Comparator circuit |
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Port P32 |
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direction register = “0” |
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Port P32 |
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P32 input |
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latch |
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Port P31 |
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direction register = “0” |
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Port P31 |
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P31 input |
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latch |
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Port P30 |
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direction register = “0” |
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Port P30 |
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P30 input |
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latch |
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P-channel transistor for pull-upCMOS output buffer
Fig. 18 Connection example when using key input interrupt and port P3 block diagram
23
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
The 3886 group has four timers: timer X, timer Y, timer 1, and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. All timers are count down. When the timer reaches “0016”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”.
b7 |
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b0 |
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Timer XY mode register |
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(TM : address 002316) |
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Timer X operating mode bit |
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b1b0 |
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0 0: Timer mode |
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0 1: Pulse output mode |
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1 0: Event counter mode |
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1 1: Pulse width measurement mode |
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CNTR0 active edge selection bit |
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0: Interrupt at falling edge |
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Count at rising edge in event |
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counter mode |
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1: Interrupt at rising edge |
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Count at falling edge in event |
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counter mode |
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Timer X count stop bit |
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0: Count start |
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1: Count stop |
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Timer Y operating mode bit |
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b5b4 |
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0 0: Timer mode |
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0 1: Pulse output mode |
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1 0: Event counter mode |
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1 1: Pulse width measurement mode |
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CNTR1 active edge selection bit |
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0: Interrupt at falling edge |
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Count at rising edge in event |
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counter mode |
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1: Interrupt at rising edge |
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Count at falling edge in event |
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counter mode |
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Timer Y count stop bit |
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0: Count start |
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1: Count stop |
Fig. 19 Structure of timer XY mode register
The count source of prescaler 12 is the oscillation frequency divided by 16. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit.
Timer X and Timer Y can each select in one of four operating modes by setting the timer XY mode register.
The timer counts f(XIN)/16.
Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of the timer reach “0016”, the signal output from the CNTR0 (or CNTR1) pin is inverted. If the CNTR0 (or CNTR1) active edge selection bit is “0”, output begins at “ H”.
If it is “1”, output starts at “L”. When using a timer in this mode, set the corresponding port P54 ( or port P55) direction register to output mode.
Operation in event counter mode is the same as in timer mode, except that the timer counts signals input through the CNTR0 or
CNTR1 pin.
When the CNTR0 (or CNTR1) active edge selection bit is “0”, the rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”, the falling edge of the CNTR0 (or CNTR1) pin is counted.
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer counts f(XIN)/16 while the CNTR0 (or CNTR1) pin is at “H”. If the
CNTR0 (or CNTR1) active edge selection bit is “1”, the timer counts while the CNTR0 (or CNTR1) pin is at “L”.
The count can be stopped by setting “1” to the timer X (or timer Y) count stop bit in any mode. The corresponding interrupt request bit is set each time a timer overflows.
The count source for timer Y in the timer mode or the pulse output mode can be selected from either f(XIN)/16 or f(XCIN) by the timer
Y count source selection bit of the port control register 2 (bit 5 of address 002F16).
24
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
|
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Data bus |
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Oscillator |
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Divider |
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f(XIN) |
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1/16 |
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Prescaler X latch (8) |
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(f(XCIN) in low-speed mode) |
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Pulse width |
Timer mode |
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measurement |
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mode |
Pulse output mode |
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Prescaler X (8) |
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CNTR0 active |
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Event |
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edge selection |
Timer X count stop bit |
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P54/CNTR0 |
counter |
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bit |
“0” |
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mode |
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“1” |
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CNTR0 active |
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edge selection “1” |
Q |
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bit |
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Toggle flip-flop T |
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“0” |
Q |
R |
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Port P54 |
Port P54 |
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latch |
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direction register |
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Pulse output mode |
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Data bus |
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Timer X latch (8) |
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To timer X interrupt |
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Timer X (8) |
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request bit |
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To CNTR0 interrupt request bit
Timer X latch write pulse
Pulse output mode
Oscillator |
Divider |
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f(XIN) |
1/16 |
Timer Y count source |
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selection bit |
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(f(XCIN) in low-speed mode) |
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“0” |
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Prescaler Y latch (8) |
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Oscillator |
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“1” |
Pulse width |
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measure- |
Timer mode |
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f(XCIN) |
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ment mode |
Pulse output mode |
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Prescaler Y (8) |
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CNTR1 active |
Event |
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P55/CNTR1 |
edge selection |
Timer Y count stop bit |
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bit |
“0” |
counter |
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mode |
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“1” |
CNTR1 active |
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edge selection “1” |
Q |
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bit |
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Toggle flip-flop T |
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“0” |
Q |
R |
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Port P55 |
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Port P55 |
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latch |
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direction register |
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Timer Y latch |
(8) |
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To timer Y interrupt |
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Timer Y (8) |
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request bit |
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To CNTR1 interrupt |
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request bit |
Timer Y latch write pulse
Pulse output mode
Pulse output mode
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Data bus |
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Prescaler 12 latch (8) |
Timer 1 latch (8) |
Oscillator |
Divider |
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f(XIN) |
1/16 |
Prescaler 12 (8) |
Timer 1 (8) |
(f(XCIN) in low-speed mode)
Timer 2 latch (8)
Timer 2 (8)
To timer 2 interrupt request bit
To timer 1 interrupt request bit
Fig. 20 Block diagram of timer X, timer Y, timer 1, and timer 2
25
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O1 can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation.
Clock synchronous serial I/O1 mode can be selected by setting the serial I/O1 mode selection bit of the serial I/O1 control register (bit 6 of address 001A16) to “1”.
For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB.
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Data bus |
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Address 001816 |
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Serial I/O1 control register |
Address 001A16 |
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Receive buffer register |
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Receive buffer full flag (RBF) |
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Receive interrupt request (RI) |
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P44/RXD |
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Receive shift register |
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Shift clock |
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Clock control circuit |
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P46/SCLK1/OBF10
BRG count source selection bit
f(XIN)
(f(XCIN) in low-speed mode)
1/4
Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1)
Baud rate generator |
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1/4 |
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Address 001C16 |
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P47/SRDY1/S1 |
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F/F |
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Falling-edge detector |
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P45/TXD |
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Shift clock |
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Transmit shift register |
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Clock control circuit
Transmit shift completion flag (TSC) Transmit interrupt source selection bit
Transmit interrupt request (TI)
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Transmit buffer register |
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Transmit buffer empty flag (TBE) |
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Address 001816 |
Serial I/O1 status register |
Address 001916 |
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Data bus |
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Fig. 21 Block diagram of clock synchronous serial I/O1
Transfer shift clock
(1/2 to 1/2048 of the internal clock, or an external clock)
Serial output TxD
Serial input RxD
Receive enable signal SRDY1
Write pulse to receive/transmit buffer register (address 001816)
D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
TBE = 0 |
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RBF = 1 |
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TSC = 1 |
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TBE = 1 |
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TSC = 0 |
Overrun error (OE) |
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detection |
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
2:If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin.
3:The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Fig. 22 Operation of clock synchronous serial I/O1 function
26
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to “0”.
Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register.
The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received.
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Data bus |
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Address 001816 |
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Serial I/O1 control register Address 001A16 |
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OE |
Receive buffer register |
Receive buffer full flag (RBF) |
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Character length selection bit |
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Receive interrupt request (RI) |
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P44/RXD |
ST detector |
7 bits |
Receive shift register |
1/16 |
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8 bits |
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PE FE |
SP detector |
UART control register |
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Clock control circuit |
Address 001B16 |
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Serial I/O1 synchronous clock selection bit |
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P46/SCLK1/OBF10 |
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f(XIN) |
BRG count source selection bit |
Frequency division ratio 1/(n+1) |
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Baud rate generator |
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(f(XCIN) in low-speed mode) |
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Address 001C16 |
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1/4 |
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ST/SP/PA generator |
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Transmit shift completion flag (TSC) |
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1/16 |
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Transmit interrupt source selection bit |
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P45/TXD |
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Transmit shift register |
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Transmit interrupt request (TI) |
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Character length selection bit |
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Transmit buffer empty flag (TBE) |
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Transmit buffer register |
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Serial I/O1 status register |
Address 001916 |
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Address 001816 |
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Data bus |
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Fig. 23 Block diagram of UART serial I/O1
27
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Transmit or receive clock |
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Transmit buffer write |
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signal |
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TBE=0 |
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TBE=0 |
TSC=0 |
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TBE=1 |
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Serial output TXD |
ST |
D0 |
D1 |
1 start bit 7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
Receive buffer read signal
Serial input RXD |
ST |
D0 |
D1 |
TBE=1 |
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TSC=1 |
SP |
ST |
D0 |
D1 |
SP |
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Generated at 2nd |
bit in 2-stop-bit mode |
RBF=1 |
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RBF=0 |
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RBF=1 |
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SP |
ST |
D0 |
D1 |
SP |
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Notes 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2:As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register.
3:The receive interrupt (RI) is set when the RBF flag becomes “1.”
4:After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Fig. 24 Operation of UART serial I/O1 function
[Serial I/O1 Control Register (SIO1CON)] 001A16
The serial I/O1 control register consists of eight control bits for the serial I/O function.
[UART Control Register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P45/TXD pin.
[Serial I/O1 Status Register (SIO1STS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read.
If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O1 status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O control register) also clears all the status flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O1 control register has been set to “1”, the transmit shift completion flag (bit
2) and the transmit buffer empty flag (bit 0) become “1”.
[Transmit Buffer Register/Receive Buffer
Register (TB/RB)] 001816
The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Baud Rate Generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.
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MITSUBISHI MICROCOMPUTERS |
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3886 Group |
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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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b7 |
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b0 |
Serial I/O1 status register |
b7 |
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b0 |
Serial I/O1 control register |
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(SIO1STS : address 001916) |
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(SIO1CON : address 001A16) |
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BRG count source selection bit (CSS) |
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Transmit buffer empty flag (TBE) |
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0: f(XIN) (f(XCIN) in low-speed mode) |
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0: Buffer full |
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1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) |
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1: Buffer empty |
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Receive buffer full flag (RBF) |
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Serial I/O1 synchronous clock selection bit (SCS) |
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0: BRG output divided by 4 when clock synchronous |
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0: Buffer empty |
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serial I/O is selected, BRG output divided by 16 |
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1: Buffer full |
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when UART is selected. |
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Transmit shift completion flag (TSC) |
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1: External clock input when clock synchronous serial |
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I/O is selected, external clock input divided by 16 |
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0: Transmit shift in progress |
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when UART is selected. |
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1: Transmit shift completed |
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output enable bit (SRDY) |
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Overrun error flag (OE) |
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SRDY1 |
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0: P47 pin operates as ordinary I/O pin |
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0: No error |
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1: P47 pin operates as SRDY1 output pin |
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1: Overrun error |
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Parity error flag (PE) |
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Transmit interrupt source selection bit (TIC) |
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0: Interrupt when transmit buffer has emptied |
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0: No error |
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1: Interrupt when transmit shift operation is completed |
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1: Parity error |
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Framing error flag (FE) |
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Transmit enable bit (TE) |
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0: Transmit disabled |
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0: No error |
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1: Transmit enabled |
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1: Framing error |
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Summing error flag (SE) |
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Receive enable bit (RE) |
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0: Receive disabled |
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0: (OE) U (PE) U (FE)=0 |
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1: Receive enabled |
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1: (OE) U (PE) U (FE)=1 |
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Not used (returns “1” when read) |
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Serial I/O1 mode selection bit (SIOM) |
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0: Clock asynchronous (UART) serial I/O |
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1: Clock synchronous serial I/O |
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Serial I/O1 enable bit (SIOE) |
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0: Serial I/O disabled |
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b7 |
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b0 |
UART control register |
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(pins P44 to P47 operate as ordinary I/O pins) |
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(UARTCON : address 001B16) |
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1: Serial I/O enabled |
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Character length selection bit (CHAS) |
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(pins P44 to P47 operate as serial I/O pins) |
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0: 8 bits |
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1: 7 bits |
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Parity enable bit (PARE)
0:Parity checking disabled
1:Parity checking enabled
Parity selection bit (PARS)
0:Even parity
1:Odd parity
Stop bit length selection bit (STPS)
0:1 stop bit
1:2 stop bits
P45/TXD P-channel output disable bit (POFF)
0:CMOS output (in output mode)
1:N-channel open drain output (in output mode)
Not used (return “1” when read)
Fig. 25 Structure of serial I/O1 control registers
29
MITSUBISHI MICROCOMPUTERS
3886 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b7 |
b0 |
The serial I/O2 function can be used only for clock synchronous serial I/O.
For clock synchronous serial I/O the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register.
[Serial I/O2 Control Register (SIO2CON)] 001D16
The serial I/O2 control register contains seven bits which control
various serial I/O functions.
Serial I/O2 control register (SIO2CON : address 001D16)
Internal synchronous clock selection bits
b2 b1 b0
0 0 0: f(XIN)/8 (f(XCIN)/8 in low-speed mode)
00 1: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
01 0: f(XIN)/32 (f(XCIN)/32 in low-speed mode)
01 1: f(XIN)/64 (f(XCIN)/64 in low-speed mode)
11 0: f(XIN)/128 (f(XCIN)/128 in low-speed mode)
11 1: f(XIN)/256 (f(XCIN)/256 in low-speed mode)
Serial I/O2 port selection bit
0:I/O port
1:SOUT2,SCLK2 signal output
SRDY2 output enable bit
0:I/O port
1:SRDY2 signal output
Transfer direction selection bit
0:LSB first
1:MSB first
Serial I/O2 synchronous clock selection bit
0:External clock
1:Internal clock
Comparator reference input selection bit
0:P00/P3REF input
1:Reference input fixed
Fig. 26 Structure of serial I/O2 control register
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Internal synchronous |
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1/8 |
clock selection bits |
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XCIN |
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Main clock divide ratio “10” |
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1/16 |
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Data bus |
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Divider |
1/32 |
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selection bits (Note) |
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1/64 |
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“00” |
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1/128 |
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XIN |
“01” |
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1/256 |
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P73 latch |
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Serial I/O2 synchronous |
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P73/SRDY2 |
“0” |
clock selection bit “1” |
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SRDY2 |
Synchronization |
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/INT21 |
“1” |
circuit |
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SRDY2 output enable bit |
SCLK2 |
“0” |
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External clock |
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P72 latch |
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“0” |
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P72/SCLK2 |
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Serial I/O counter 2 (3) |
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“1” |
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Serial I/O2 port selection bit |
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P71 latch |
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“0” |
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P71/SOUT2 |
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“1” |
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Serial I/O2 port selection bit |
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P70/SIN2 |
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Serial I/O2 register (8) |
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Serial I/O2 interrupt request
Note: These are assigned to bits 7 and 6 of the CPU mode register (address 003B16).
These bits select any of the high-speed mode, the middle-speed mode, and the low-speed mode.
Fig. 27 Block diagram of serial I/O2 function
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