Low Current, High Performance
NPN Silicon Bipolar Transistor
Technical Data
AT-30511
AT-30533
•High Performance Bipolar Transistor Optimized for Low Current, Low Voltage Operation
•900 MHz Performance:
AT-30511:1.1dB NF, 16 dB GA AT-30533:1.1dB NF, 13 dB GA
•Characterized for End-Of- Life Battery Use (2.7 V)
•SOT-23 and SOT-143 SMT Plastic Packages
•Tape-And-Reel Packaging Option Available[1]
EMITTER COLLECTOR
305
BASE EMITTER
SOT-143 (AT-30511)
COLLECTOR
305
BASE EMITTER
SOT-23 (AT-30533)
Note:
1.Refer to “Tape-and-Reel Packaging for Semiconductor Devices”.
Hewlett-Packard’s AT-30511 and AT-30533 are high performance NPN bipolar transistors that have been optimized for maximum fT at low voltage operation, making them ideal for use in battery powered applications in wireless markets. The AT-30533 uses the 3 lead SOT-23, while the AT-30511 places the same die in the higher performance 4 lead SOT-143. Both packages are industry standard, and compatible with high volume surface mount assembly techniques.
The 3.2 micron emitter-to-emitter pitch and reduced parasitic design of these transistors yields extremely high performance products that can perform a multiplicity of tasks. The 5 emitter finger interdigitated geometry yields an extremely fast transistor with high gain and low operating currents.
Optimized performance at 2.7 V makes these devices ideal for use in 900 MHz, 1.8 GHz, and 2.4 GHz battery operated systems as an LNA, gain stage, buffer, oscillator, or active mixer. Typical amplifier designs at 900 MHz yield 1.3 dB noise figures with 13 dB or more associated gain at a 2.7 V, 1 mA bias. Voltage breakdowns are high enough for use at 5 volts. High gain capability at 1 V, 1 mA makes these devices a good fit for
900Ê MHzpagerapplications.
The AT-3 series bipolar transistors are fabricated using an optimized version of HewlettPackard’s
10Ê GHz f, 30 GHz f |
MAX |
Self- |
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Aligned-Transistor (SAT) process. The die are nitride passivated for surface protection. Excellent device uniformity, performance and reliability are produced by the use of ion-implantation, selfalignment techniques, and gold metalization in the fabrication of these devices.
4-23 |
5965-8918E |
Symbol |
Parameter |
Units |
Absolute Maximum[1] |
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Thermal Resistance[2]: |
VEBO |
Emitter-Base Voltage |
V |
1.5 |
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θjc =550°C/W |
VCBO |
Collector-Base Voltage |
V |
11 |
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VCEO |
Collector-Emitter Voltage |
V |
5.5 |
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IC |
Collector Current |
mA |
8 |
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PT |
Power Dissipation[2] [3] |
mW |
100 |
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Tj |
Junction Temperature |
°C |
150 |
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TSTG |
Storage Temperature |
°C |
-65to150 |
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Notes:
1.Operation of this device above any one of these parameters may cause permanent damage.
2.TMounting Surface = 25°C.
3.Derate at 1.82 mW/°C for TC > 95°C.
Electrical Specifications, TA = 25°C
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AT-30511 |
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AT-30533 |
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Symbol |
Parameters and Test Conditions |
Units |
Min |
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Typ |
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Max |
Min |
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Typ |
Max |
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NF |
Noise Figure |
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1.1[1] |
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1.4[1] |
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1.1[2] |
1.4[2] |
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VCE = 2.7 V, IC = 1 mA |
f=0.9GHz |
dB |
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GA |
Associated Gain |
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14[1] |
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16[1] |
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11[2] |
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13[2] |
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VCE = 2.7 V, IC = 1 mA |
f=0.9GHz |
dB |
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hFE |
Forward Current |
VCE =2.7V |
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70 |
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300 |
70 |
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300 |
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Transfer Ratio |
IC = 1 mA |
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ICBO |
Collector Cutoff Current |
VCB = 3 V |
μA |
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0.03 |
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0.2 |
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0.03 |
0.2 |
IEBO |
Emitter Cutoff Current |
VEB = 1 V |
μA |
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0.1 |
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1.5 |
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0.1 |
1.5 |
Notes:
1.Test circuit B, Figure 1. Numbers reflect device performance de-embedded from circuit losses. Input loss = 0.4 dB; output loss = 0.4 dB.
2.Test circuit A, Figure 1. Numbers reflect device performance de-embedded from circuit losses. Input loss = 0.4 dB; output loss = 0.4 dB.
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VBB |
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VCC 25 Ω |
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W = 10 |
L = 1860 |
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W = 10 L = 1860 |
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1000 pF |
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1000 pF |
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W = 10 L = 1000 |
W = 30 |
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W = 30 L = 100 |
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W = 10 L = 1025 |
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L = 100 |
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TEST CIRCUIT |
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TEST CIRCUIT A: W = 20 |
L = 100 |
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BOARD MATL = 0.062" FR-4 (ε = 4.8) |
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TEST CIRCUIT B: W = 20 |
L = 200 x 2 |
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DIMENSIONS IN MILS |
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NOT TO SCALE |
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Figure 1. Test Circuit for Noise Figure and Associated Gain. This Circuit is a
Compromise Match Between Best Noise Figure, Best Gain, Stability, a Practical,
Synthesizable Match, and a Circuit Capable of Matching Both the AT-305 and
AT-310 Geometries.
4-24
AT-30511, AT-30533 Characterization Information, TA = 25°C
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AT-30511 |
AT-30533 |
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Symbol |
Parameters and Test Conditions |
Units |
Typ |
Typ |
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P1dB |
Power at 1 dB Gain Compression (opt tuning) |
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VCE = 2.7 V, IC = 5 mA |
f=0.9GHz |
dBm |
7 |
7 |
G1dB |
Gain at 1 dB Gain Compression (opt tuning) |
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VCE = 2.7 V, IC = 5 mA |
f=0.9GHz |
dB |
16.5 |
15 |
IP3 |
Output Third Order Intercept Point, |
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VCE = 2.7 V, IC = 5 mA (opt tuning) |
f = 0.9 GHz |
dBm |
17 |
17 |
|S21|E2 |
Gain in 50 Ω System; VCE = 2.7 V, IC = 1 mA |
f=0.9GHz |
dB |
10 |
9 |
CCB |
Collector-Base Capacitance |
VCB = 3V, f = 1 MHz |
pF |
0.04 |
0.04 |
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2.5 |
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2.0 |
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(dB) |
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AMPLIFIER NF |
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1.5 |
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FIGURE |
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NOISE |
1.0 |
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NF |
MIN. |
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0.5 |
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1 mA |
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5 mA |
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0 |
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0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
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0 |
FREQUENCY (GHz)
Figure 2. AT-30511 and AT-30533 Minimum Noise Figure and Amplifier NF[1] vs. Frequency and Current at VCEÊ =2 .7 V.
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25 |
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20 |
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5 mA |
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Ga (dB) |
15 |
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10 |
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1 mA |
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5 |
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0 |
0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
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0 |
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FREQUENCY (GHz) |
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Figure 3. AT-30511 Associated Gain at Optimum Noise Match vs. Frequency and Current at VCEÊ = 2 .7 V.
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25 |
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20 |
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5 mA |
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Ga (dB) |
15 |
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10 |
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1 mA |
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5 |
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0 |
0.5 |
1.0 |
1.5 |
2 |
2.5 |
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0 |
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FREQUENCY (GHz) |
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Figure 4. AT-30533 Associated Gain at Optimum Noise Match vs. Frequency and Current at VCEÊ = 2 .7 V.
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10 |
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8 |
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1dB (dBm) |
6 |
5 mA |
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4 |
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P |
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2 |
2 mA |
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0 |
0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
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FREQUENCY (GHz) |
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25 |
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20 |
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5 mA |
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(dBm) |
15 |
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2 mA |
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1dB |
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10 |
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G |
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5 |
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0 |
0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
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FREQUENCY (GHz) |
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25 |
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20 |
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1dB (dBm) |
15 |
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5 mA |
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10 |
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2 mA |
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G |
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5 |
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0 |
0.5 |
1.0 |
1.5 |
2.0 |
2.5 |
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FREQUENCY (GHz) |
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Figure 5. AT-30511 and AT-30533 Power at 1 dB Gain Compression vs. Frequency and Current at VCEÊ = 2.7 V.
Note:
Figure 6. AT-30511 1 dB Compressed Gain vs. Frequency and Current at VCEÊ =2.7 V.
Figure 7. AT-30533 1 dB Compressed Gain vs. Frequency and Current at VCEÊ =2.7 V.
1.Amplifier NF represents the noise figure which can be expected in a real circuit representing reasonable reflection coefficients and including circuit losses.
4-25